2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_common_transform.h"
55 #include "ia32_transform.h"
56 #include "ia32_dbg_stat.h"
57 #include "ia32_util.h"
58 #include "ia32_architecture.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static const arch_env_t *arch_env;
63 static ia32_code_gen_t *cg;
66 * Returns non-zero if the given node produces
69 * @param node the node to check
70 * @param pn if >= 0, the projection number of the used result
72 static int produces_zero_flag(ir_node *node, int pn)
75 const ia32_immediate_attr_t *imm_attr;
77 if (!is_ia32_irn(node))
81 if (pn != pn_ia32_res)
85 switch (get_ia32_irn_opcode(node)) {
103 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
104 assert(n_ia32_Shl_count == n_ia32_Shr_count
105 && n_ia32_Shl_count == n_ia32_Sar_count);
106 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
107 count = get_irn_n(node, n_ia32_ShlD_count);
109 count = get_irn_n(node, n_ia32_Shl_count);
111 /* when shift count is zero the flags are not affected, so we can only
112 * do this for constants != 0 */
113 if (!is_ia32_Immediate(count))
116 imm_attr = get_ia32_immediate_attr_const(count);
117 if (imm_attr->symconst != NULL)
119 if ((imm_attr->offset & 0x1f) == 0)
130 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
132 * @param node the node to change
134 * @return the new mode_T node (if the mode was changed) or node itself
136 static ir_node *turn_into_mode_t(ir_node *node)
141 const arch_register_t *reg;
143 if(get_irn_mode(node) == mode_T)
146 assert(get_irn_mode(node) == mode_Iu);
148 new_node = exact_copy(node);
149 set_irn_mode(new_node, mode_T);
151 block = get_nodes_block(new_node);
152 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
155 reg = arch_get_irn_register(arch_env, node);
156 arch_set_irn_register(arch_env, res_proj, reg);
158 sched_add_before(node, new_node);
159 be_peephole_exchange(node, res_proj);
164 * Peephole optimization for Test instructions.
165 * We can remove the Test, if a zero flags was produced which is still
168 static void peephole_ia32_Test(ir_node *node)
170 ir_node *left = get_irn_n(node, n_ia32_Test_left);
171 ir_node *right = get_irn_n(node, n_ia32_Test_right);
177 const ir_edge_t *edge;
179 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
180 && n_ia32_Test_right == n_ia32_Test8Bit_right);
182 /* we need a test for 0 */
186 block = get_nodes_block(node);
187 if(get_nodes_block(left) != block)
191 pn = get_Proj_proj(left);
192 left = get_Proj_pred(left);
195 /* happens rarely, but if it does code will panic' */
196 if (is_ia32_Unknown_GP(left))
199 /* walk schedule up and abort when we find left or some other node destroys
201 schedpoint = sched_prev(node);
202 while(schedpoint != left) {
203 schedpoint = sched_prev(schedpoint);
204 if(arch_irn_is(arch_env, schedpoint, modify_flags))
206 if(schedpoint == block)
207 panic("couldn't find left");
210 /* make sure only Lg/Eq tests are used */
211 foreach_out_edge(node, edge) {
212 ir_node *user = get_edge_src_irn(edge);
213 int pnc = get_ia32_condcode(user);
215 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
220 if(!produces_zero_flag(left, pn))
223 left = turn_into_mode_t(left);
225 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
226 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
228 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
230 assert(get_irn_mode(node) != mode_T);
232 be_peephole_exchange(node, flags_proj);
236 * AMD Athlon works faster when RET is not destination of
237 * conditional jump or directly preceded by other jump instruction.
238 * Can be avoided by placing a Rep prefix before the return.
240 static void peephole_ia32_Return(ir_node *node) {
241 ir_node *block, *irn;
243 if (!ia32_cg_config.use_pad_return)
246 block = get_nodes_block(node);
248 /* check if this return is the first on the block */
249 sched_foreach_reverse_from(node, irn) {
250 switch (get_irn_opcode(irn)) {
252 /* the return node itself, ignore */
255 /* ignore the barrier, no code generated */
258 /* arg, IncSP 0 nodes might occur, ignore these */
259 if (be_get_IncSP_offset(irn) == 0)
269 /* ensure, that the 3 byte return is generated
270 * actually the emitter tests again if the block beginning has a label and
271 * isn't just a fallthrough */
272 be_Return_set_emit_pop(node, 1);
275 /* only optimize up to 48 stores behind IncSPs */
276 #define MAXPUSH_OPTIMIZE 48
279 * Tries to create Push's from IncSP, Store combinations.
280 * The Stores are replaced by Push's, the IncSP is modified
281 * (possibly into IncSP 0, but not removed).
283 static void peephole_IncSP_Store_to_push(ir_node *irn)
285 int i, maxslot, inc_ofs;
287 ir_node *stores[MAXPUSH_OPTIMIZE];
293 memset(stores, 0, sizeof(stores));
295 assert(be_is_IncSP(irn));
297 inc_ofs = be_get_IncSP_offset(irn);
302 * We first walk the schedule after the IncSP node as long as we find
303 * suitable Stores that could be transformed to a Push.
304 * We save them into the stores array which is sorted by the frame offset/4
305 * attached to the node
308 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
313 /* it has to be a Store */
314 if (!is_ia32_Store(node))
317 /* it has to use our sp value */
318 if (get_irn_n(node, n_ia32_base) != irn)
320 /* Store has to be attached to NoMem */
321 mem = get_irn_n(node, n_ia32_mem);
325 /* unfortunately we can't support the full AMs possible for push at the
326 * moment. TODO: fix this */
327 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
330 offset = get_ia32_am_offs_int(node);
331 /* we should NEVER access uninitialized stack BELOW the current SP */
334 offset = inc_ofs - 4 - offset;
336 /* storing at half-slots is bad */
337 if ((offset & 3) != 0)
340 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
342 storeslot = offset >> 2;
344 /* storing into the same slot twice is bad (and shouldn't happen...) */
345 if (stores[storeslot] != NULL)
348 stores[storeslot] = node;
349 if (storeslot > maxslot)
353 curr_sp = be_get_IncSP_pred(irn);
355 /* walk through the Stores and create Pushs for them */
356 block = get_nodes_block(irn);
357 spmode = get_irn_mode(irn);
359 for (i = 0; i <= maxslot; ++i) {
360 const arch_register_t *spreg;
362 ir_node *val, *mem, *mem_proj;
363 ir_node *store = stores[i];
364 ir_node *noreg = ia32_new_NoReg_gp(cg);
369 val = get_irn_n(store, n_ia32_unary_op);
370 mem = get_irn_n(store, n_ia32_mem);
371 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
373 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
375 sched_add_before(irn, push);
377 /* create stackpointer Proj */
378 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
379 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
381 /* create memory Proj */
382 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
384 /* use the memproj now */
385 be_peephole_exchange(store, mem_proj);
390 be_set_IncSP_offset(irn, inc_ofs);
391 be_set_IncSP_pred(irn, curr_sp);
395 * Return true if a mode can be stored in the GP register set
397 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
398 if (mode == mode_fpcw)
400 if (get_mode_size_bits(mode) > 32)
402 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
406 * Tries to create Pops from Load, IncSP combinations.
407 * The Loads are replaced by Pops, the IncSP is modified
408 * (possibly into IncSP 0, but not removed).
410 static void peephole_Load_IncSP_to_pop(ir_node *irn)
412 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
413 int i, maxslot, inc_ofs, ofs;
414 ir_node *node, *pred_sp, *block;
415 ir_node *loads[MAXPUSH_OPTIMIZE];
417 unsigned regmask = 0;
418 unsigned copymask = ~0;
420 memset(loads, 0, sizeof(loads));
421 assert(be_is_IncSP(irn));
423 inc_ofs = -be_get_IncSP_offset(irn);
428 * We first walk the schedule before the IncSP node as long as we find
429 * suitable Loads that could be transformed to a Pop.
430 * We save them into the stores array which is sorted by the frame offset/4
431 * attached to the node
434 pred_sp = be_get_IncSP_pred(irn);
435 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
439 const arch_register_t *sreg, *dreg;
441 /* it has to be a Load */
442 if (!is_ia32_Load(node)) {
443 if (be_is_Copy(node)) {
444 if (!mode_needs_gp_reg(get_irn_mode(node))) {
445 /* not a GP copy, ignore */
448 dreg = arch_get_irn_register(arch_env, node);
449 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
450 if (regmask & copymask & (1 << sreg->index)) {
453 if (regmask & copymask & (1 << dreg->index)) {
456 /* we CAN skip Copies if neither the destination nor the source
457 * is not in our regmask, ie none of our future Pop will overwrite it */
458 regmask |= (1 << dreg->index) | (1 << sreg->index);
459 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
465 /* we can handle only GP loads */
466 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
469 /* it has to use our predecessor sp value */
470 if (get_irn_n(node, n_ia32_base) != pred_sp) {
471 /* it would be ok if this load does not use a Pop result,
472 * but we do not check this */
475 /* Load has to be attached to Spill-Mem */
476 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
477 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
480 /* should have NO index */
481 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
484 offset = get_ia32_am_offs_int(node);
485 /* we should NEVER access uninitialized stack BELOW the current SP */
488 /* storing at half-slots is bad */
489 if ((offset & 3) != 0)
492 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
494 /* ignore those outside the possible windows */
495 if (offset > inc_ofs - 4)
497 loadslot = offset >> 2;
499 /* loading from the same slot twice is bad (and shouldn't happen...) */
500 if (loads[loadslot] != NULL)
503 dreg = arch_get_irn_register(arch_env, node);
504 if (regmask & (1 << dreg->index)) {
505 /* this register is already used */
508 regmask |= 1 << dreg->index;
510 loads[loadslot] = node;
511 if (loadslot > maxslot)
518 /* find the first slot */
519 for (i = maxslot; i >= 0; --i) {
520 ir_node *load = loads[i];
526 ofs = inc_ofs - (maxslot + 1) * 4;
529 /* create a new IncSP if needed */
530 block = get_nodes_block(irn);
533 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
534 sched_add_before(irn, pred_sp);
537 /* walk through the Loads and create Pops for them */
538 for (++i; i <= maxslot; ++i) {
539 ir_node *load = loads[i];
541 const ir_edge_t *edge, *tmp;
542 const arch_register_t *reg;
544 mem = get_irn_n(load, n_ia32_mem);
545 reg = arch_get_irn_register(arch_env, load);
547 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
548 arch_set_irn_register(arch_env, pop, reg);
550 /* create stackpointer Proj */
551 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
552 arch_set_irn_register(arch_env, pred_sp, esp);
554 sched_add_before(irn, pop);
557 foreach_out_edge_safe(load, edge, tmp) {
558 ir_node *proj = get_edge_src_irn(edge);
560 set_Proj_pred(proj, pop);
563 /* we can remove the Load now */
568 be_set_IncSP_offset(irn, -ofs);
569 be_set_IncSP_pred(irn, pred_sp);
574 * Find a free GP register if possible, else return NULL.
576 static const arch_register_t *get_free_gp_reg(void)
580 for(i = 0; i < N_ia32_gp_REGS; ++i) {
581 const arch_register_t *reg = &ia32_gp_regs[i];
582 if(arch_register_type_is(reg, ignore))
585 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
586 return &ia32_gp_regs[i];
593 * Creates a Pop instruction before the given schedule point.
595 * @param dbgi debug info
596 * @param irg the graph
597 * @param block the block
598 * @param stack the previous stack value
599 * @param schedpoint the new node is added before this node
600 * @param reg the register to pop
602 * @return the new stack value
604 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
605 ir_node *stack, ir_node *schedpoint,
606 const arch_register_t *reg)
608 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
614 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
616 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
617 arch_set_irn_register(arch_env, stack, esp);
618 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
619 arch_set_irn_register(arch_env, val, reg);
621 sched_add_before(schedpoint, pop);
624 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
625 sched_add_before(schedpoint, keep);
631 * Creates a Push instruction before the given schedule point.
633 * @param dbgi debug info
634 * @param irg the graph
635 * @param block the block
636 * @param stack the previous stack value
637 * @param schedpoint the new node is added before this node
638 * @param reg the register to pop
640 * @return the new stack value
642 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
643 ir_node *stack, ir_node *schedpoint)
645 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
647 ir_node *val = ia32_new_Unknown_gp(cg);
648 ir_node *noreg = ia32_new_NoReg_gp(cg);
649 ir_node *nomem = get_irg_no_mem(irg);
650 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
651 sched_add_before(schedpoint, push);
653 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
654 arch_set_irn_register(arch_env, stack, esp);
660 * Optimize an IncSp by replacing it with Push/Pop.
662 static void peephole_be_IncSP(ir_node *node)
664 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
665 const arch_register_t *reg;
666 ir_graph *irg = current_ir_graph;
672 /* first optimize incsp->incsp combinations */
673 node = be_peephole_IncSP_IncSP(node);
675 /* transform IncSP->Store combinations to Push where possible */
676 peephole_IncSP_Store_to_push(node);
678 /* transform Load->IncSP combinations to Pop where possible */
679 peephole_Load_IncSP_to_pop(node);
681 if (arch_get_irn_register(arch_env, node) != esp)
684 /* replace IncSP -4 by Pop freereg when possible */
685 offset = be_get_IncSP_offset(node);
686 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
687 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
688 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
689 (offset != +8 || ia32_cg_config.use_sub_esp_8))
693 /* we need a free register for pop */
694 reg = get_free_gp_reg();
698 dbgi = get_irn_dbg_info(node);
699 block = get_nodes_block(node);
700 stack = be_get_IncSP_pred(node);
702 stack = create_pop(dbgi, irg, block, stack, node, reg);
705 stack = create_pop(dbgi, irg, block, stack, node, reg);
708 dbgi = get_irn_dbg_info(node);
709 block = get_nodes_block(node);
710 stack = be_get_IncSP_pred(node);
711 stack = create_push(dbgi, irg, block, stack, node);
714 stack = create_push(dbgi, irg, block, stack, node);
718 be_peephole_exchange(node, stack);
722 * Peephole optimisation for ia32_Const's
724 static void peephole_ia32_Const(ir_node *node)
726 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
727 const arch_register_t *reg;
728 ir_graph *irg = current_ir_graph;
735 /* try to transform a mov 0, reg to xor reg reg */
736 if (attr->offset != 0 || attr->symconst != NULL)
738 if (ia32_cg_config.use_mov_0)
740 /* xor destroys the flags, so no-one must be using them */
741 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
744 reg = arch_get_irn_register(arch_env, node);
745 assert(be_peephole_get_reg_value(reg) == NULL);
747 /* create xor(produceval, produceval) */
748 block = get_nodes_block(node);
749 dbgi = get_irn_dbg_info(node);
750 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
751 arch_set_irn_register(arch_env, produceval, reg);
753 noreg = ia32_new_NoReg_gp(cg);
754 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
755 produceval, produceval);
756 arch_set_irn_register(arch_env, xor, reg);
758 sched_add_before(node, produceval);
759 sched_add_before(node, xor);
761 be_peephole_exchange(node, xor);
764 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
766 return node == cg->noreg_gp;
769 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
771 ir_graph *irg = current_ir_graph;
772 ir_node *start_block = get_irg_start_block(irg);
773 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
775 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
780 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
783 ir_graph *irg = get_irn_irg(node);
784 ir_node *block = get_nodes_block(node);
785 int offset = get_ia32_am_offs_int(node);
786 int sc_sign = is_ia32_am_sc_sign(node);
787 ir_entity *entity = get_ia32_am_sc(node);
790 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
791 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
795 static int is_am_one(const ir_node *node)
797 int offset = get_ia32_am_offs_int(node);
798 ir_entity *entity = get_ia32_am_sc(node);
800 return offset == 1 && entity == NULL;
803 static int is_am_minus_one(const ir_node *node)
805 int offset = get_ia32_am_offs_int(node);
806 ir_entity *entity = get_ia32_am_sc(node);
808 return offset == -1 && entity == NULL;
812 * Transforms a LEA into an Add or SHL if possible.
814 static void peephole_ia32_Lea(ir_node *node)
816 const arch_env_t *arch_env = cg->arch_env;
817 ir_graph *irg = current_ir_graph;
820 const arch_register_t *base_reg;
821 const arch_register_t *index_reg;
822 const arch_register_t *out_reg;
833 assert(is_ia32_Lea(node));
835 /* we can only do this if are allowed to globber the flags */
836 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
839 base = get_irn_n(node, n_ia32_Lea_base);
840 index = get_irn_n(node, n_ia32_Lea_index);
842 if(is_noreg(cg, base)) {
846 base_reg = arch_get_irn_register(arch_env, base);
848 if(is_noreg(cg, index)) {
852 index_reg = arch_get_irn_register(arch_env, index);
855 if(base == NULL && index == NULL) {
856 /* we shouldn't construct these in the first place... */
858 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
863 out_reg = arch_get_irn_register(arch_env, node);
864 scale = get_ia32_am_scale(node);
865 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
866 /* check if we have immediates values (frame entities should already be
867 * expressed in the offsets) */
868 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
874 /* we can transform leas where the out register is the same as either the
875 * base or index register back to an Add or Shl */
876 if(out_reg == base_reg) {
879 if(!has_immediates) {
880 ir_fprintf(stderr, "Optimisation warning: found lea which is "
885 goto make_add_immediate;
887 if(scale == 0 && !has_immediates) {
892 /* can't create an add */
894 } else if(out_reg == index_reg) {
896 if(has_immediates && scale == 0) {
898 goto make_add_immediate;
899 } else if(!has_immediates && scale > 0) {
901 op2 = create_immediate_from_int(cg, scale);
903 } else if(!has_immediates) {
905 ir_fprintf(stderr, "Optimisation warning: found lea which is "
909 } else if(scale == 0 && !has_immediates) {
914 /* can't create an add */
917 /* can't create an add */
922 if(ia32_cg_config.use_incdec) {
923 if(is_am_one(node)) {
924 dbgi = get_irn_dbg_info(node);
925 block = get_nodes_block(node);
926 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
927 arch_set_irn_register(arch_env, res, out_reg);
930 if(is_am_minus_one(node)) {
931 dbgi = get_irn_dbg_info(node);
932 block = get_nodes_block(node);
933 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
934 arch_set_irn_register(arch_env, res, out_reg);
938 op2 = create_immediate_from_am(cg, node);
941 dbgi = get_irn_dbg_info(node);
942 block = get_nodes_block(node);
943 noreg = ia32_new_NoReg_gp(cg);
945 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
946 arch_set_irn_register(arch_env, res, out_reg);
947 set_ia32_commutative(res);
951 dbgi = get_irn_dbg_info(node);
952 block = get_nodes_block(node);
953 noreg = ia32_new_NoReg_gp(cg);
955 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
956 arch_set_irn_register(arch_env, res, out_reg);
960 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
962 /* add new ADD/SHL to schedule */
963 DBG_OPT_LEA2ADD(node, res);
965 /* exchange the Add and the LEA */
966 sched_add_before(node, res);
967 be_peephole_exchange(node, res);
971 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
973 static void peephole_ia32_Imul_split(ir_node *imul) {
974 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
975 const arch_register_t *reg;
976 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
980 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
981 /* no memory, imm form ignore */
984 /* we need a free register */
985 reg = get_free_gp_reg();
989 /* fine, we can rebuild it */
990 dbgi = get_irn_dbg_info(imul);
991 block = get_nodes_block(imul);
992 irg = current_ir_graph;
993 base = get_irn_n(imul, n_ia32_IMul_base);
994 index = get_irn_n(imul, n_ia32_IMul_index);
995 mem = get_irn_n(imul, n_ia32_IMul_mem);
996 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
998 /* copy all attributes */
999 set_irn_pinned(load, get_irn_pinned(imul));
1000 set_ia32_op_type(load, ia32_AddrModeS);
1001 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1003 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1004 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1005 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1006 if (is_ia32_am_sc_sign(imul))
1007 set_ia32_am_sc_sign(load);
1008 if (is_ia32_use_frame(imul))
1009 set_ia32_use_frame(load);
1010 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1012 sched_add_before(imul, load);
1014 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1015 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1017 arch_set_irn_register(arch_env, res, reg);
1018 be_peephole_new_node(res);
1020 set_irn_n(imul, n_ia32_IMul_mem, mem);
1021 noreg = get_irn_n(imul, n_ia32_IMul_left);
1022 set_irn_n(imul, n_ia32_IMul_left, res);
1023 set_ia32_op_type(imul, ia32_Normal);
1027 * Replace xorps r,r and xorpd r,r by pxor r,r
1029 static void peephole_ia32_xZero(ir_node *xor) {
1030 set_irn_op(xor, op_ia32_xPzero);
1034 * Register a peephole optimisation function.
1036 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1037 assert(op->ops.generic == NULL);
1038 op->ops.generic = (op_func)func;
1041 /* Perform peephole-optimizations. */
1042 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1045 arch_env = cg->arch_env;
1047 /* register peephole optimisations */
1048 clear_irp_opcodes_generic_func();
1049 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1050 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1051 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1052 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1053 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1054 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1055 if (! ia32_cg_config.use_imul_mem_imm32)
1056 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1057 if (ia32_cg_config.use_pxor)
1058 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1060 be_peephole_opt(cg->birg);
1064 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1065 * all it's Projs are removed as well.
1066 * @param irn The irn to be removed from schedule
1068 static INLINE void try_kill(ir_node *node)
1070 if(get_irn_mode(node) == mode_T) {
1071 const ir_edge_t *edge, *next;
1072 foreach_out_edge_safe(node, edge, next) {
1073 ir_node *proj = get_edge_src_irn(edge);
1078 if(get_irn_n_edges(node) != 0)
1081 if (sched_is_scheduled(node)) {
1088 static void optimize_conv_store(ir_node *node)
1093 ir_mode *store_mode;
1095 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1098 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1099 pred_proj = get_irn_n(node, n_ia32_Store_val);
1100 if(is_Proj(pred_proj)) {
1101 pred = get_Proj_pred(pred_proj);
1105 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1107 if(get_ia32_op_type(pred) != ia32_Normal)
1110 /* the store only stores the lower bits, so we only need the conv
1111 * it it shrinks the mode */
1112 conv_mode = get_ia32_ls_mode(pred);
1113 store_mode = get_ia32_ls_mode(node);
1114 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1117 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1118 if(get_irn_n_edges(pred_proj) == 0) {
1119 kill_node(pred_proj);
1120 if(pred != pred_proj)
1125 static void optimize_load_conv(ir_node *node)
1127 ir_node *pred, *predpred;
1131 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1134 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1135 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1139 predpred = get_Proj_pred(pred);
1140 if(!is_ia32_Load(predpred))
1143 /* the load is sign extending the upper bits, so we only need the conv
1144 * if it shrinks the mode */
1145 load_mode = get_ia32_ls_mode(predpred);
1146 conv_mode = get_ia32_ls_mode(node);
1147 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1150 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1151 /* change the load if it has only 1 user */
1152 if(get_irn_n_edges(pred) == 1) {
1154 if(get_mode_sign(conv_mode)) {
1155 newmode = find_signed_mode(load_mode);
1157 newmode = find_unsigned_mode(load_mode);
1159 assert(newmode != NULL);
1160 set_ia32_ls_mode(predpred, newmode);
1162 /* otherwise we have to keep the conv */
1168 exchange(node, pred);
1171 static void optimize_conv_conv(ir_node *node)
1173 ir_node *pred_proj, *pred, *result_conv;
1174 ir_mode *pred_mode, *conv_mode;
1178 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1181 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1182 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1183 if(is_Proj(pred_proj))
1184 pred = get_Proj_pred(pred_proj);
1188 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1191 /* we know that after a conv, the upper bits are sign extended
1192 * so we only need the 2nd conv if it shrinks the mode */
1193 conv_mode = get_ia32_ls_mode(node);
1194 conv_mode_bits = get_mode_size_bits(conv_mode);
1195 pred_mode = get_ia32_ls_mode(pred);
1196 pred_mode_bits = get_mode_size_bits(pred_mode);
1198 if(conv_mode_bits == pred_mode_bits
1199 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1200 result_conv = pred_proj;
1201 } else if(conv_mode_bits <= pred_mode_bits) {
1202 /* if 2nd conv is smaller then first conv, then we can always take the
1204 if(get_irn_n_edges(pred_proj) == 1) {
1205 result_conv = pred_proj;
1206 set_ia32_ls_mode(pred, conv_mode);
1208 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1209 if (get_mode_size_bits(conv_mode) == 8) {
1210 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1211 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1214 /* we don't want to end up with 2 loads, so we better do nothing */
1215 if(get_irn_mode(pred) == mode_T) {
1219 result_conv = exact_copy(pred);
1220 set_ia32_ls_mode(result_conv, conv_mode);
1222 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1223 if (get_mode_size_bits(conv_mode) == 8) {
1224 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1225 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1229 /* if both convs have the same sign, then we can take the smaller one */
1230 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1231 result_conv = pred_proj;
1233 /* no optimisation possible if smaller conv is sign-extend */
1234 if(mode_is_signed(pred_mode)) {
1237 /* we can take the smaller conv if it is unsigned */
1238 result_conv = pred_proj;
1243 exchange(node, result_conv);
1245 if(get_irn_n_edges(pred_proj) == 0) {
1246 kill_node(pred_proj);
1247 if(pred != pred_proj)
1250 optimize_conv_conv(result_conv);
1253 static void optimize_node(ir_node *node, void *env)
1257 optimize_load_conv(node);
1258 optimize_conv_store(node);
1259 optimize_conv_conv(node);
1263 * Performs conv and address mode optimization.
1265 void ia32_optimize_graph(ia32_code_gen_t *cg)
1267 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1270 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1273 void ia32_init_optimize(void)
1275 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");