2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Christian Wuerdig
33 #include "firm_types.h"
43 #include "../benode_t.h"
44 #include "../besched_t.h"
46 #include "ia32_new_nodes.h"
47 #include "bearch_ia32_t.h"
48 #include "gen_ia32_regalloc_if_t.h"
49 #include "ia32_transform.h"
50 #include "ia32_dbg_stat.h"
51 #include "ia32_util.h"
53 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
59 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
60 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
61 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
64 typedef int is_op_func_t(const ir_node *n);
65 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
68 * checks if a node represents the NOREG value
70 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
71 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
74 /********************************************************************************************************
75 * _____ _ _ ____ _ _ _ _ _
76 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
77 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
78 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
79 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
80 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
83 ********************************************************************************************************/
86 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
89 static int ia32_const_equal(const ir_node *n1, const ir_node *n2) {
90 if(get_ia32_immop_type(n1) != get_ia32_immop_type(n2))
93 if(get_ia32_immop_type(n1) == ia32_ImmConst) {
94 return get_ia32_Immop_tarval(n1) == get_ia32_Immop_tarval(n2);
95 } else if(get_ia32_immop_type(n1) == ia32_ImmSymConst) {
96 return get_ia32_Immop_symconst(n1) == get_ia32_Immop_symconst(n2);
99 assert(get_ia32_immop_type(n1) == ia32_ImmNone);
104 * Checks for potential CJmp/CJmpAM optimization candidates.
106 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
107 ir_node *cand = NULL;
108 ir_node *prev = sched_prev(irn);
110 if (is_Block(prev)) {
111 if (get_Block_n_cfgpreds(prev) == 1)
112 prev = get_Block_cfgpred(prev, 0);
117 /* The predecessor must be a ProjX. */
118 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
119 prev = get_Proj_pred(prev);
121 if (is_op_func(prev))
128 static int is_TestJmp_cand(const ir_node *irn) {
129 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
133 * Checks if two consecutive arguments of cand matches
134 * the two arguments of irn (TestJmp).
136 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
137 ir_node *in1 = get_irn_n(irn, 0);
138 ir_node *in2 = get_irn_n(irn, 1);
139 int i, n = get_irn_arity(cand);
142 for (i = 0; i < n - 1; i++) {
143 if (get_irn_n(cand, i) == in1 &&
144 get_irn_n(cand, i + 1) == in2)
154 return ia32_const_equal(cand, irn);
158 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
160 static void ia32_optimize_TestJmp(ir_node *irn)
162 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
165 /* we found a possible candidate */
166 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
169 DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
171 if (is_ia32_And(cand))
172 set_irn_op(irn, op_ia32_CJmpAM);
174 set_irn_op(irn, op_ia32_CJmp);
176 DB((dbg, LEVEL_1, "%+F\n", irn));
180 static int is_CondJmp_cand(const ir_node *irn) {
181 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
185 * Checks if the arguments of cand are the same of irn.
187 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
190 arity = get_irn_arity(cand);
191 for (i = 0; i < arity; i++) {
192 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
197 return ia32_const_equal(cand, irn);
201 * Tries to replace a CondJmp by a CJmpAM
203 static void ia32_optimize_CondJmp(ir_node *irn)
205 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
208 /* we found a possible candidate */
209 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
212 DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
215 set_irn_op(irn, op_ia32_CJmpAM);
217 DB((dbg, LEVEL_1, "%+F\n", irn));
221 // only optimize up to 48 stores behind IncSPs
222 #define MAXPUSH_OPTIMIZE 48
225 * Tries to create pushs from IncSP,Store combinations
227 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
231 ir_node *stores[MAXPUSH_OPTIMIZE];
232 ir_node *block = get_nodes_block(irn);
233 ir_graph *irg = cg->irg;
235 ir_mode *spmode = get_irn_mode(irn);
237 memset(stores, 0, sizeof(stores));
239 assert(be_is_IncSP(irn));
241 offset = be_get_IncSP_offset(irn);
246 * We first walk the schedule after the IncSP node as long as we find
247 * suitable stores that could be transformed to a push.
248 * We save them into the stores array which is sorted by the frame offset/4
249 * attached to the node
251 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
256 // it has to be a store
257 if(!is_ia32_Store(node))
260 // it has to use our sp value
261 if(get_irn_n(node, 0) != irn)
263 // store has to be attached to NoMem
264 mem = get_irn_n(node, 3);
269 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
272 offset = get_ia32_am_offs_int(node);
274 storeslot = offset / 4;
275 if(storeslot >= MAXPUSH_OPTIMIZE)
278 // storing into the same slot twice is bad (and shouldn't happen...)
279 if(stores[storeslot] != NULL)
282 // storing at half-slots is bad
286 stores[storeslot] = node;
289 curr_sp = get_irn_n(irn, 0);
291 // walk the stores in inverse order and create pushs for them
292 i = (offset / 4) - 1;
293 if(i >= MAXPUSH_OPTIMIZE) {
294 i = MAXPUSH_OPTIMIZE - 1;
297 for( ; i >= 0; --i) {
298 const arch_register_t *spreg;
300 ir_node *val, *mem, *mem_proj;
301 ir_node *store = stores[i];
302 ir_node *noreg = ia32_new_NoReg_gp(cg);
304 if(store == NULL || is_Bad(store))
307 val = get_irn_n(store, 2);
308 mem = get_irn_n(store, 3);
309 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
312 push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
314 set_ia32_am_support(push, ia32_am_Source);
315 copy_ia32_Immop_attr(push, store);
317 sched_add_before(irn, push);
319 // create stackpointer proj
320 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
321 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
322 sched_add_before(irn, curr_sp);
324 // create memory proj
325 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
327 // use the memproj now
328 exchange(store, mem_proj);
330 // we can remove the store now
336 be_set_IncSP_offset(irn, offset);
338 // can we remove the IncSP now?
340 const ir_edge_t *edge, *next;
342 foreach_out_edge_safe(irn, edge, next) {
343 ir_node *arg = get_edge_src_irn(edge);
344 int pos = get_edge_src_pos(edge);
346 set_irn_n(arg, pos, curr_sp);
349 set_irn_n(irn, 0, new_Bad());
352 set_irn_n(irn, 0, curr_sp);
358 * Tries to optimize two following IncSP.
360 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
361 ir_node *prev = be_get_IncSP_pred(irn);
362 int real_uses = get_irn_n_edges(prev);
364 if (be_is_IncSP(prev) && real_uses == 1) {
365 /* first IncSP has only one IncSP user, kill the first one */
366 int prev_offs = be_get_IncSP_offset(prev);
367 int curr_offs = be_get_IncSP_offset(irn);
369 be_set_IncSP_offset(prev, prev_offs + curr_offs);
371 /* Omit the optimized IncSP */
372 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
374 set_irn_n(prev, 0, new_Bad());
381 * Performs Peephole Optimizations.
383 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
384 ia32_code_gen_t *cg = env;
386 /* AMD CPUs want explicit compare before conditional jump */
387 if (! ARCH_AMD(cg->opt_arch)) {
388 if (is_ia32_TestJmp(irn))
389 ia32_optimize_TestJmp(irn);
390 else if (is_ia32_CondJmp(irn))
391 ia32_optimize_CondJmp(irn);
394 if (be_is_IncSP(irn)) {
395 // optimize_IncSP doesn't respect dependency edges yet...
396 //ia32_optimize_IncSP(irn, cg);
398 if (cg->opt & IA32_OPT_PUSHARGS)
399 ia32_create_Pushs(irn, cg);
403 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
404 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
407 /******************************************************************
409 * /\ | | | | | \/ | | |
410 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
411 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
412 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
413 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
415 ******************************************************************/
422 static int node_is_ia32_comm(const ir_node *irn) {
423 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
426 static int ia32_get_irn_n_edges(const ir_node *irn) {
427 const ir_edge_t *edge;
430 foreach_out_edge(irn, edge) {
438 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
440 * @param pred The node to be checked
441 * @param is_op_func The check-function
442 * @return 1 if conditions are fulfilled, 0 otherwise
444 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
445 return is_op_func(pred);
449 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
450 * and if the predecessor is in block bl.
452 * @param bl The block
453 * @param pred The node to be checked
454 * @param is_op_func The check-function
455 * @return 1 if conditions are fulfilled, 0 otherwise
457 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
458 int (*is_op_func)(const ir_node *n))
461 pred = get_Proj_pred(pred);
462 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
471 * Checks if irn is a candidate for address calculation. We avoid transforming
472 * adds to leas if they have a load as pred, because then we can use AM mode
475 * - none of the operand must be a Load within the same block OR
476 * - all Loads must have more than one user OR
478 * @param block The block the Loads must/mustnot be in
479 * @param irn The irn to check
480 * return 1 if irn is a candidate, 0 otherwise
482 static int is_addr_candidate(const ir_node *irn)
484 #ifndef AGGRESSIVE_AM
485 const ir_node *block = get_nodes_block(irn);
486 ir_node *left, *right;
489 left = get_irn_n(irn, 2);
490 right = get_irn_n(irn, 3);
492 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
493 n = ia32_get_irn_n_edges(left);
494 /* load with only one user: don't create LEA */
499 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
500 n = ia32_get_irn_n_edges(right);
511 * Checks if irn is a candidate for address mode.
514 * - at least one operand has to be a Load within the same block AND
515 * - the load must not have other users than the irn AND
516 * - the irn must not have a frame entity set
518 * @param cg The ia32 code generator
519 * @param h The height information of the irg
520 * @param block The block the Loads must/mustnot be in
521 * @param irn The irn to check
522 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
524 static ia32_am_cand_t is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
525 ir_node *in, *load, *other, *left, *right;
526 int is_cand = 0, cand;
529 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
530 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
533 if(get_ia32_frame_ent(irn) != NULL)
534 return IA32_AM_CAND_NONE;
536 left = get_irn_n(irn, 2);
537 arity = get_irn_arity(irn);
538 assert(arity == 5 || arity == 4);
541 right = get_irn_n(irn, 3);
549 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
550 #ifndef AGGRESSIVE_AM
552 n = ia32_get_irn_n_edges(in);
553 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
558 load = get_Proj_pred(in);
561 /* 8bit Loads are not supported (for binary ops),
562 * they cannot be used with every register */
563 if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
564 assert(get_irn_arity(irn) == 5);
568 /* If there is a data dependency of other irn from load: cannot use AM */
569 if (is_cand && get_nodes_block(other) == block) {
570 other = skip_Proj(other);
571 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
572 /* this could happen in loops */
573 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
577 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
581 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
582 #ifndef AGGRESSIVE_AM
584 n = ia32_get_irn_n_edges(in);
585 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
590 load = get_Proj_pred(in);
593 /* 8bit Loads are not supported, they cannot be used with every register */
594 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
597 /* If there is a data dependency of other irn from load: cannot use load */
598 if (is_cand && get_nodes_block(other) == block) {
599 other = skip_Proj(other);
600 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
601 /* this could happen in loops */
602 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
606 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
608 /* if the irn has a frame entity: we do not use address mode */
613 * Compares the base and index addr and the load/store entities
614 * and returns 1 if they are equal.
616 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
617 const ir_node *addr_b, const ir_node *addr_i)
619 if(get_irn_n(load, 0) != addr_b)
621 if(get_irn_n(load, 1) != addr_i)
624 if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
627 if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
629 if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
631 if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
633 if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
639 typedef enum _ia32_take_lea_attr {
640 IA32_LEA_ATTR_NONE = 0,
641 IA32_LEA_ATTR_BASE = (1 << 0),
642 IA32_LEA_ATTR_INDEX = (1 << 1),
643 IA32_LEA_ATTR_OFFS = (1 << 2),
644 IA32_LEA_ATTR_SCALE = (1 << 3),
645 IA32_LEA_ATTR_AMSC = (1 << 4),
646 IA32_LEA_ATTR_FENT = (1 << 5)
647 } ia32_take_lea_attr;
650 * Decides if we have to keep the LEA operand or if we can assimilate it.
652 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
653 int have_am_sc, ia32_code_gen_t *cg)
655 ir_entity *irn_ent = get_ia32_frame_ent(irn);
656 ir_entity *lea_ent = get_ia32_frame_ent(lea);
658 int is_noreg_base = be_is_NoReg(cg, base);
659 int is_noreg_index = be_is_NoReg(cg, index);
660 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
662 /* If the Add and the LEA both have a different frame entity set: keep */
663 if (irn_ent && lea_ent && (irn_ent != lea_ent))
664 return IA32_LEA_ATTR_NONE;
665 else if (! irn_ent && lea_ent)
666 ret_val |= IA32_LEA_ATTR_FENT;
668 /* If the Add and the LEA both have already an address mode symconst: keep */
669 if (have_am_sc && get_ia32_am_sc(lea))
670 return IA32_LEA_ATTR_NONE;
671 else if (get_ia32_am_sc(lea))
672 ret_val |= IA32_LEA_ATTR_AMSC;
674 /* Check the different base-index combinations */
676 if (! is_noreg_base && ! is_noreg_index) {
677 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
678 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
679 if (am_flav & ia32_O)
680 ret_val |= IA32_LEA_ATTR_OFFS;
682 ret_val |= IA32_LEA_ATTR_BASE;
685 return IA32_LEA_ATTR_NONE;
687 else if (! is_noreg_base && is_noreg_index) {
688 /* Base is set but index not */
690 /* Base points to LEA: assimilate everything */
691 if (am_flav & ia32_O)
692 ret_val |= IA32_LEA_ATTR_OFFS;
693 if (am_flav & ia32_S)
694 ret_val |= IA32_LEA_ATTR_SCALE;
695 if (am_flav & ia32_I)
696 ret_val |= IA32_LEA_ATTR_INDEX;
698 ret_val |= IA32_LEA_ATTR_BASE;
700 else if (am_flav & ia32_B ? 0 : 1) {
701 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
702 if (am_flav & ia32_O)
703 ret_val |= IA32_LEA_ATTR_OFFS;
704 if (am_flav & ia32_S)
705 ret_val |= IA32_LEA_ATTR_SCALE;
707 ret_val |= IA32_LEA_ATTR_INDEX;
710 return IA32_LEA_ATTR_NONE;
712 else if (is_noreg_base && ! is_noreg_index) {
713 /* Index is set but not base */
715 /* Index points to LEA: assimilate everything */
716 if (am_flav & ia32_O)
717 ret_val |= IA32_LEA_ATTR_OFFS;
718 if (am_flav & ia32_S)
719 ret_val |= IA32_LEA_ATTR_SCALE;
720 if (am_flav & ia32_B)
721 ret_val |= IA32_LEA_ATTR_BASE;
723 ret_val |= IA32_LEA_ATTR_INDEX;
725 else if (am_flav & ia32_I ? 0 : 1) {
726 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
727 if (am_flav & ia32_O)
728 ret_val |= IA32_LEA_ATTR_OFFS;
729 if (am_flav & ia32_S)
730 ret_val |= IA32_LEA_ATTR_SCALE;
732 ret_val |= IA32_LEA_ATTR_BASE;
735 return IA32_LEA_ATTR_NONE;
738 assert(0 && "There must have been set base or index");
745 * Adds res before irn into schedule if irn was scheduled.
746 * @param irn The schedule point
747 * @param res The node to be scheduled
749 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
750 if (sched_is_scheduled(irn))
751 sched_add_before(irn, res);
755 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
756 * all it's Projs are removed as well.
757 * @param irn The irn to be removed from schedule
759 static INLINE void try_remove_from_sched(ir_node *node) {
762 if(get_irn_mode(node) == mode_T) {
763 const ir_edge_t *edge, *next;
764 foreach_out_edge_safe(node, edge, next) {
765 ir_node *proj = get_edge_src_irn(edge);
766 try_remove_from_sched(proj);
770 if(get_irn_n_edges(node) != 0)
773 if (sched_is_scheduled(node)) {
777 arity = get_irn_arity(node);
778 for(i = 0; i < arity; ++i) {
779 set_irn_n(node, i, new_Bad());
784 * Folds Add or Sub to LEA if possible
786 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
787 ir_graph *irg = get_irn_irg(irn);
788 dbg_info *dbg_info = get_irn_dbg_info(irn);
789 ir_node *block = get_nodes_block(irn);
791 ir_node *shift = NULL;
792 ir_node *lea_o = NULL;
802 ir_entity *am_sc = NULL;
803 ir_entity *lea_ent = NULL;
804 ir_node *noreg = ia32_new_NoReg_gp(cg);
805 ir_node *left, *right, *temp;
806 ir_node *base, *index;
807 int consumed_left_shift;
808 ia32_am_flavour_t am_flav;
810 if (is_ia32_Add(irn))
813 left = get_irn_n(irn, 2);
814 right = get_irn_n(irn, 3);
816 /* "normalize" arguments in case of add with two operands */
817 if (isadd && ! be_is_NoReg(cg, right)) {
818 /* put LEA == ia32_am_O as right operand */
819 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
820 set_irn_n(irn, 2, right);
821 set_irn_n(irn, 3, left);
827 /* put LEA != ia32_am_O as left operand */
828 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
829 set_irn_n(irn, 2, right);
830 set_irn_n(irn, 3, left);
836 /* put SHL as left operand iff left is NOT a LEA */
837 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
838 set_irn_n(irn, 2, right);
839 set_irn_n(irn, 3, left);
852 /* check for operation with immediate */
853 if (is_ia32_ImmConst(irn)) {
854 tarval *tv = get_ia32_Immop_tarval(irn);
856 DBG((dbg, LEVEL_1, "\tfound op with imm const"));
858 offs_cnst = get_tarval_long(tv);
861 else if (isadd && is_ia32_ImmSymConst(irn)) {
862 DBG((dbg, LEVEL_1, "\tfound op with imm symconst"));
866 am_sc = get_ia32_Immop_symconst(irn);
867 am_sc_sign = is_ia32_am_sc_sign(irn);
870 /* determine the operand which needs to be checked */
871 temp = be_is_NoReg(cg, right) ? left : right;
873 /* check if right operand is AMConst (LEA with ia32_am_O) */
874 /* but we can only eat it up if there is no other symconst */
875 /* because the linker won't accept two symconsts */
876 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
877 DBG((dbg, LEVEL_1, "\tgot op with LEA am_O"));
879 offs_lea = get_ia32_am_offs_int(temp);
880 am_sc = get_ia32_am_sc(temp);
881 am_sc_sign = is_ia32_am_sc_sign(temp);
888 else if (temp == right)
893 /* default for add -> make right operand to index */
896 consumed_left_shift = -1;
898 DBG((dbg, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
900 /* determine the operand which needs to be checked */
902 if (is_ia32_Lea(left)) {
904 consumed_left_shift = 0;
907 /* check for SHL 1,2,3 */
908 if (pred_is_specific_node(temp, is_ia32_Shl)) {
910 if (is_ia32_ImmConst(temp)) {
911 long shiftval = get_tarval_long(get_ia32_Immop_tarval(temp));
914 index = get_irn_n(temp, 2);
915 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
919 DBG((dbg, LEVEL_1, "\tgot scaled index %+F\n", index));
925 if (! be_is_NoReg(cg, index)) {
926 /* if we have index, but left == right -> no base */
930 else if (consumed_left_shift == 1) {
931 /* -> base is right operand */
932 base = (right == lea_o) ? noreg : right;
937 /* Try to assimilate a LEA as left operand */
938 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
939 /* check if we can assimilate the LEA */
940 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
942 if (take_attr == IA32_LEA_ATTR_NONE) {
943 DBG((dbg, LEVEL_1, "\tleave old LEA, creating new one\n"));
946 DBG((dbg, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
947 lea = left; /* for statistics */
949 if (take_attr & IA32_LEA_ATTR_OFFS)
950 offs = get_ia32_am_offs_int(left);
952 if (take_attr & IA32_LEA_ATTR_AMSC) {
953 am_sc = get_ia32_am_sc(left);
955 am_sc_sign = is_ia32_am_sc_sign(left);
958 if (take_attr & IA32_LEA_ATTR_SCALE)
959 scale = get_ia32_am_scale(left);
961 if (take_attr & IA32_LEA_ATTR_BASE)
962 base = get_irn_n(left, 0);
964 if (take_attr & IA32_LEA_ATTR_INDEX)
965 index = get_irn_n(left, 1);
967 if (take_attr & IA32_LEA_ATTR_FENT)
968 lea_ent = get_ia32_frame_ent(left);
972 /* ok, we can create a new LEA */
974 res = new_rd_ia32_Lea(dbg_info, irg, block, base, index);
975 /* we don't want stuff before the barrier... */
976 if(be_is_NoReg(cg, base) && be_is_NoReg(cg, index)) {
977 add_irn_dep(res, get_irg_frame(irg));
980 /* add the old offset of a previous LEA */
981 add_ia32_am_offs_int(res, offs);
983 /* add the new offset */
985 add_ia32_am_offs_int(res, offs_cnst);
986 add_ia32_am_offs_int(res, offs_lea);
988 /* either lea_O-cnst, -cnst or -lea_O */
989 if (offs_cnst != 0) {
990 add_ia32_am_offs_int(res, offs_lea);
991 add_ia32_am_offs_int(res, -offs_cnst);
993 add_ia32_am_offs_int(res, offs_lea);
997 /* set the address mode symconst */
999 set_ia32_am_sc(res, am_sc);
1001 set_ia32_am_sc_sign(res);
1004 /* copy the frame entity (could be set in case of Add */
1005 /* which was a FrameAddr) */
1006 if (lea_ent != NULL) {
1007 set_ia32_frame_ent(res, lea_ent);
1008 set_ia32_use_frame(res);
1010 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1011 if(is_ia32_use_frame(irn))
1012 set_ia32_use_frame(res);
1016 set_ia32_am_scale(res, scale);
1018 am_flav = ia32_am_N;
1019 /* determine new am flavour */
1020 if (offs || offs_cnst || offs_lea || have_am_sc) {
1023 if (! be_is_NoReg(cg, base)) {
1026 if (! be_is_NoReg(cg, index)) {
1032 set_ia32_am_flavour(res, am_flav);
1034 set_ia32_op_type(res, ia32_AddrModeS);
1036 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1038 DBG((dbg, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
1040 assert(irn && "Couldn't find result proj");
1042 /* get the result Proj of the Add/Sub */
1043 try_add_to_sched(irn, res);
1045 /* exchange the old op with the new LEA */
1046 try_remove_from_sched(irn);
1049 /* we will exchange it, report here before the Proj is created */
1050 if (shift && lea && lea_o) {
1051 try_remove_from_sched(shift);
1052 try_remove_from_sched(lea);
1053 try_remove_from_sched(lea_o);
1054 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1055 } else if (shift && lea) {
1056 try_remove_from_sched(shift);
1057 try_remove_from_sched(lea);
1058 DBG_OPT_LEA3(irn, lea, shift, res);
1059 } else if (shift && lea_o) {
1060 try_remove_from_sched(shift);
1061 try_remove_from_sched(lea_o);
1062 DBG_OPT_LEA3(irn, lea_o, shift, res);
1063 } else if (lea && lea_o) {
1064 try_remove_from_sched(lea);
1065 try_remove_from_sched(lea_o);
1066 DBG_OPT_LEA3(irn, lea_o, lea, res);
1068 try_remove_from_sched(shift);
1069 DBG_OPT_LEA2(irn, shift, res);
1071 try_remove_from_sched(lea);
1072 DBG_OPT_LEA2(irn, lea, res);
1074 try_remove_from_sched(lea_o);
1075 DBG_OPT_LEA2(irn, lea_o, res);
1077 DBG_OPT_LEA1(irn, res);
1086 * Merges a Load/Store node with a LEA.
1087 * @param irn The Load/Store node
1088 * @param lea The LEA
1090 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1091 ir_entity *irn_ent = get_ia32_frame_ent(irn);
1092 ir_entity *lea_ent = get_ia32_frame_ent(lea);
1094 /* If the irn and the LEA both have a different frame entity set: do not merge */
1095 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
1097 else if (irn_ent == NULL && lea_ent != NULL) {
1098 set_ia32_frame_ent(irn, lea_ent);
1099 set_ia32_use_frame(irn);
1102 /* get the AM attributes from the LEA */
1103 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
1104 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1105 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1107 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1108 if (is_ia32_am_sc_sign(lea))
1109 set_ia32_am_sc_sign(irn);
1111 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1113 /* set base and index */
1114 set_irn_n(irn, 0, get_irn_n(lea, 0));
1115 set_irn_n(irn, 1, get_irn_n(lea, 1));
1117 try_remove_from_sched(lea);
1119 /* clear remat flag */
1120 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1122 if (is_ia32_Ld(irn))
1123 DBG_OPT_LOAD_LEA(lea, irn);
1125 DBG_OPT_STORE_LEA(lea, irn);
1130 * Sets new_right index of irn to right and new_left index to left.
1131 * Also exchange left and right
1133 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1136 set_irn_n(irn, new_right, *right);
1137 set_irn_n(irn, new_left, *left);
1143 /* this is only needed for Compares, but currently ALL nodes
1144 * have this attribute :-) */
1145 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1149 * Performs address calculation optimization (create LEAs if possible)
1151 static void optimize_lea(ia32_code_gen_t *cg, ir_node *irn) {
1152 if (! is_ia32_irn(irn))
1155 /* Following cases can occur: */
1156 /* - Sub (l, imm) -> LEA [base - offset] */
1157 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1158 /* - Add (l, imm) -> LEA [base + offset] */
1159 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1160 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1161 /* - Add (l, r) -> LEA [base + index * scale] */
1162 /* with scale > 1 iff l/r == shl (1,2,3) */
1163 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1166 if(!is_addr_candidate(irn))
1169 DBG((dbg, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1170 res = fold_addr(cg, irn);
1173 DB((dbg, LEVEL_1, "transformed into %+F\n", res));
1175 DB((dbg, LEVEL_1, "not transformed\n"));
1176 } else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1177 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1178 /* - Store -> LEA into Store } it might be better to keep the LEA */
1179 ir_node *left = get_irn_n(irn, 0);
1181 if (is_ia32_Lea(left)) {
1182 const ir_edge_t *edge, *ne;
1185 /* merge all Loads/Stores connected to this LEA with the LEA */
1186 foreach_out_edge_safe(left, edge, ne) {
1187 src = get_edge_src_irn(edge);
1189 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1190 DBG((dbg, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1191 if (! is_ia32_got_lea(src))
1192 merge_loadstore_lea(src, left);
1193 set_ia32_got_lea(src);
1200 static void optimize_conv_store(ir_node *node)
1204 ir_mode *store_mode;
1206 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1209 pred = get_irn_n(node, 2);
1210 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1213 /* the store only stores the lower bits, so we only need the conv
1214 * it it shrinks the mode */
1215 conv_mode = get_ia32_ls_mode(pred);
1216 store_mode = get_ia32_ls_mode(node);
1217 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1220 set_irn_n(node, 2, get_irn_n(pred, 2));
1221 if(get_irn_n_edges(pred) == 0) {
1226 static void optimize_load_conv(ir_node *node)
1228 ir_node *pred, *predpred;
1232 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1235 pred = get_irn_n(node, 2);
1239 predpred = get_Proj_pred(pred);
1240 if(!is_ia32_Load(predpred))
1243 /* the load is sign extending the upper bits, so we only need the conv
1244 * if it shrinks the mode */
1245 load_mode = get_ia32_ls_mode(predpred);
1246 conv_mode = get_ia32_ls_mode(node);
1247 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1250 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1251 /* change the load if it has only 1 user */
1252 if(get_irn_n_edges(pred) == 1) {
1254 if(get_mode_sign(conv_mode)) {
1255 newmode = find_signed_mode(load_mode);
1257 newmode = find_unsigned_mode(load_mode);
1259 assert(newmode != NULL);
1260 set_ia32_ls_mode(predpred, newmode);
1262 /* otherwise we have to keep the conv */
1268 exchange(node, pred);
1271 static void optimize_conv_conv(ir_node *node)
1277 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1280 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1281 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1282 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1285 /* we know that after a conv, the upper bits are sign extended
1286 * so we only need the 2nd conv if it shrinks the mode */
1287 conv_mode = get_ia32_ls_mode(node);
1288 pred_mode = get_ia32_ls_mode(pred);
1289 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(pred_mode))
1292 /* we can't eliminate an upconv signed->unsigned */
1293 if (get_mode_size_bits(conv_mode) != get_mode_size_bits(pred_mode) &&
1294 !get_mode_sign(conv_mode) && get_mode_sign(pred_mode))
1298 exchange(node, pred);
1301 static void optimize_node(ir_node *node, void *env)
1303 ia32_code_gen_t *cg = env;
1305 optimize_load_conv(node);
1306 optimize_conv_store(node);
1307 optimize_conv_conv(node);
1308 optimize_lea(cg, node);
1312 * Checks for address mode patterns and performs the
1313 * necessary transformations.
1314 * This function is called by a walker.
1316 static void optimize_am(ir_node *irn, void *env) {
1317 ia32_am_opt_env_t *am_opt_env = env;
1318 ia32_code_gen_t *cg = am_opt_env->cg;
1319 ir_graph *irg = get_irn_irg(irn);
1320 heights_t *h = am_opt_env->h;
1321 ir_node *block, *left, *right;
1322 ir_node *store, *load, *mem_proj;
1323 ir_node *addr_b, *addr_i;
1324 int need_exchange_on_fail = 0;
1325 ia32_am_type_t am_support;
1326 ia32_am_cand_t cand;
1327 ia32_am_cand_t orig_cand;
1329 int source_possible;
1331 static const arch_register_req_t dest_out_reg_req_0 = {
1332 arch_register_req_type_none,
1333 NULL, /* regclass */
1334 NULL, /* limit bitset */
1336 -1 /* different pos */
1338 static const arch_register_req_t *dest_am_out_reqs[] = {
1342 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1344 if (is_ia32_Lea(irn))
1347 am_support = get_ia32_am_support(irn);
1348 block = get_nodes_block(irn);
1350 /* fold following patterns: */
1351 /* - op -> Load into AMop with am_Source */
1353 /* - op is am_Source capable AND */
1354 /* - the Load is only used by this op AND */
1355 /* - the Load is in the same block */
1356 /* - Store -> op -> Load into AMop with am_Dest */
1358 /* - op is am_Dest capable AND */
1359 /* - the Store uses the same address as the Load AND */
1360 /* - the Load is only used by this op AND */
1361 /* - the Load and Store are in the same block AND */
1362 /* - nobody else uses the result of the op */
1363 if (get_ia32_am_support(irn) == ia32_am_None)
1366 cand = is_am_candidate(h, block, irn);
1367 if (cand == IA32_AM_CAND_NONE)
1371 DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F (candleft %d candright %d)... \n", irn,
1372 cand & IA32_AM_CAND_LEFT, cand & IA32_AM_CAND_RIGHT));
1374 left = get_irn_n(irn, 2);
1375 if (get_irn_arity(irn) == 4) {
1376 /* it's an "unary" operation */
1378 assert(cand == IA32_AM_CAND_BOTH);
1380 right = get_irn_n(irn, 3);
1383 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1384 source_possible = am_support & ia32_am_Source ? 1 : 0;
1386 DBG((dbg, LEVEL_2, "\tdest_possible %d source_possible %d ... \n", dest_possible, source_possible));
1388 if (dest_possible) {
1393 /* we should only have 1 user which is a store */
1394 if (ia32_get_irn_n_edges(irn) == 1) {
1395 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1397 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1399 addr_b = get_irn_n(store, 0);
1400 addr_i = get_irn_n(store, 1);
1404 if (store == NULL) {
1405 DBG((dbg, LEVEL_2, "\tno store found, not using dest_mode\n"));
1410 if (dest_possible) {
1411 /* normalize nodes, we need the interesting load on the left side */
1412 if (cand & IA32_AM_CAND_RIGHT) {
1413 load = get_Proj_pred(right);
1414 if (load_store_addr_is_equal(load, store, addr_b, addr_i)
1415 && node_is_ia32_comm(irn)) {
1416 DBG((dbg, LEVEL_2, "\texchanging left/right\n"));
1417 exchange_left_right(irn, &left, &right, 3, 2);
1418 need_exchange_on_fail ^= 1;
1419 if (cand == IA32_AM_CAND_RIGHT)
1420 cand = IA32_AM_CAND_LEFT;
1425 if (dest_possible) {
1426 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1427 load = get_Proj_pred(left);
1429 #ifndef AGGRESSIVE_AM
1430 /* we have to be the only user of the load */
1431 if (get_irn_n_edges(left) > 1) {
1432 DBG((dbg, LEVEL_2, "\tmatching load has too may users, not using dest_mode\n"));
1437 DBG((dbg, LEVEL_2, "\tno matching load found, not using dest_mode"));
1442 if (dest_possible) {
1443 /* the store has to use the loads memory or the same memory
1445 ir_node *loadmem = get_irn_n(load, 2);
1446 ir_node *storemem = get_irn_n(store, 3);
1447 assert(get_irn_mode(loadmem) == mode_M);
1448 assert(get_irn_mode(storemem) == mode_M);
1449 /* TODO there could be a sync between store and load... */
1450 if(storemem != loadmem && (!is_Proj(storemem) || get_Proj_pred(storemem) != load)) {
1451 DBG((dbg, LEVEL_2, "\tload/store using different memories, not using dest_mode"));
1456 if (dest_possible) {
1457 /* Compare Load and Store address */
1458 if (!load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1459 DBG((dbg, LEVEL_2, "\taddresses not equal, not using dest_mode"));
1464 if (dest_possible) {
1465 ir_mode *lsmode = get_ia32_ls_mode(load);
1466 if(get_mode_size_bits(lsmode) != 32) {
1471 if (dest_possible) {
1472 /* all conditions fullfilled, do the transformation */
1473 assert(cand & IA32_AM_CAND_LEFT);
1475 /* set new base, index and attributes */
1476 set_irn_n(irn, 0, addr_b);
1477 set_irn_n(irn, 1, addr_i);
1478 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1479 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1480 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1481 set_ia32_op_type(irn, ia32_AddrModeD);
1482 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1483 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1485 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1486 if (is_ia32_am_sc_sign(load))
1487 set_ia32_am_sc_sign(irn);
1489 /* connect to Load memory and disconnect Load */
1490 if (get_irn_arity(irn) == 5) {
1492 set_irn_n(irn, 4, get_irn_n(load, 2));
1493 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1496 set_irn_n(irn, 3, get_irn_n(load, 2));
1497 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1500 /* change node mode and out register requirements */
1501 set_irn_mode(irn, mode_M);
1502 set_ia32_out_req_all(irn, dest_am_out_reqs);
1504 /* connect the memory Proj of the Store to the op */
1505 edges_reroute(store, irn, irg);
1507 /* clear remat flag */
1508 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1510 try_remove_from_sched(store);
1511 try_remove_from_sched(load);
1512 DBG_OPT_AM_D(load, store, irn);
1514 DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1515 need_exchange_on_fail = 0;
1516 source_possible = 0;
1519 if (source_possible) {
1520 /* normalize ops, we need the load on the right */
1521 if(cand == IA32_AM_CAND_LEFT) {
1522 if(node_is_ia32_comm(irn)) {
1523 exchange_left_right(irn, &left, &right, 3, 2);
1524 need_exchange_on_fail ^= 1;
1525 cand = IA32_AM_CAND_RIGHT;
1527 source_possible = 0;
1532 if (source_possible) {
1533 /* all conditions fullfilled, do transform */
1534 assert(cand & IA32_AM_CAND_RIGHT);
1535 load = get_Proj_pred(right);
1537 if(get_irn_n_edges(load) > 1) {
1538 source_possible = 0;
1542 if (source_possible) {
1543 ir_mode *ls_mode = get_ia32_ls_mode(load);
1544 if(get_mode_size_bits(ls_mode) != 32)
1545 source_possible = 0;
1549 if (source_possible) {
1550 addr_b = get_irn_n(load, 0);
1551 addr_i = get_irn_n(load, 1);
1553 /* set new base, index and attributes */
1554 set_irn_n(irn, 0, addr_b);
1555 set_irn_n(irn, 1, addr_i);
1556 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1557 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1558 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1559 set_ia32_op_type(irn, ia32_AddrModeS);
1560 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1561 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1563 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1564 if (is_ia32_am_sc_sign(load))
1565 set_ia32_am_sc_sign(irn);
1567 /* clear remat flag */
1568 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1570 if (is_ia32_use_frame(load)) {
1571 if(get_ia32_frame_ent(load) == NULL) {
1572 set_ia32_need_stackent(irn);
1574 set_ia32_use_frame(irn);
1577 /* connect to Load memory and disconnect Load */
1578 if (get_irn_arity(irn) == 5) {
1580 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
1581 set_irn_n(irn, 4, get_irn_n(load, 2));
1583 assert(get_irn_arity(irn) == 4);
1585 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1586 set_irn_n(irn, 3, get_irn_n(load, 2));
1589 DBG_OPT_AM_S(load, irn);
1591 /* If Load has a memory Proj, connect it to the op */
1592 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1593 if (mem_proj != NULL) {
1595 ir_mode *mode = get_irn_mode(irn);
1597 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1598 get_nodes_block(irn), new_Unknown(mode_T),
1600 set_irn_mode(irn, mode_T);
1601 edges_reroute(irn, res_proj, irg);
1602 set_Proj_pred(res_proj, irn);
1604 set_Proj_pred(mem_proj, irn);
1605 set_Proj_proj(mem_proj, 1);
1607 if(sched_is_scheduled(irn)) {
1608 sched_add_after(irn, res_proj);
1609 sched_add_after(irn, mem_proj);
1613 if(get_irn_n_edges(load) == 0) {
1614 try_remove_from_sched(load);
1616 need_exchange_on_fail = 0;
1618 DB((dbg, LEVEL_1, "merged with %+F into source AM\n", load));
1621 /* was exchanged but optimize failed: exchange back */
1622 if (need_exchange_on_fail) {
1623 exchange_left_right(irn, &left, &right, 3, 2);
1628 * Performs conv and address mode optimization.
1630 void ia32_optimize_graph(ia32_code_gen_t *cg) {
1631 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1632 if (! (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA))) {
1633 /* no optimizations at all */
1637 /* beware: we cannot optimize LEA and AM in one run because */
1638 /* LEA optimization adds new nodes to the irg which */
1639 /* invalidates the phase data */
1641 if (cg->opt & IA32_OPT_LEA) {
1642 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1646 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1648 /* hack for now, so these don't get created during optimize, because then
1649 * they will be unknown to the heights module
1651 ia32_new_NoReg_gp(cg);
1652 ia32_new_NoReg_fp(cg);
1653 ia32_new_NoReg_vfp(cg);
1655 if (cg->opt & IA32_OPT_DOAM) {
1656 /* we need height information for am optimization */
1657 heights_t *h = heights_new(cg->irg);
1658 ia32_am_opt_env_t env;
1663 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
1669 void ia32_init_optimize(void)
1671 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");