8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
23 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
25 typedef int is_op_func_t(const ir_node *n);
27 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
28 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
29 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
39 /*************************************************
42 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
43 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
44 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
45 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
47 *************************************************/
50 * creates a unique ident by adding a number to a tag
52 * @param tag the tag string, must contain a %d if a number
55 static ident *unique_id(const char *tag)
57 static unsigned id = 0;
60 snprintf(str, sizeof(str), tag, ++id);
61 return new_id_from_str(str);
67 * Transforms a SymConst.
69 * @param mod the debug module
70 * @param block the block the new node should belong to
71 * @param node the ir SymConst node
72 * @param mode mode of the SymConst
73 * @return the created ia32 Const node
75 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
77 dbg_info *dbg = env->dbg;
78 ir_mode *mode = env->mode;
79 ir_graph *irg = env->irg;
80 ir_node *block = env->block;
82 if (mode_is_float(mode)) {
83 cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
86 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
88 set_ia32_Const_attr(cnst, env->irn);
93 * Get a primitive type for a mode.
95 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
97 pmap_entry *e = pmap_find(types, mode);
102 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
103 res = new_type_primitive(new_id_from_str(buf), mode);
104 pmap_insert(types, mode, res);
112 * Get an entity that is initialized with a tarval
114 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
116 tarval *tv = get_Const_tarval(cnst);
117 pmap_entry *e = pmap_find(cg->tv_ent, tv);
122 ir_mode *mode = get_irn_mode(cnst);
123 ir_type *tp = get_Const_type(cnst);
124 if (tp == firm_unknown_type)
125 tp = get_prim_type(cg->types, mode);
127 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
129 set_entity_ld_ident(res, get_entity_ident(res));
130 set_entity_visibility(res, visibility_local);
131 set_entity_variability(res, variability_constant);
132 set_entity_allocation(res, allocation_static);
134 /* we create a new entity here: It's initialization must resist on the
136 rem = current_ir_graph;
137 current_ir_graph = get_const_code_irg();
138 set_atomic_ent_value(res, new_Const_type(tv, tp));
139 current_ir_graph = rem;
147 * Transforms a Const.
149 * @param mod the debug module
150 * @param block the block the new node should belong to
151 * @param node the ir Const node
152 * @param mode mode of the Const
153 * @return the created ia32 Const node
155 static ir_node *gen_Const(ia32_transform_env_t *env) {
158 ir_graph *irg = env->irg;
159 ir_node *block = env->block;
160 ir_node *node = env->irn;
161 dbg_info *dbg = env->dbg;
162 ir_mode *mode = env->mode;
164 if (mode_is_float(mode)) {
165 sym.entity_p = get_entity_for_tv(env->cg, node);
167 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
169 cnst = gen_SymConst(env);
172 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
173 set_ia32_Const_attr(cnst, node);
181 * Transforms (all) Const's into ia32_Const and places them in the
182 * block where they are used (or in the cfg-pred Block in case of Phi's).
183 * Additionally all reference nodes are changed into mode_Is nodes.
185 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
186 ia32_code_gen_t *cg = env;
187 ia32_transform_env_t tenv;
189 ir_node *pred, *cnst;
196 mode = get_irn_mode(irn);
198 /* transform all reference nodes into mode_Is nodes */
199 if (mode_is_reference(mode)) {
201 set_irn_mode(irn, mode);
204 tenv.block = get_nodes_block(irn);
209 /* Loop over all predecessors and check for Sym/Const nodes */
210 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
211 pred = get_irn_n(irn, i);
213 opc = get_irn_opcode(pred);
215 tenv.mode = get_irn_mode(pred);
216 tenv.dbg = get_irn_dbg_info(pred);
218 /* If it's a Phi, then we need to create the */
219 /* new Const in it's predecessor block */
221 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
224 /* put the const into the block where the original const was */
225 if (! cg->opt.placecnst) {
226 tenv.block = get_nodes_block(pred);
231 cnst = gen_Const(&tenv);
234 cnst = gen_SymConst(&tenv);
240 /* if we found a const, then set it */
242 set_irn_n(irn, i, cnst);
249 /********************************************************************************************************
250 * _____ _ _ ____ _ _ _ _ _
251 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
252 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
253 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
254 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
255 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
258 ********************************************************************************************************/
261 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
264 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
265 char *c1 = get_ia32_cnst(n1);
266 char *c2 = get_ia32_cnst(n2);
268 if (c1 && c2) /* both consts are set -> compare */
269 return strcmp(c1, c2) == 0;
270 else if (!c1 && !c2) /* both consts are not set -> true */
277 * Checks for potential CJmp/CJmpAM optimization candidates.
279 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
280 ir_node *cand = NULL;
281 ir_node *prev = sched_prev(irn);
283 if (is_Block(prev)) {
284 if (get_Block_n_cfgpreds(prev) == 1)
285 prev = get_Block_cfgpred(prev, 0);
290 /* The predecessor must be a ProjX. */
291 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
292 prev = get_Proj_pred(prev);
294 if (is_op_func(prev))
301 static int is_TestJmp_cand(const ir_node *irn) {
302 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
306 * Checks if two consecutive arguments of cand matches
307 * the two arguments of irn (TestJmp).
309 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
310 ir_node *in1 = get_irn_n(irn, 0);
311 ir_node *in2 = get_irn_n(irn, 1);
312 int i, n = get_irn_arity(cand);
315 for (i = 0; i < n - 1; i++) {
316 if (get_irn_n(cand, i) == in1 &&
317 get_irn_n(cand, i + 1) == in2)
325 return ia32_cnst_compare(cand, irn);
331 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
333 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
334 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
337 /* we found a possible candidate */
338 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
341 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
343 if (is_ia32_And(cand))
344 set_irn_op(irn, op_ia32_CJmpAM);
346 set_irn_op(irn, op_ia32_CJmp);
348 DB((cg->mod, LEVEL_1, "%+F\n", irn));
352 static int is_CondJmp_cand(const ir_node *irn) {
353 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
357 * Checks if the arguments of cand are the same of irn.
359 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
360 int i, n = get_irn_arity(cand);
363 for (i = 0; i < n; i++) {
364 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
371 return ia32_cnst_compare(cand, irn);
377 * Tries to replace a CondJmp by a CJmpAM
379 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
380 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
383 /* we found a possible candidate */
384 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
387 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
389 set_irn_op(irn, op_ia32_CJmp);
391 DB((cg->mod, LEVEL_1, "%+F\n", irn));
396 * Performs Peephole Optimizations
398 void ia32_peephole_optimization(ir_node *irn, void *env) {
399 if (is_ia32_TestJmp(irn)) {
400 ia32_optimize_TestJmp(irn, env);
402 else if (is_ia32_CondJmp(irn)) {
403 ia32_optimize_CondJmp(irn, env);
409 /******************************************************************
411 * /\ | | | | | \/ | | |
412 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
413 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
414 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
415 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
417 ******************************************************************/
419 static int node_is_comm(const ir_node *irn) {
420 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
423 static int ia32_get_irn_n_edges(const ir_node *irn) {
424 const ir_edge_t *edge;
427 foreach_out_edge(irn, edge) {
435 * Returns the first mode_M Proj connected to irn.
437 static ir_node *get_mem_proj(const ir_node *irn) {
438 const ir_edge_t *edge;
441 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
443 foreach_out_edge(irn, edge) {
444 src = get_edge_src_irn(edge);
446 assert(is_Proj(src) && "Proj expected");
448 if (get_irn_mode(src) == mode_M)
456 * Returns the first Proj with mode != mode_M connected to irn.
458 static ir_node *get_res_proj(const ir_node *irn) {
459 const ir_edge_t *edge;
462 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
464 foreach_out_edge(irn, edge) {
465 src = get_edge_src_irn(edge);
467 assert(is_Proj(src) && "Proj expected");
469 if (get_irn_mode(src) != mode_M)
477 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
479 * @param pred The node to be checked
480 * @param is_op_func The check-function
481 * @return 1 if conditions are fulfilled, 0 otherwise
483 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
484 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
492 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
493 * and if the predecessor is in block bl.
495 * @param bl The block
496 * @param pred The node to be checked
497 * @param is_op_func The check-function
498 * @return 1 if conditions are fulfilled, 0 otherwise
500 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
501 int (*is_op_func)(const ir_node *n))
504 pred = get_Proj_pred(pred);
505 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
516 * Checks if irn is a candidate for address calculation or address mode.
518 * address calculation (AC):
519 * - none of the operand must be a Load within the same block OR
520 * - all Loads must have more than one user OR
521 * - the irn has a frame entity (it's a former FrameAddr)
524 * - at least one operand has to be a Load within the same block AND
525 * - the load must not have other users than the irn AND
526 * - the irn must not have a frame entity set
528 * @param block The block the Loads must/not be in
529 * @param irn The irn to check
530 * @param check_addr 1 if to check for address calculation, 0 otherwise
531 * return 1 if irn is a candidate for AC or AM, 0 otherwise
533 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
535 int n, is_cand = check_addr;
537 in = get_irn_n(irn, 2);
539 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
540 n = ia32_get_irn_n_edges(in);
541 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
544 in = get_irn_n(irn, 3);
546 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
547 n = ia32_get_irn_n_edges(in);
548 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
551 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
557 * Compares the base and index addr and the load/store entities
558 * and returns 1 if they are equal.
560 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
561 const ir_node *addr_b, const ir_node *addr_i)
563 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
564 entity *lent = get_ia32_frame_ent(load);
565 entity *sent = get_ia32_frame_ent(store);
567 /* are both entities set and equal? */
568 is_equal = lent && sent && (lent == sent);
570 /* are the load and the store of the same mode? */
571 is_equal = get_ia32_ls_mode(load) == get_ia32_ls_mode(store);
579 * Folds Add or Sub to LEA if possible
581 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
582 ir_graph *irg = get_irn_irg(irn);
583 dbg_info *dbg = get_irn_dbg_info(irn);
584 ir_node *block = get_nodes_block(irn);
587 char *offs_cnst = NULL;
588 char *offs_lea = NULL;
592 ir_node *left, *right, *temp;
593 ir_node *base, *index;
594 ia32_am_flavour_t am_flav;
596 if (is_ia32_Add(irn))
599 left = get_irn_n(irn, 2);
600 right = get_irn_n(irn, 3);
602 /* "normalize" arguments in case of add with two operands */
603 if (isadd && ! be_is_NoReg(babi, right)) {
604 /* put LEA == ia32_am_O as right operand */
605 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
606 set_irn_n(irn, 2, right);
607 set_irn_n(irn, 3, left);
613 /* put LEA != ia32_am_O as left operand */
614 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
615 set_irn_n(irn, 2, right);
616 set_irn_n(irn, 3, left);
622 /* put SHL as left operand iff left is NOT a LEA */
623 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
624 set_irn_n(irn, 2, right);
625 set_irn_n(irn, 3, left);
638 /* check if operand is either const */
639 if (get_ia32_cnst(irn)) {
640 DBG((mod, LEVEL_1, "\tfound op with imm"));
642 offs_cnst = get_ia32_cnst(irn);
646 /* determine the operand which needs to be checked */
647 if (be_is_NoReg(babi, right)) {
654 /* check if right operand is AMConst (LEA with ia32_am_O) */
655 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
656 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
658 offs_lea = get_ia32_am_offs(temp);
663 /* default for add -> make right operand to index */
667 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
669 /* determine the operand which needs to be checked */
671 if (is_ia32_Lea(left)) {
675 /* check for SHL 1,2,3 */
676 if (pred_is_specific_node(temp, is_ia32_Shl)) {
677 temp = get_Proj_pred(temp);
679 if (get_ia32_Immop_tarval(temp)) {
680 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
683 index = get_irn_n(temp, 2);
685 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
691 if (! be_is_NoReg(babi, index)) {
692 /* if we have index, but left == right -> no base */
696 else if (! is_ia32_Lea(left) && (index != right)) {
697 /* index != right -> we found a good Shl */
698 /* left != LEA -> this Shl was the left operand */
699 /* -> base is right operand */
705 /* Try to assimilate a LEA as left operand */
706 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
707 am_flav = get_ia32_am_flavour(left);
709 /* If we have an Add with a real right operand (not NoReg) and */
710 /* the LEA contains already an index calculation then we create */
712 /* If the LEA contains already a frame_entity then we also */
713 /* create a new one otherwise we would loose it. */
714 if ((isadd && !be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) ||
715 get_ia32_frame_ent(left))
717 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
720 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
721 offs = get_ia32_am_offs(left);
722 base = get_irn_n(left, 0);
723 index = get_irn_n(left, 1);
724 scale = get_ia32_am_scale(left);
728 /* ok, we can create a new LEA */
730 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
732 /* add the old offset of a previous LEA */
734 add_ia32_am_offs(res, offs);
737 /* add the new offset */
740 add_ia32_am_offs(res, offs_cnst);
743 add_ia32_am_offs(res, offs_lea);
747 /* either lea_O-cnst, -cnst or -lea_O */
750 add_ia32_am_offs(res, offs_lea);
753 sub_ia32_am_offs(res, offs_cnst);
756 sub_ia32_am_offs(res, offs_lea);
760 /* copy the frame entity (could be set in case of Add */
761 /* which was a FrameAddr) */
762 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
764 if (is_ia32_use_frame(irn))
765 set_ia32_use_frame(res);
768 set_ia32_am_scale(res, scale);
771 /* determine new am flavour */
772 if (offs || offs_cnst || offs_lea) {
775 if (! be_is_NoReg(babi, base)) {
778 if (! be_is_NoReg(babi, index)) {
784 set_ia32_am_flavour(res, am_flav);
786 set_ia32_op_type(res, ia32_AddrModeS);
788 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
790 /* get the result Proj of the Add/Sub */
791 irn = get_res_proj(irn);
793 assert(irn && "Couldn't find result proj");
795 /* exchange the old op with the new LEA */
803 * Optimizes a pattern around irn to address mode if possible.
805 void ia32_optimize_am(ir_node *irn, void *env) {
806 ia32_code_gen_t *cg = env;
807 firm_dbg_module_t *mod = cg->mod;
809 be_abi_irg_t *babi = cg->birg->abi;
812 ir_node *block, *noreg_gp, *noreg_fp;
813 ir_node *left, *right, *temp;
814 ir_node *store, *load, *mem_proj;
815 ir_node *succ, *addr_b, *addr_i;
816 int check_am_src = 0;
818 if (! is_ia32_irn(irn))
821 dbg = get_irn_dbg_info(irn);
822 mode = get_irn_mode(irn);
823 block = get_nodes_block(irn);
824 noreg_gp = ia32_new_NoReg_gp(cg);
825 noreg_fp = ia32_new_NoReg_fp(cg);
827 DBG((mod, LEVEL_1, "checking for AM\n"));
829 /* 1st part: check for address calculations and transform the into Lea */
831 /* Following cases can occur: */
832 /* - Sub (l, imm) -> LEA [base - offset] */
833 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
834 /* - Add (l, imm) -> LEA [base + offset] */
835 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
836 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
837 /* - Add (l, r) -> LEA [base + index * scale] */
838 /* with scale > 1 iff l/r == shl (1,2,3) */
840 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
841 left = get_irn_n(irn, 2);
842 right = get_irn_n(irn, 3);
844 /* Do not try to create a LEA if one of the operands is a Load. */
845 /* check is irn is a candidate for address calculation */
846 if (is_candidate(block, irn, 1)) {
847 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
848 res = fold_addr(babi, irn, mod, noreg_gp);
851 DB((mod, LEVEL_1, "transformed into %+F\n", res));
853 DB((mod, LEVEL_1, "not transformed\n"));
857 /* 2nd part: fold following patterns: */
858 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
859 /* - Store -> LEA into Store } it might be better to keep the LEA */
860 /* - op -> Load into AMop with am_Source */
862 /* - op is am_Source capable AND */
863 /* - the Load is only used by this op AND */
864 /* - the Load is in the same block */
865 /* - Store -> op -> Load into AMop with am_Dest */
867 /* - op is am_Dest capable AND */
868 /* - the Store uses the same address as the Load AND */
869 /* - the Load is only used by this op AND */
870 /* - the Load and Store are in the same block AND */
871 /* - nobody else uses the result of the op */
873 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
874 /* 1st: check for Load/Store -> LEA */
875 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
876 left = get_irn_n(irn, 0);
878 if (is_ia32_Lea(left)) {
879 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
881 /* get the AM attributes from the LEA */
882 add_ia32_am_offs(irn, get_ia32_am_offs(left));
883 set_ia32_am_scale(irn, get_ia32_am_scale(left));
884 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
886 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
888 /* set base and index */
889 set_irn_n(irn, 0, get_irn_n(left, 0));
890 set_irn_n(irn, 1, get_irn_n(left, 1));
893 /* check if the node is an address mode candidate */
894 else if (is_candidate(block, irn, 0)) {
895 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
897 left = get_irn_n(irn, 2);
898 if (get_irn_arity(irn) == 4) {
899 /* it's an "unary" operation */
903 right = get_irn_n(irn, 3);
906 /* normalize commutative ops */
907 if (node_is_comm(irn)) {
908 /* Assure that right operand is always a Load if there is one */
909 /* because non-commutative ops can only use Dest AM if the right */
910 /* operand is a load, so we only need to check right operand. */
911 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
913 set_irn_n(irn, 2, right);
914 set_irn_n(irn, 3, left);
922 /* check for Store -> op -> Load */
924 /* Store -> op -> Load optimization is only possible if supported by op */
925 /* and if right operand is a Load */
926 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
927 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
930 /* An address mode capable op always has a result Proj. */
931 /* If this Proj is used by more than one other node, we don't need to */
932 /* check further, otherwise we check for Store and remember the address, */
933 /* the Store points to. */
935 succ = get_res_proj(irn);
936 assert(succ && "Couldn't find result proj");
942 /* now check for users and Store */
943 if (ia32_get_irn_n_edges(succ) == 1) {
944 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
946 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
948 addr_b = get_irn_n(store, 0);
950 /* Could be that the Store is connected to the address */
951 /* calculating LEA while the Load is already transformed. */
952 if (is_ia32_Lea(addr_b)) {
954 addr_b = get_irn_n(succ, 0);
955 addr_i = get_irn_n(succ, 1);
964 /* we found a Store as single user: Now check for Load */
966 /* Extra check for commutative ops with two Loads */
967 /* -> put the interesting Load right */
968 if (node_is_comm(irn) &&
969 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
971 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
972 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
974 /* We exchange left and right, so it's easier to kill */
975 /* the correct Load later and to handle unary operations. */
976 set_irn_n(irn, 2, right);
977 set_irn_n(irn, 3, left);
985 /* skip the Proj for easier access */
986 load = get_Proj_pred(right);
988 /* Compare Load and Store address */
989 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
990 /* Right Load is from same address, so we can */
991 /* disconnect the Load and Store here */
993 /* set new base, index and attributes */
994 set_irn_n(irn, 0, addr_b);
995 set_irn_n(irn, 1, addr_i);
996 add_ia32_am_offs(irn, get_ia32_am_offs(load));
997 set_ia32_am_scale(irn, get_ia32_am_scale(load));
998 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
999 set_ia32_op_type(irn, ia32_AddrModeD);
1000 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1001 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1003 if (is_ia32_use_frame(load))
1004 set_ia32_use_frame(irn);
1006 /* connect to Load memory and disconnect Load */
1007 if (get_irn_arity(irn) == 5) {
1009 set_irn_n(irn, 4, get_irn_n(load, 2));
1010 set_irn_n(irn, 3, noreg_gp);
1014 set_irn_n(irn, 3, get_irn_n(load, 2));
1015 set_irn_n(irn, 2, noreg_gp);
1018 /* connect the memory Proj of the Store to the op */
1019 mem_proj = get_mem_proj(store);
1020 set_Proj_pred(mem_proj, irn);
1021 set_Proj_proj(mem_proj, 1);
1023 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1026 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1027 /* There was no store, check if we still can optimize for source address mode */
1030 } /* if (support AM Dest) */
1031 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1032 /* op doesn't support am AM Dest -> check for AM Source */
1036 /* normalize commutative ops */
1037 if (node_is_comm(irn)) {
1038 /* Assure that left operand is always a Load if there is one */
1039 /* because non-commutative ops can only use Source AM if the */
1040 /* left operand is a Load, so we only need to check the left */
1041 /* operand afterwards. */
1042 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1043 set_irn_n(irn, 2, right);
1044 set_irn_n(irn, 3, left);
1052 /* optimize op -> Load iff Load is only used by this op */
1053 /* and left operand is a Load which only used by this irn */
1055 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1056 (ia32_get_irn_n_edges(left) == 1))
1058 left = get_Proj_pred(left);
1060 addr_b = get_irn_n(left, 0);
1061 addr_i = get_irn_n(left, 1);
1063 /* set new base, index and attributes */
1064 set_irn_n(irn, 0, addr_b);
1065 set_irn_n(irn, 1, addr_i);
1066 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1067 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1068 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1069 set_ia32_op_type(irn, ia32_AddrModeS);
1070 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1071 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1073 if (is_ia32_use_frame(left))
1074 set_ia32_use_frame(irn);
1076 /* connect to Load memory */
1077 if (get_irn_arity(irn) == 5) {
1079 set_irn_n(irn, 4, get_irn_n(left, 2));
1083 set_irn_n(irn, 3, get_irn_n(left, 2));
1086 /* disconnect from Load */
1087 set_irn_n(irn, 2, noreg_gp);
1089 /* If Load has a memory Proj, connect it to the op */
1090 mem_proj = get_mem_proj(left);
1092 set_Proj_pred(mem_proj, irn);
1093 set_Proj_proj(mem_proj, 1);
1096 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));