2 * This file is part of libFirm.
3 * Copyright (C) 2012 University of Karlsruhe.
8 * @brief Implements several optimizations for IA32.
9 * @author Matthias Braun, Christian Wuerdig
17 #include "firm_types.h"
26 #include "firmstat_t.h"
32 #include "bepeephole.h"
34 #include "ia32_new_nodes.h"
35 #include "ia32_optimize.h"
36 #include "bearch_ia32_t.h"
37 #include "gen_ia32_regalloc_if.h"
38 #include "ia32_common_transform.h"
39 #include "ia32_transform.h"
40 #include "ia32_dbg_stat.h"
41 #include "ia32_architecture.h"
43 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
45 static void copy_mark(const ir_node *old, ir_node *newn)
47 if (is_ia32_is_reload(old))
48 set_ia32_is_reload(newn);
49 if (is_ia32_is_spill(old))
50 set_ia32_is_spill(newn);
51 if (is_ia32_is_remat(old))
52 set_ia32_is_remat(newn);
55 typedef enum produces_flag_t {
58 produces_zero_in_carry
62 * Return which usable flag the given node produces about the result.
63 * That is zero (ZF) and sign(SF).
64 * We do not check for carry (CF) or overflow (OF).
66 * @param node the node to check
67 * @param pn the projection number of the used result
69 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
72 const ia32_immediate_attr_t *imm_attr;
74 if (!is_ia32_irn(node))
75 return produces_no_flag;
77 switch (get_ia32_irn_opcode(node)) {
92 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
93 count = get_irn_n(node, n_ia32_ShlD_count);
94 goto check_shift_amount;
99 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
100 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
101 count = get_irn_n(node, n_ia32_Shl_count);
103 /* when shift count is zero the flags are not affected, so we can only
104 * do this for constants != 0 */
105 if (!is_ia32_Immediate(count))
106 return produces_no_flag;
108 imm_attr = get_ia32_immediate_attr_const(count);
109 if (imm_attr->symconst != NULL)
110 return produces_no_flag;
111 if ((imm_attr->offset & 0x1f) == 0)
112 return produces_no_flag;
116 return pn == pn_ia32_Mul_res_high ?
117 produces_zero_in_carry : produces_no_flag;
120 return produces_no_flag;
123 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
127 * Replace Cmp(x, 0) by a Test(x, x)
129 static void peephole_ia32_Cmp(ir_node *const node)
131 if (get_ia32_op_type(node) != ia32_Normal)
134 ir_node *const right = get_irn_n(node, n_ia32_Cmp_right);
135 if (!is_ia32_Immediate(right))
138 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
139 if (imm->symconst != NULL || imm->offset != 0)
142 dbg_info *const dbgi = get_irn_dbg_info(node);
143 ir_node *const block = get_nodes_block(node);
144 ir_graph *const irg = get_Block_irg(block);
145 ir_node *const noreg = ia32_new_NoReg_gp(irg);
146 ir_node *const nomem = get_irg_no_mem(irg);
147 ir_node *const op = get_irn_n(node, n_ia32_Cmp_left);
148 int const ins_permuted = get_ia32_attr(node)->data.ins_permuted;
150 ir_mode *const ls_mode = get_ia32_ls_mode(node);
151 ir_node *const test = get_mode_size_bits(ls_mode) == 8
152 ? new_bd_ia32_Test_8bit(dbgi, block, noreg, noreg, nomem, op, op, ins_permuted)
153 : new_bd_ia32_Test (dbgi, block, noreg, noreg, nomem, op, op, ins_permuted);
154 set_ia32_ls_mode(test, ls_mode);
156 arch_register_t const *const reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
157 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
159 foreach_out_edge_safe(node, edge) {
160 ir_node *const user = get_edge_src_irn(edge);
163 exchange(user, test);
166 sched_add_before(node, test);
167 copy_mark(node, test);
168 be_peephole_exchange(node, test);
172 * Peephole optimization for Test instructions.
173 * - Remove the Test, if an appropriate flag was produced which is still live
174 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
176 static void peephole_ia32_Test(ir_node *node)
178 ir_node *left = get_irn_n(node, n_ia32_Test_left);
179 ir_node *right = get_irn_n(node, n_ia32_Test_right);
181 if (left == right) { /* we need a test for 0 */
182 ir_node *block = get_nodes_block(node);
183 int pn = pn_ia32_res;
189 produces_flag_t produced;
191 if (get_nodes_block(left) != block)
195 pn = get_Proj_proj(op);
196 op = get_Proj_pred(op);
199 /* walk schedule up and abort when we find left or some other node
200 * destroys the flags */
203 schedpoint = sched_prev(schedpoint);
204 if (schedpoint == op)
206 if (arch_irn_is(schedpoint, modify_flags))
208 if (schedpoint == block)
209 panic("couldn't find left");
212 produced = check_produces_zero_sign(op, pn);
213 if (produced == produces_no_flag)
216 /* make sure users only look at the sign/zero flag */
217 foreach_out_edge(node, edge) {
218 ir_node *user = get_edge_src_irn(edge);
219 ia32_condition_code_t cc = get_ia32_condcode(user);
221 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
223 if (produced == produces_zero_sign
224 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
230 op_mode = get_ia32_ls_mode(op);
232 op_mode = get_irn_mode(op);
234 /* Make sure we operate on the same bit size */
235 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
238 if (produced == produces_zero_in_carry) {
239 /* patch users to look at the carry instead of the zero flag */
240 foreach_out_edge(node, edge) {
241 ir_node *user = get_edge_src_irn(edge);
242 ia32_condition_code_t cc = get_ia32_condcode(user);
245 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
246 case ia32_cc_not_equal: cc = ia32_cc_below; break;
247 default: panic("unexpected pn");
249 set_ia32_condcode(user, cc);
253 if (get_irn_mode(op) != mode_T) {
254 set_irn_mode(op, mode_T);
256 /* If there are other users, reroute them to result proj */
257 if (get_irn_n_edges(op) != 2) {
258 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
259 edges_reroute_except(op, res, res);
262 if (get_irn_n_edges(left) == 2)
266 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
267 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
268 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
270 assert(get_irn_mode(node) != mode_T);
272 be_peephole_exchange(node, flags_proj);
273 } else if (is_ia32_Immediate(right)) {
274 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
277 /* A test with a symconst is rather strange, but better safe than sorry */
278 if (imm->symconst != NULL)
281 offset = imm->offset;
282 if (get_ia32_op_type(node) == ia32_AddrModeS) {
283 ia32_attr_t *const attr = get_ia32_attr(node);
284 ir_graph *const irg = get_irn_irg(node);
286 if ((offset & 0xFFFFFF00) == 0) {
287 /* attr->am_offs += 0; */
288 } else if ((offset & 0xFFFF00FF) == 0) {
289 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 8);
290 set_irn_n(node, n_ia32_Test_right, imm_node);
292 } else if ((offset & 0xFF00FFFF) == 0) {
293 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 16);
294 set_irn_n(node, n_ia32_Test_right, imm_node);
296 } else if ((offset & 0x00FFFFFF) == 0) {
297 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 24);
298 set_irn_n(node, n_ia32_Test_right, imm_node);
303 } else if (offset < 256) {
304 arch_register_t const* const reg = arch_get_irn_register(left);
306 if (reg != &ia32_registers[REG_EAX] &&
307 reg != &ia32_registers[REG_EBX] &&
308 reg != &ia32_registers[REG_ECX] &&
309 reg != &ia32_registers[REG_EDX]) {
316 /* Technically we should build a Test8Bit because of the register
317 * constraints, but nobody changes registers at this point anymore. */
318 set_ia32_ls_mode(node, mode_Bu);
323 * AMD Athlon works faster when RET is not destination of
324 * conditional jump or directly preceded by other jump instruction.
325 * Can be avoided by placing a Rep prefix before the return.
327 static void peephole_ia32_Return(ir_node *node)
329 if (!ia32_cg_config.use_pad_return)
332 /* check if this return is the first on the block */
333 sched_foreach_reverse_before(node, irn) {
334 switch (get_irn_opcode(irn)) {
336 /* ignore no code generated */
339 /* arg, IncSP 0 nodes might occur, ignore these */
340 if (be_get_IncSP_offset(irn) == 0)
350 /* ensure, that the 3 byte return is generated */
351 be_Return_set_emit_pop(node, 1);
354 /* only optimize up to 48 stores behind IncSPs */
355 #define MAXPUSH_OPTIMIZE 48
358 * Tries to create Push's from IncSP, Store combinations.
359 * The Stores are replaced by Push's, the IncSP is modified
360 * (possibly into IncSP 0, but not removed).
362 static void peephole_IncSP_Store_to_push(ir_node *irn)
366 ir_node *stores[MAXPUSH_OPTIMIZE];
371 ir_node *first_push = NULL;
373 memset(stores, 0, sizeof(stores));
375 int inc_ofs = be_get_IncSP_offset(irn);
380 * We first walk the schedule after the IncSP node as long as we find
381 * suitable Stores that could be transformed to a Push.
382 * We save them into the stores array which is sorted by the frame offset/4
383 * attached to the node
386 sched_foreach_after(irn, node) {
391 /* it has to be a Store */
392 if (!is_ia32_Store(node))
395 /* it has to use our sp value */
396 if (get_irn_n(node, n_ia32_base) != irn)
398 /* Store has to be attached to NoMem */
399 mem = get_irn_n(node, n_ia32_mem);
403 /* unfortunately we can't support the full AMs possible for push at the
404 * moment. TODO: fix this */
405 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
408 offset = get_ia32_am_offs_int(node);
409 /* we should NEVER access uninitialized stack BELOW the current SP */
412 /* storing at half-slots is bad */
413 if ((offset & 3) != 0)
416 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
418 storeslot = offset >> 2;
420 /* storing into the same slot twice is bad (and shouldn't happen...) */
421 if (stores[storeslot] != NULL)
424 stores[storeslot] = node;
425 if (storeslot > maxslot)
431 for (i = -1; i < maxslot; ++i) {
432 if (stores[i + 1] == NULL)
436 /* walk through the Stores and create Pushs for them */
437 block = get_nodes_block(irn);
438 spmode = get_irn_mode(irn);
439 irg = get_irn_irg(irn);
440 for (; i >= 0; --i) {
441 const arch_register_t *spreg;
443 ir_node *val, *mem, *mem_proj;
444 ir_node *store = stores[i];
445 ir_node *noreg = ia32_new_NoReg_gp(irg);
447 val = get_irn_n(store, n_ia32_unary_op);
448 mem = get_irn_n(store, n_ia32_mem);
449 spreg = arch_get_irn_register(curr_sp);
451 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
453 copy_mark(store, push);
455 if (first_push == NULL)
458 sched_add_after(skip_Proj(curr_sp), push);
460 /* create stackpointer Proj */
461 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
462 arch_set_irn_register(curr_sp, spreg);
464 /* create memory Proj */
465 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
467 /* rewire Store Projs */
468 foreach_out_edge_safe(store, edge) {
469 ir_node *proj = get_edge_src_irn(edge);
472 switch (get_Proj_proj(proj)) {
473 case pn_ia32_Store_M:
474 exchange(proj, mem_proj);
477 panic("unexpected Proj on Store->IncSp");
481 /* use the memproj now */
482 be_peephole_exchange(store, push);
487 foreach_out_edge_safe(irn, edge) {
488 ir_node *const src = get_edge_src_irn(edge);
489 int const pos = get_edge_src_pos(edge);
491 if (src == first_push)
494 set_irn_n(src, pos, curr_sp);
497 be_set_IncSP_offset(irn, inc_ofs);
501 * Return true if a mode can be stored in the GP register set
503 static inline int mode_needs_gp_reg(ir_mode *mode)
505 if (mode == ia32_mode_fpcw)
507 if (get_mode_size_bits(mode) > 32)
509 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
513 * Tries to create Pops from Load, IncSP combinations.
514 * The Loads are replaced by Pops, the IncSP is modified
515 * (possibly into IncSP 0, but not removed).
517 static void peephole_Load_IncSP_to_pop(ir_node *irn)
519 const arch_register_t *esp = &ia32_registers[REG_ESP];
521 ir_node *loads[MAXPUSH_OPTIMIZE];
522 unsigned regmask = 0;
523 unsigned copymask = ~0;
525 memset(loads, 0, sizeof(loads));
527 int inc_ofs = -be_get_IncSP_offset(irn);
532 * We first walk the schedule before the IncSP node as long as we find
533 * suitable Loads that could be transformed to a Pop.
534 * We save them into the stores array which is sorted by the frame offset/4
535 * attached to the node
538 ir_node *pred_sp = be_get_IncSP_pred(irn);
539 sched_foreach_reverse_before(irn, node) {
542 const arch_register_t *sreg, *dreg;
544 /* it has to be a Load */
545 if (!is_ia32_Load(node)) {
546 if (be_is_Copy(node)) {
547 if (!mode_needs_gp_reg(get_irn_mode(node))) {
548 /* not a GP copy, ignore */
551 dreg = arch_get_irn_register(node);
552 sreg = arch_get_irn_register(be_get_Copy_op(node));
553 if (regmask & copymask & (1 << sreg->index)) {
556 if (regmask & copymask & (1 << dreg->index)) {
559 /* we CAN skip Copies if neither the destination nor the source
560 * is not in our regmask, ie none of our future Pop will overwrite it */
561 regmask |= (1 << dreg->index) | (1 << sreg->index);
562 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
568 /* we can handle only GP loads */
569 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
572 /* it has to use our predecessor sp value */
573 if (get_irn_n(node, n_ia32_base) != pred_sp) {
574 /* it would be ok if this load does not use a Pop result,
575 * but we do not check this */
579 /* should have NO index */
580 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
583 offset = get_ia32_am_offs_int(node);
584 /* we should NEVER access uninitialized stack BELOW the current SP */
587 /* storing at half-slots is bad */
588 if ((offset & 3) != 0)
591 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
593 /* ignore those outside the possible windows */
594 if (offset > inc_ofs - 4)
596 loadslot = offset >> 2;
598 /* loading from the same slot twice is bad (and shouldn't happen...) */
599 if (loads[loadslot] != NULL)
602 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
603 if (regmask & (1 << dreg->index)) {
604 /* this register is already used */
607 regmask |= 1 << dreg->index;
609 loads[loadslot] = node;
610 if (loadslot > maxslot)
617 /* find the first slot */
618 for (i = maxslot; i >= 0; --i) {
619 ir_node *load = loads[i];
625 ofs = inc_ofs - (maxslot + 1) * 4;
628 /* create a new IncSP if needed */
629 ir_node *const block = get_nodes_block(irn);
631 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
632 sched_add_before(irn, pred_sp);
635 /* walk through the Loads and create Pops for them */
636 for (++i; i <= maxslot; ++i) {
637 ir_node *load = loads[i];
639 const arch_register_t *reg;
641 mem = get_irn_n(load, n_ia32_mem);
642 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
644 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
645 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
647 copy_mark(load, pop);
649 /* create stackpointer Proj */
650 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
651 arch_set_irn_register(pred_sp, esp);
653 sched_add_before(irn, pop);
656 foreach_out_edge_safe(load, edge) {
657 ir_node *proj = get_edge_src_irn(edge);
659 set_Proj_pred(proj, pop);
662 /* we can remove the Load now */
667 be_set_IncSP_offset(irn, -ofs);
668 be_set_IncSP_pred(irn, pred_sp);
673 * Find a free GP register if possible, else return NULL.
675 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
677 be_irg_t *birg = be_birg_from_irg(irg);
680 for (i = 0; i < N_ia32_gp_REGS; ++i) {
681 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
682 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
685 if (be_peephole_get_value(reg->global_index) == NULL)
693 * Creates a Pop instruction before the given schedule point.
695 * @param dbgi debug info
696 * @param block the block
697 * @param stack the previous stack value
698 * @param schedpoint the new node is added before this node
699 * @param reg the register to pop
701 * @return the new stack value
703 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
704 ir_node *stack, ir_node *schedpoint,
705 const arch_register_t *reg)
707 const arch_register_t *esp = &ia32_registers[REG_ESP];
708 ir_graph *irg = get_irn_irg(block);
714 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
716 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
717 arch_set_irn_register(stack, esp);
718 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
719 arch_set_irn_register(val, reg);
721 sched_add_before(schedpoint, pop);
724 keep = be_new_Keep(block, 1, in);
725 sched_add_before(schedpoint, keep);
731 * Optimize an IncSp by replacing it with Push/Pop.
733 static void peephole_be_IncSP(ir_node *node)
735 const arch_register_t *esp = &ia32_registers[REG_ESP];
736 const arch_register_t *reg;
742 /* first optimize incsp->incsp combinations */
743 node = be_peephole_IncSP_IncSP(node);
745 /* transform IncSP->Store combinations to Push where possible */
746 peephole_IncSP_Store_to_push(node);
748 /* transform Load->IncSP combinations to Pop where possible */
749 peephole_Load_IncSP_to_pop(node);
751 if (arch_get_irn_register(node) != esp)
754 /* replace IncSP -4 by Pop freereg when possible */
755 offset = be_get_IncSP_offset(node);
756 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
757 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
758 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
759 (offset != +8 || ia32_cg_config.use_sub_esp_8))
763 /* we need a free register for pop */
764 reg = get_free_gp_reg(get_irn_irg(node));
768 dbgi = get_irn_dbg_info(node);
769 block = get_nodes_block(node);
770 stack = be_get_IncSP_pred(node);
772 stack = create_pop(dbgi, block, stack, node, reg);
775 stack = create_pop(dbgi, block, stack, node, reg);
778 dbgi = get_irn_dbg_info(node);
779 block = get_nodes_block(node);
780 stack = be_get_IncSP_pred(node);
781 stack = new_bd_ia32_PushEax(dbgi, block, stack);
782 arch_set_irn_register(stack, esp);
783 sched_add_before(node, stack);
786 stack = new_bd_ia32_PushEax(dbgi, block, stack);
787 arch_set_irn_register(stack, esp);
788 sched_add_before(node, stack);
792 be_peephole_exchange(node, stack);
796 * Peephole optimisation for ia32_Const's
798 static void peephole_ia32_Const(ir_node *node)
800 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
801 const arch_register_t *reg;
806 /* try to transform a mov 0, reg to xor reg reg */
807 if (attr->offset != 0 || attr->symconst != NULL)
809 if (ia32_cg_config.use_mov_0)
811 /* xor destroys the flags, so no-one must be using them */
812 if (be_peephole_get_value(REG_EFLAGS) != NULL)
815 reg = arch_get_irn_register(node);
816 assert(be_peephole_get_reg_value(reg) == NULL);
818 /* create xor(produceval, produceval) */
819 block = get_nodes_block(node);
820 dbgi = get_irn_dbg_info(node);
821 xorn = new_bd_ia32_Xor0(dbgi, block);
822 arch_set_irn_register(xorn, reg);
824 sched_add_before(node, xorn);
826 copy_mark(node, xorn);
827 be_peephole_exchange(node, xorn);
830 static inline int is_noreg(const ir_node *node)
832 return is_ia32_NoReg_GP(node);
835 ir_node *ia32_immediate_from_long(long val)
837 ir_graph *irg = current_ir_graph;
838 ir_node *start_block = get_irg_start_block(irg);
840 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
841 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
846 static ir_node *create_immediate_from_am(const ir_node *node)
848 ir_node *block = get_nodes_block(node);
849 int offset = get_ia32_am_offs_int(node);
850 int sc_sign = is_ia32_am_sc_sign(node);
851 const ia32_attr_t *attr = get_ia32_attr_const(node);
852 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
853 ir_entity *entity = get_ia32_am_sc(node);
856 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
858 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
862 static int is_am_one(const ir_node *node)
864 int offset = get_ia32_am_offs_int(node);
865 ir_entity *entity = get_ia32_am_sc(node);
867 return offset == 1 && entity == NULL;
870 static int is_am_minus_one(const ir_node *node)
872 int offset = get_ia32_am_offs_int(node);
873 ir_entity *entity = get_ia32_am_sc(node);
875 return offset == -1 && entity == NULL;
879 * Transforms a LEA into an Add or SHL if possible.
881 static void peephole_ia32_Lea(ir_node *node)
885 const arch_register_t *base_reg;
886 const arch_register_t *index_reg;
887 const arch_register_t *out_reg;
896 assert(is_ia32_Lea(node));
898 /* we can only do this if it is allowed to clobber the flags */
899 if (be_peephole_get_value(REG_EFLAGS) != NULL)
902 base = get_irn_n(node, n_ia32_Lea_base);
903 index = get_irn_n(node, n_ia32_Lea_index);
905 if (is_noreg(base)) {
909 base_reg = arch_get_irn_register(base);
911 if (is_noreg(index)) {
915 index_reg = arch_get_irn_register(index);
918 if (base == NULL && index == NULL) {
919 /* we shouldn't construct these in the first place... */
921 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
926 out_reg = arch_get_irn_register(node);
927 scale = get_ia32_am_scale(node);
928 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
929 /* check if we have immediates values (frame entities should already be
930 * expressed in the offsets) */
931 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
937 /* we can transform leas where the out register is the same as either the
938 * base or index register back to an Add or Shl */
939 if (out_reg == base_reg) {
942 if (!has_immediates) {
943 ir_fprintf(stderr, "Optimisation warning: found lea which is "
948 goto make_add_immediate;
950 if (scale == 0 && !has_immediates) {
955 /* can't create an add */
957 } else if (out_reg == index_reg) {
959 if (has_immediates && scale == 0) {
961 goto make_add_immediate;
962 } else if (!has_immediates && scale > 0) {
964 op2 = ia32_immediate_from_long(scale);
966 } else if (!has_immediates) {
968 ir_fprintf(stderr, "Optimisation warning: found lea which is "
972 } else if (scale == 0 && !has_immediates) {
977 /* can't create an add */
980 /* can't create an add */
985 if (ia32_cg_config.use_incdec) {
986 if (is_am_one(node)) {
987 dbgi = get_irn_dbg_info(node);
988 block = get_nodes_block(node);
989 res = new_bd_ia32_Inc(dbgi, block, op1);
990 arch_set_irn_register(res, out_reg);
993 if (is_am_minus_one(node)) {
994 dbgi = get_irn_dbg_info(node);
995 block = get_nodes_block(node);
996 res = new_bd_ia32_Dec(dbgi, block, op1);
997 arch_set_irn_register(res, out_reg);
1001 op2 = create_immediate_from_am(node);
1004 dbgi = get_irn_dbg_info(node);
1005 block = get_nodes_block(node);
1006 ir_graph *irg = get_irn_irg(node);
1007 ir_node *noreg = ia32_new_NoReg_gp(irg);
1008 ir_node *nomem = get_irg_no_mem(irg);
1009 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1010 arch_set_irn_register(res, out_reg);
1011 set_ia32_commutative(res);
1015 dbgi = get_irn_dbg_info(node);
1016 block = get_nodes_block(node);
1017 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1018 arch_set_irn_register(res, out_reg);
1022 SET_IA32_ORIG_NODE(res, node);
1024 /* add new ADD/SHL to schedule */
1025 DBG_OPT_LEA2ADD(node, res);
1027 /* exchange the Add and the LEA */
1028 sched_add_before(node, res);
1029 copy_mark(node, res);
1030 be_peephole_exchange(node, res);
1034 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1036 static void peephole_ia32_Imul_split(ir_node *imul)
1038 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1039 const arch_register_t *reg;
1042 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1043 /* no memory, imm form ignore */
1046 /* we need a free register */
1047 reg = get_free_gp_reg(get_irn_irg(imul));
1051 /* fine, we can rebuild it */
1052 res = ia32_turn_back_am(imul);
1053 arch_set_irn_register(res, reg);
1057 * Replace xorps r,r and xorpd r,r by pxor r,r
1059 static void peephole_ia32_xZero(ir_node *xorn)
1061 set_irn_op(xorn, op_ia32_xPzero);
1065 * Replace 16bit sign extension from ax to eax by shorter cwtl
1067 static void peephole_ia32_Conv_I2I(ir_node *node)
1069 const arch_register_t *eax = &ia32_registers[REG_EAX];
1070 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1071 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1076 if (get_mode_size_bits(smaller_mode) != 16 ||
1077 !mode_is_signed(smaller_mode) ||
1078 eax != arch_get_irn_register(val) ||
1079 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1082 dbgi = get_irn_dbg_info(node);
1083 block = get_nodes_block(node);
1084 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1085 arch_set_irn_register(cwtl, eax);
1086 sched_add_before(node, cwtl);
1087 be_peephole_exchange(node, cwtl);
1091 * Register a peephole optimisation function.
1093 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1095 assert(op->ops.generic == NULL);
1096 op->ops.generic = (op_func)func;
1099 /* Perform peephole-optimizations. */
1100 void ia32_peephole_optimization(ir_graph *irg)
1102 /* we currently do it in 2 passes because:
1103 * Lea -> Add could be usefull as flag producer for Test later
1107 ir_clear_opcodes_generic_func();
1108 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1109 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1110 if (ia32_cg_config.use_short_sex_eax)
1111 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1112 if (ia32_cg_config.use_pxor)
1113 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1114 if (! ia32_cg_config.use_imul_mem_imm32)
1115 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1116 be_peephole_opt(irg);
1119 ir_clear_opcodes_generic_func();
1120 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1121 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1122 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1123 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1124 be_peephole_opt(irg);
1128 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1129 * all its Projs are removed as well.
1130 * @param irn The irn to be removed from schedule
1132 static inline void try_kill(ir_node *node)
1134 if (get_irn_mode(node) == mode_T) {
1135 foreach_out_edge_safe(node, edge) {
1136 ir_node *proj = get_edge_src_irn(edge);
1141 if (get_irn_n_edges(node) != 0)
1144 if (sched_is_scheduled(node)) {
1151 static void optimize_conv_store(ir_node *node)
1156 ir_mode *store_mode;
1158 if (!is_ia32_Store(node))
1161 pred_proj = get_irn_n(node, n_ia32_Store_val);
1162 if (is_Proj(pred_proj)) {
1163 pred = get_Proj_pred(pred_proj);
1167 if (!is_ia32_Conv_I2I(pred))
1169 if (get_ia32_op_type(pred) != ia32_Normal)
1172 /* the store only stores the lower bits, so we only need the conv
1173 * it it shrinks the mode */
1174 conv_mode = get_ia32_ls_mode(pred);
1175 store_mode = get_ia32_ls_mode(node);
1176 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1179 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Store(Conv) (%+F, %+F)\n", node, pred);
1180 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1181 if (get_irn_n_edges(pred_proj) == 0) {
1182 kill_node(pred_proj);
1183 if (pred != pred_proj)
1188 static void optimize_load_conv(ir_node *node)
1190 ir_node *pred, *predpred;
1194 if (!is_ia32_Conv_I2I(node))
1197 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1201 predpred = get_Proj_pred(pred);
1202 if (!is_ia32_Load(predpred))
1205 /* the load is sign extending the upper bits, so we only need the conv
1206 * if it shrinks the mode */
1207 load_mode = get_ia32_ls_mode(predpred);
1208 conv_mode = get_ia32_ls_mode(node);
1209 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1212 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1213 /* change the load if it has only 1 user */
1214 if (get_irn_n_edges(pred) == 1) {
1216 if (get_mode_sign(conv_mode)) {
1217 newmode = find_signed_mode(load_mode);
1219 newmode = find_unsigned_mode(load_mode);
1221 assert(newmode != NULL);
1222 set_ia32_ls_mode(predpred, newmode);
1224 /* otherwise we have to keep the conv */
1230 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Load) (%+F, %+F)\n", node, predpred);
1231 exchange(node, pred);
1234 static void optimize_conv_conv(ir_node *node)
1236 ir_node *pred_proj, *pred, *result_conv;
1237 ir_mode *pred_mode, *conv_mode;
1241 if (!is_ia32_Conv_I2I(node))
1244 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1245 if (is_Proj(pred_proj))
1246 pred = get_Proj_pred(pred_proj);
1250 if (!is_ia32_Conv_I2I(pred))
1253 /* we know that after a conv, the upper bits are sign extended
1254 * so we only need the 2nd conv if it shrinks the mode */
1255 conv_mode = get_ia32_ls_mode(node);
1256 conv_mode_bits = get_mode_size_bits(conv_mode);
1257 pred_mode = get_ia32_ls_mode(pred);
1258 pred_mode_bits = get_mode_size_bits(pred_mode);
1260 if (conv_mode_bits == pred_mode_bits
1261 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1262 result_conv = pred_proj;
1263 } else if (conv_mode_bits <= pred_mode_bits) {
1264 /* if 2nd conv is smaller then first conv, then we can always take the
1266 if (get_irn_n_edges(pred_proj) == 1) {
1267 result_conv = pred_proj;
1268 set_ia32_ls_mode(pred, conv_mode);
1270 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1271 if (get_mode_size_bits(conv_mode) == 8) {
1272 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1273 set_irn_op(pred, op_ia32_Conv_I2I);
1274 arch_set_irn_register_reqs_in(pred, reqs);
1277 /* we don't want to end up with 2 loads, so we better do nothing */
1278 if (get_irn_mode(pred) == mode_T) {
1282 result_conv = exact_copy(pred);
1283 set_ia32_ls_mode(result_conv, conv_mode);
1285 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1286 if (get_mode_size_bits(conv_mode) == 8) {
1287 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1288 set_irn_op(result_conv, op_ia32_Conv_I2I);
1289 arch_set_irn_register_reqs_in(result_conv, reqs);
1293 /* if both convs have the same sign, then we can take the smaller one */
1294 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1295 result_conv = pred_proj;
1297 /* no optimisation possible if smaller conv is sign-extend */
1298 if (mode_is_signed(pred_mode)) {
1301 /* we can take the smaller conv if it is unsigned */
1302 result_conv = pred_proj;
1306 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Conv) (%+F, %+F)\n", node, pred);
1307 /* Some user (like Phis) won't be happy if we change the mode. */
1308 set_irn_mode(result_conv, get_irn_mode(node));
1311 exchange(node, result_conv);
1313 if (get_irn_n_edges(pred_proj) == 0) {
1314 kill_node(pred_proj);
1315 if (pred != pred_proj)
1318 optimize_conv_conv(result_conv);
1321 static void optimize_node(ir_node *node, void *env)
1325 optimize_load_conv(node);
1326 optimize_conv_store(node);
1327 optimize_conv_conv(node);
1331 * Performs conv and address mode optimization.
1333 void ia32_optimize_graph(ir_graph *irg)
1335 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1338 void ia32_init_optimize(void)
1340 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");