2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Christian Wuerdig
33 #include "firm_types.h"
43 #include "../benode_t.h"
44 #include "../besched_t.h"
46 #include "ia32_new_nodes.h"
47 #include "bearch_ia32_t.h"
48 #include "gen_ia32_regalloc_if.h"
49 #include "ia32_transform.h"
50 #include "ia32_dbg_stat.h"
51 #include "ia32_util.h"
53 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
55 //#define AGGRESSIVE_AM
58 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
59 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
60 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
61 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
64 typedef int is_op_func_t(const ir_node *n);
65 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
68 * checks if a node represents the NOREG value
70 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
71 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
74 /********************************************************************************************************
75 * _____ _ _ ____ _ _ _ _ _
76 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
77 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
78 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
79 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
80 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
83 ********************************************************************************************************/
86 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
89 // only optimize up to 48 stores behind IncSPs
90 #define MAXPUSH_OPTIMIZE 48
93 * Tries to create pushs from IncSP,Store combinations
95 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
99 ir_node *stores[MAXPUSH_OPTIMIZE];
100 ir_node *block = get_nodes_block(irn);
101 ir_graph *irg = cg->irg;
103 ir_mode *spmode = get_irn_mode(irn);
105 memset(stores, 0, sizeof(stores));
107 assert(be_is_IncSP(irn));
109 offset = be_get_IncSP_offset(irn);
114 * We first walk the schedule after the IncSP node as long as we find
115 * suitable stores that could be transformed to a push.
116 * We save them into the stores array which is sorted by the frame offset/4
117 * attached to the node
119 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
124 // it has to be a store
125 if(!is_ia32_Store(node))
128 // it has to use our sp value
129 if(get_irn_n(node, 0) != irn)
131 // store has to be attached to NoMem
132 mem = get_irn_n(node, 3);
137 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
140 offset = get_ia32_am_offs_int(node);
142 storeslot = offset / 4;
143 if(storeslot >= MAXPUSH_OPTIMIZE)
146 // storing into the same slot twice is bad (and shouldn't happen...)
147 if(stores[storeslot] != NULL)
150 // storing at half-slots is bad
154 stores[storeslot] = node;
157 curr_sp = get_irn_n(irn, 0);
159 // walk the stores in inverse order and create pushs for them
160 i = (offset / 4) - 1;
161 if(i >= MAXPUSH_OPTIMIZE) {
162 i = MAXPUSH_OPTIMIZE - 1;
165 for( ; i >= 0; --i) {
166 const arch_register_t *spreg;
168 ir_node *val, *mem, *mem_proj;
169 ir_node *store = stores[i];
170 ir_node *noreg = ia32_new_NoReg_gp(cg);
172 if(store == NULL || is_Bad(store))
175 val = get_irn_n(store, 2);
176 mem = get_irn_n(store, 3);
177 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
179 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, val, curr_sp, mem);
181 set_ia32_am_support(push, ia32_am_Source, ia32_am_unary);
182 copy_ia32_Immop_attr(push, store);
184 sched_add_before(irn, push);
186 // create stackpointer proj
187 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
188 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
190 // create memory proj
191 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
193 // use the memproj now
194 exchange(store, mem_proj);
196 // we can remove the store now
202 be_set_IncSP_offset(irn, offset);
204 // can we remove the IncSP now?
206 const ir_edge_t *edge, *next;
208 foreach_out_edge_safe(irn, edge, next) {
209 ir_node *arg = get_edge_src_irn(edge);
210 int pos = get_edge_src_pos(edge);
212 set_irn_n(arg, pos, curr_sp);
215 set_irn_n(irn, 0, new_Bad());
218 set_irn_n(irn, 0, curr_sp);
223 * Tries to optimize two following IncSP.
225 static void ia32_optimize_IncSP(ir_node *node)
230 ir_node *pred = be_get_IncSP_pred(node);
233 if(!be_is_IncSP(pred))
236 if(get_irn_n_edges(pred) > 1)
239 pred_offs = be_get_IncSP_offset(pred);
240 curr_offs = be_get_IncSP_offset(node);
242 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
243 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
247 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
248 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
252 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
253 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
256 offs = curr_offs + pred_offs;
259 be_set_IncSP_offset(node, offs);
261 /* rewire dependency edges */
262 predpred = be_get_IncSP_pred(pred);
263 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
266 be_set_IncSP_pred(node, predpred);
272 * Performs Peephole Optimizations.
274 static void ia32_peephole_optimize_node(ir_node *node, void *env) {
275 ia32_code_gen_t *cg = env;
277 if (be_is_IncSP(node)) {
278 ia32_optimize_IncSP(node);
280 if (cg->opt & IA32_OPT_PUSHARGS)
281 ia32_create_Pushs(node, cg);
285 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
286 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
289 /******************************************************************
291 * /\ | | | | | \/ | | |
292 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
293 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
294 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
295 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
297 ******************************************************************/
304 static int node_is_ia32_comm(const ir_node *irn) {
305 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
308 static int ia32_get_irn_n_edges(const ir_node *irn) {
309 const ir_edge_t *edge;
312 foreach_out_edge(irn, edge) {
320 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
322 * @param pred The node to be checked
323 * @param is_op_func The check-function
324 * @return 1 if conditions are fulfilled, 0 otherwise
326 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
327 return is_op_func(pred);
331 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
332 * and if the predecessor is in block bl.
334 * @param bl The block
335 * @param pred The node to be checked
336 * @param is_op_func The check-function
337 * @return 1 if conditions are fulfilled, 0 otherwise
339 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
340 int (*is_op_func)(const ir_node *n))
343 pred = get_Proj_pred(pred);
344 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
353 * Checks if irn is a candidate for address calculation. We avoid transforming
354 * adds to leas if they have a load as pred, because then we can use AM mode
357 * - none of the operand must be a Load within the same block OR
358 * - all Loads must have more than one user OR
360 * @param block The block the Loads must/mustnot be in
361 * @param irn The irn to check
362 * return 1 if irn is a candidate, 0 otherwise
364 static int is_addr_candidate(const ir_node *irn)
366 #ifndef AGGRESSIVE_AM
367 const ir_node *block = get_nodes_block(irn);
368 ir_node *left, *right;
371 left = get_irn_n(irn, 2);
372 right = get_irn_n(irn, 3);
374 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
375 n = ia32_get_irn_n_edges(left);
376 /* load with only one user: don't create LEA */
381 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
382 n = ia32_get_irn_n_edges(right);
393 * Checks if irn is a candidate for address mode.
396 * - at least one operand has to be a Load within the same block AND
397 * - the load must not have other users than the irn AND
398 * - the irn must not have a frame entity set
400 * @param cg The ia32 code generator
401 * @param h The height information of the irg
402 * @param block The block the Loads must/mustnot be in
403 * @param irn The irn to check
404 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
406 static ia32_am_cand_t is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
407 ir_node *in, *load, *other, *left, *right;
408 int is_cand = 0, cand;
411 if (is_ia32_Ld(irn) || is_ia32_St(irn) ||
412 is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
413 is_ia32_xStoreSimple(irn))
416 if(get_ia32_frame_ent(irn) != NULL)
417 return IA32_AM_CAND_NONE;
419 left = get_irn_n(irn, 2);
420 arity = get_irn_arity(irn);
421 if(get_ia32_am_arity(irn) == ia32_am_binary) {
423 right = get_irn_n(irn, 3);
425 assert(get_ia32_am_arity(irn) == ia32_am_unary);
432 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
433 #ifndef AGGRESSIVE_AM
435 n = ia32_get_irn_n_edges(in);
436 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
441 load = get_Proj_pred(in);
444 /* 8bit Loads are not supported (for binary ops),
445 * they cannot be used with every register */
446 if (get_ia32_am_arity(irn) == ia32_am_binary &&
447 get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
451 /* If there is a data dependency of other irn from load: cannot use AM */
452 if (is_cand && get_nodes_block(other) == block) {
453 other = skip_Proj(other);
454 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
455 /* this could happen in loops */
456 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
460 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
464 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
465 #ifndef AGGRESSIVE_AM
467 n = ia32_get_irn_n_edges(in);
468 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
473 load = get_Proj_pred(in);
476 /* 8bit Loads are not supported, they cannot be used with every register */
477 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
480 /* If there is a data dependency of other irn from load: cannot use load */
481 if (is_cand && get_nodes_block(other) == block) {
482 other = skip_Proj(other);
483 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
484 /* this could happen in loops */
485 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
489 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
491 /* if the irn has a frame entity: we do not use address mode */
496 * Compares the base and index addr and the load/store entities
497 * and returns 1 if they are equal.
499 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
500 const ir_node *addr_b, const ir_node *addr_i)
502 if(get_irn_n(load, 0) != addr_b)
504 if(get_irn_n(load, 1) != addr_i)
507 if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
510 if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
512 if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
514 if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
516 if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
522 typedef enum _ia32_take_lea_attr {
523 IA32_LEA_ATTR_NONE = 0,
524 IA32_LEA_ATTR_BASE = (1 << 0),
525 IA32_LEA_ATTR_INDEX = (1 << 1),
526 IA32_LEA_ATTR_OFFS = (1 << 2),
527 IA32_LEA_ATTR_SCALE = (1 << 3),
528 IA32_LEA_ATTR_AMSC = (1 << 4),
529 IA32_LEA_ATTR_FENT = (1 << 5)
530 } ia32_take_lea_attr;
533 * Decides if we have to keep the LEA operand or if we can assimilate it.
535 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
536 int have_am_sc, ia32_code_gen_t *cg)
538 ir_entity *irn_ent = get_ia32_frame_ent(irn);
539 ir_entity *lea_ent = get_ia32_frame_ent(lea);
541 int is_noreg_base = be_is_NoReg(cg, base);
542 int is_noreg_index = be_is_NoReg(cg, index);
543 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
545 /* If the Add and the LEA both have a different frame entity set: keep */
546 if (irn_ent && lea_ent && (irn_ent != lea_ent))
547 return IA32_LEA_ATTR_NONE;
548 else if (! irn_ent && lea_ent)
549 ret_val |= IA32_LEA_ATTR_FENT;
551 /* If the Add and the LEA both have already an address mode symconst: keep */
552 if (have_am_sc && get_ia32_am_sc(lea))
553 return IA32_LEA_ATTR_NONE;
554 else if (get_ia32_am_sc(lea))
555 ret_val |= IA32_LEA_ATTR_AMSC;
557 /* Check the different base-index combinations */
559 if (! is_noreg_base && ! is_noreg_index) {
560 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
561 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
562 if (am_flav & ia32_O)
563 ret_val |= IA32_LEA_ATTR_OFFS;
565 ret_val |= IA32_LEA_ATTR_BASE;
568 return IA32_LEA_ATTR_NONE;
570 else if (! is_noreg_base && is_noreg_index) {
571 /* Base is set but index not */
573 /* Base points to LEA: assimilate everything */
574 if (am_flav & ia32_O)
575 ret_val |= IA32_LEA_ATTR_OFFS;
576 if (am_flav & ia32_S)
577 ret_val |= IA32_LEA_ATTR_SCALE;
578 if (am_flav & ia32_I)
579 ret_val |= IA32_LEA_ATTR_INDEX;
581 ret_val |= IA32_LEA_ATTR_BASE;
583 else if (am_flav & ia32_B ? 0 : 1) {
584 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
585 if (am_flav & ia32_O)
586 ret_val |= IA32_LEA_ATTR_OFFS;
587 if (am_flav & ia32_S)
588 ret_val |= IA32_LEA_ATTR_SCALE;
590 ret_val |= IA32_LEA_ATTR_INDEX;
593 return IA32_LEA_ATTR_NONE;
595 else if (is_noreg_base && ! is_noreg_index) {
596 /* Index is set but not base */
598 /* Index points to LEA: assimilate everything */
599 if (am_flav & ia32_O)
600 ret_val |= IA32_LEA_ATTR_OFFS;
601 if (am_flav & ia32_S)
602 ret_val |= IA32_LEA_ATTR_SCALE;
603 if (am_flav & ia32_B)
604 ret_val |= IA32_LEA_ATTR_BASE;
606 ret_val |= IA32_LEA_ATTR_INDEX;
608 else if (am_flav & ia32_I ? 0 : 1) {
609 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
610 if (am_flav & ia32_O)
611 ret_val |= IA32_LEA_ATTR_OFFS;
612 if (am_flav & ia32_S)
613 ret_val |= IA32_LEA_ATTR_SCALE;
615 ret_val |= IA32_LEA_ATTR_BASE;
618 return IA32_LEA_ATTR_NONE;
621 assert(0 && "There must have been set base or index");
628 * Adds res before irn into schedule if irn was scheduled.
629 * @param irn The schedule point
630 * @param res The node to be scheduled
632 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
633 if (sched_is_scheduled(irn))
634 sched_add_before(irn, res);
638 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
639 * all it's Projs are removed as well.
640 * @param irn The irn to be removed from schedule
642 static INLINE void try_kill(ir_node *node)
644 if(get_irn_mode(node) == mode_T) {
645 const ir_edge_t *edge, *next;
646 foreach_out_edge_safe(node, edge, next) {
647 ir_node *proj = get_edge_src_irn(edge);
652 if(get_irn_n_edges(node) != 0)
655 if (sched_is_scheduled(node)) {
663 * Folds Add or Sub to LEA if possible
665 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
666 ir_graph *irg = get_irn_irg(irn);
667 dbg_info *dbg_info = get_irn_dbg_info(irn);
668 ir_node *block = get_nodes_block(irn);
670 ir_node *shift = NULL;
671 ir_node *lea_o = NULL;
681 ir_entity *am_sc = NULL;
682 ir_entity *lea_ent = NULL;
683 ir_node *noreg = ia32_new_NoReg_gp(cg);
684 ir_node *left, *right, *temp;
685 ir_node *base, *index;
686 int consumed_left_shift;
687 ia32_am_flavour_t am_flav;
689 if (is_ia32_Add(irn))
692 left = get_irn_n(irn, 2);
693 right = get_irn_n(irn, 3);
695 /* "normalize" arguments in case of add with two operands */
696 if (isadd && ! be_is_NoReg(cg, right)) {
697 /* put LEA == ia32_am_O as right operand */
698 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
699 set_irn_n(irn, 2, right);
700 set_irn_n(irn, 3, left);
706 /* put LEA != ia32_am_O as left operand */
707 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
708 set_irn_n(irn, 2, right);
709 set_irn_n(irn, 3, left);
715 /* put SHL as left operand iff left is NOT a LEA */
716 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
717 set_irn_n(irn, 2, right);
718 set_irn_n(irn, 3, left);
731 /* check for operation with immediate */
732 if (is_ia32_ImmConst(irn)) {
733 tarval *tv = get_ia32_Immop_tarval(irn);
735 DBG((dbg, LEVEL_1, "\tfound op with imm const"));
737 offs_cnst = get_tarval_long(tv);
740 else if (isadd && is_ia32_ImmSymConst(irn)) {
741 DBG((dbg, LEVEL_1, "\tfound op with imm symconst"));
745 am_sc = get_ia32_Immop_symconst(irn);
746 am_sc_sign = is_ia32_am_sc_sign(irn);
749 /* determine the operand which needs to be checked */
750 temp = be_is_NoReg(cg, right) ? left : right;
752 /* check if right operand is AMConst (LEA with ia32_am_O) */
753 /* but we can only eat it up if there is no other symconst */
754 /* because the linker won't accept two symconsts */
755 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
756 DBG((dbg, LEVEL_1, "\tgot op with LEA am_O"));
758 offs_lea = get_ia32_am_offs_int(temp);
759 am_sc = get_ia32_am_sc(temp);
760 am_sc_sign = is_ia32_am_sc_sign(temp);
767 else if (temp == right)
772 /* default for add -> make right operand to index */
775 consumed_left_shift = -1;
777 DBG((dbg, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
779 /* determine the operand which needs to be checked */
781 if (is_ia32_Lea(left)) {
783 consumed_left_shift = 0;
786 /* check for SHL 1,2,3 */
787 if (pred_is_specific_node(temp, is_ia32_Shl)) {
788 ir_node *right = get_irn_n(temp, n_ia32_Shl_right);
790 if (is_ia32_Immediate(right)) {
791 const ia32_immediate_attr_t *attr
792 = get_ia32_immediate_attr_const(right);
793 long shiftval = attr->offset;
796 index = get_irn_n(temp, 2);
797 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
801 DBG((dbg, LEVEL_1, "\tgot scaled index %+F\n", index));
807 if (! be_is_NoReg(cg, index)) {
808 /* if we have index, but left == right -> no base */
812 else if (consumed_left_shift == 1) {
813 /* -> base is right operand */
814 base = (right == lea_o) ? noreg : right;
819 /* Try to assimilate a LEA as left operand */
820 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
821 /* check if we can assimilate the LEA */
822 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
824 if (take_attr == IA32_LEA_ATTR_NONE) {
825 DBG((dbg, LEVEL_1, "\tleave old LEA, creating new one\n"));
828 DBG((dbg, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
829 lea = left; /* for statistics */
831 if (take_attr & IA32_LEA_ATTR_OFFS)
832 offs = get_ia32_am_offs_int(left);
834 if (take_attr & IA32_LEA_ATTR_AMSC) {
835 am_sc = get_ia32_am_sc(left);
837 am_sc_sign = is_ia32_am_sc_sign(left);
840 if (take_attr & IA32_LEA_ATTR_SCALE)
841 scale = get_ia32_am_scale(left);
843 if (take_attr & IA32_LEA_ATTR_BASE)
844 base = get_irn_n(left, 0);
846 if (take_attr & IA32_LEA_ATTR_INDEX)
847 index = get_irn_n(left, 1);
849 if (take_attr & IA32_LEA_ATTR_FENT)
850 lea_ent = get_ia32_frame_ent(left);
854 /* ok, we can create a new LEA */
856 res = new_rd_ia32_Lea(dbg_info, irg, block, base, index);
857 /* we don't want stuff before the barrier... */
858 if(be_is_NoReg(cg, base) && be_is_NoReg(cg, index)) {
859 add_irn_dep(res, get_irg_frame(irg));
862 /* add the old offset of a previous LEA */
863 add_ia32_am_offs_int(res, offs);
865 /* add the new offset */
867 add_ia32_am_offs_int(res, offs_cnst);
868 add_ia32_am_offs_int(res, offs_lea);
870 /* either lea_O-cnst, -cnst or -lea_O */
871 if (offs_cnst != 0) {
872 add_ia32_am_offs_int(res, offs_lea);
873 add_ia32_am_offs_int(res, -offs_cnst);
875 add_ia32_am_offs_int(res, offs_lea);
879 /* set the address mode symconst */
881 set_ia32_am_sc(res, am_sc);
883 set_ia32_am_sc_sign(res);
886 /* copy the frame entity (could be set in case of Add */
887 /* which was a FrameAddr) */
888 if (lea_ent != NULL) {
889 set_ia32_frame_ent(res, lea_ent);
890 set_ia32_use_frame(res);
892 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
893 if(is_ia32_use_frame(irn))
894 set_ia32_use_frame(res);
898 set_ia32_am_scale(res, scale);
901 /* determine new am flavour */
902 if (offs || offs_cnst || offs_lea || have_am_sc) {
905 if (! be_is_NoReg(cg, base)) {
908 if (! be_is_NoReg(cg, index)) {
914 set_ia32_am_flavour(res, am_flav);
916 set_ia32_op_type(res, ia32_AddrModeS);
918 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
920 DBG((dbg, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
922 assert(irn && "Couldn't find result proj");
924 /* get the result Proj of the Add/Sub */
925 try_add_to_sched(irn, res);
927 /* exchange the old op with the new LEA */
931 /* we will exchange it, report here before the Proj is created */
932 if (shift && lea && lea_o) {
936 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
937 } else if (shift && lea) {
940 DBG_OPT_LEA3(irn, lea, shift, res);
941 } else if (shift && lea_o) {
944 DBG_OPT_LEA3(irn, lea_o, shift, res);
945 } else if (lea && lea_o) {
948 DBG_OPT_LEA3(irn, lea_o, lea, res);
951 DBG_OPT_LEA2(irn, shift, res);
954 DBG_OPT_LEA2(irn, lea, res);
957 DBG_OPT_LEA2(irn, lea_o, res);
959 DBG_OPT_LEA1(irn, res);
968 * Merges a Load/Store node with a LEA.
969 * @param irn The Load/Store node
972 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
973 ir_entity *irn_ent = get_ia32_frame_ent(irn);
974 ir_entity *lea_ent = get_ia32_frame_ent(lea);
976 /* If the irn and the LEA both have a different frame entity set: do not merge */
977 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
979 else if (irn_ent == NULL && lea_ent != NULL) {
980 set_ia32_frame_ent(irn, lea_ent);
981 set_ia32_use_frame(irn);
984 /* get the AM attributes from the LEA */
985 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
986 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
987 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
989 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
990 if (is_ia32_am_sc_sign(lea))
991 set_ia32_am_sc_sign(irn);
993 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
995 /* set base and index */
996 set_irn_n(irn, 0, get_irn_n(lea, 0));
997 set_irn_n(irn, 1, get_irn_n(lea, 1));
1001 /* clear remat flag */
1002 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1004 if (is_ia32_Ld(irn))
1005 DBG_OPT_LOAD_LEA(lea, irn);
1007 DBG_OPT_STORE_LEA(lea, irn);
1012 * Sets new_right index of irn to right and new_left index to left.
1013 * Also exchange left and right
1015 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right,
1016 int new_left, int new_right)
1020 assert(is_ia32_commutative(irn));
1022 set_irn_n(irn, new_right, *right);
1023 set_irn_n(irn, new_left, *left);
1029 /* this is only needed for Compares, but currently ALL nodes
1030 * have this attribute :-) */
1031 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1035 * Performs address calculation optimization (create LEAs if possible)
1037 static void optimize_lea(ia32_code_gen_t *cg, ir_node *irn) {
1038 if (! is_ia32_irn(irn))
1041 /* Following cases can occur: */
1042 /* - Sub (l, imm) -> LEA [base - offset] */
1043 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1044 /* - Add (l, imm) -> LEA [base + offset] */
1045 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1046 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1047 /* - Add (l, r) -> LEA [base + index * scale] */
1048 /* with scale > 1 iff l/r == shl (1,2,3) */
1049 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1052 if(!is_addr_candidate(irn))
1055 DBG((dbg, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1056 res = fold_addr(cg, irn);
1059 DB((dbg, LEVEL_1, "transformed into %+F\n", res));
1061 DB((dbg, LEVEL_1, "not transformed\n"));
1062 } else if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
1063 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1064 /* - Store -> LEA into Store } it might be better to keep the LEA */
1065 ir_node *left = get_irn_n(irn, 0);
1067 if (is_ia32_Lea(left)) {
1068 const ir_edge_t *edge, *ne;
1071 /* merge all Loads/Stores connected to this LEA with the LEA */
1072 foreach_out_edge_safe(left, edge, ne) {
1073 src = get_edge_src_irn(edge);
1075 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src))) {
1076 DBG((dbg, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1077 if (! is_ia32_got_lea(src))
1078 merge_loadstore_lea(src, left);
1079 set_ia32_got_lea(src);
1086 static void optimize_conv_store(ir_node *node)
1090 ir_mode *store_mode;
1092 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1095 pred = get_irn_n(node, 2);
1096 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1099 /* the store only stores the lower bits, so we only need the conv
1100 * it it shrinks the mode */
1101 conv_mode = get_ia32_ls_mode(pred);
1102 store_mode = get_ia32_ls_mode(node);
1103 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1106 set_irn_n(node, 2, get_irn_n(pred, 2));
1107 if(get_irn_n_edges(pred) == 0) {
1112 static void optimize_load_conv(ir_node *node)
1114 ir_node *pred, *predpred;
1118 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1121 pred = get_irn_n(node, 2);
1125 predpred = get_Proj_pred(pred);
1126 if(!is_ia32_Load(predpred))
1129 /* the load is sign extending the upper bits, so we only need the conv
1130 * if it shrinks the mode */
1131 load_mode = get_ia32_ls_mode(predpred);
1132 conv_mode = get_ia32_ls_mode(node);
1133 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1136 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1137 /* change the load if it has only 1 user */
1138 if(get_irn_n_edges(pred) == 1) {
1140 if(get_mode_sign(conv_mode)) {
1141 newmode = find_signed_mode(load_mode);
1143 newmode = find_unsigned_mode(load_mode);
1145 assert(newmode != NULL);
1146 set_ia32_ls_mode(predpred, newmode);
1148 /* otherwise we have to keep the conv */
1154 exchange(node, pred);
1157 static void optimize_conv_conv(ir_node *node)
1163 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1166 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1167 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1168 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1171 /* we know that after a conv, the upper bits are sign extended
1172 * so we only need the 2nd conv if it shrinks the mode */
1173 conv_mode = get_ia32_ls_mode(node);
1174 pred_mode = get_ia32_ls_mode(pred);
1175 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(pred_mode))
1178 /* we can't eliminate an upconv signed->unsigned */
1179 if (get_mode_size_bits(conv_mode) != get_mode_size_bits(pred_mode) &&
1180 !get_mode_sign(conv_mode) && get_mode_sign(pred_mode))
1184 exchange(node, pred);
1187 static void optimize_node(ir_node *node, void *env)
1189 ia32_code_gen_t *cg = env;
1191 optimize_load_conv(node);
1192 optimize_conv_store(node);
1193 optimize_conv_conv(node);
1194 optimize_lea(cg, node);
1198 * Checks for address mode patterns and performs the
1199 * necessary transformations.
1200 * This function is called by a walker.
1202 static void optimize_am(ir_node *irn, void *env) {
1203 ia32_am_opt_env_t *am_opt_env = env;
1204 ia32_code_gen_t *cg = am_opt_env->cg;
1205 ir_graph *irg = get_irn_irg(irn);
1206 heights_t *h = am_opt_env->h;
1207 ir_node *block, *left, *right;
1208 ir_node *store, *load, *mem_proj;
1209 ir_node *addr_b, *addr_i;
1210 int need_exchange_on_fail = 0;
1211 ia32_am_type_t am_support;
1212 ia32_am_arity_t am_arity;
1213 ia32_am_cand_t cand;
1214 ia32_am_cand_t orig_cand;
1216 int source_possible;
1218 static const arch_register_req_t dest_out_reg_req_0 = {
1219 arch_register_req_type_none,
1220 NULL, /* regclass */
1221 NULL, /* limit bitset */
1223 -1 /* different pos */
1225 static const arch_register_req_t *dest_am_out_reqs[] = {
1229 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn))
1231 if (is_ia32_Lea(irn))
1234 am_support = get_ia32_am_support(irn);
1235 am_arity = get_ia32_am_arity(irn);
1236 block = get_nodes_block(irn);
1238 /* fold following patterns:
1239 * - op -> Load into AMop with am_Source
1241 * - op is am_Source capable AND
1242 * - the Load is only used by this op AND
1243 * - the Load is in the same block
1244 * - Store -> op -> Load into AMop with am_Dest
1246 * - op is am_Dest capable AND
1247 * - the Store uses the same address as the Load AND
1248 * - the Load is only used by this op AND
1249 * - the Load and Store are in the same block AND
1250 * - nobody else uses the result of the op
1252 if (am_support == ia32_am_None)
1255 assert(am_arity == ia32_am_unary || am_arity == ia32_am_binary);
1257 cand = is_am_candidate(h, block, irn);
1258 if (cand == IA32_AM_CAND_NONE)
1262 DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F (candleft %d candright %d)... \n", irn,
1263 cand & IA32_AM_CAND_LEFT, cand & IA32_AM_CAND_RIGHT));
1265 left = get_irn_n(irn, 2);
1266 if (am_arity == ia32_am_unary) {
1267 assert(get_irn_arity(irn) >= 4);
1269 assert(cand == IA32_AM_CAND_BOTH);
1271 assert(get_irn_arity(irn) >= 5);
1272 right = get_irn_n(irn, 3);
1275 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1276 source_possible = am_support & ia32_am_Source ? 1 : 0;
1278 DBG((dbg, LEVEL_2, "\tdest_possible %d source_possible %d ... \n", dest_possible, source_possible));
1280 if (dest_possible) {
1285 /* we should only have 1 user which is a store */
1286 if (ia32_get_irn_n_edges(irn) == 1) {
1287 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1289 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1291 addr_b = get_irn_n(store, 0);
1292 addr_i = get_irn_n(store, 1);
1296 if (store == NULL) {
1297 DBG((dbg, LEVEL_2, "\tno store found, not using dest_mode\n"));
1302 if (dest_possible) {
1303 /* normalize nodes, we need the interesting load on the left side */
1304 if (cand & IA32_AM_CAND_RIGHT) {
1305 load = get_Proj_pred(right);
1306 if (load_store_addr_is_equal(load, store, addr_b, addr_i)
1307 && node_is_ia32_comm(irn)) {
1308 DBG((dbg, LEVEL_2, "\texchanging left/right\n"));
1309 exchange_left_right(irn, &left, &right, 3, 2);
1310 need_exchange_on_fail ^= 1;
1311 if (cand == IA32_AM_CAND_RIGHT)
1312 cand = IA32_AM_CAND_LEFT;
1317 if (dest_possible) {
1318 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1319 load = get_Proj_pred(left);
1321 #ifndef AGGRESSIVE_AM
1322 /* we have to be the only user of the load */
1323 if (get_irn_n_edges(left) > 1) {
1324 DBG((dbg, LEVEL_2, "\tmatching load has too may users, not using dest_mode\n"));
1329 DBG((dbg, LEVEL_2, "\tno matching load found, not using dest_mode"));
1334 if (dest_possible) {
1335 /* the store has to use the loads memory or the same memory
1337 ir_node *loadmem = get_irn_n(load, 2);
1338 ir_node *storemem = get_irn_n(store, 3);
1339 assert(get_irn_mode(loadmem) == mode_M);
1340 assert(get_irn_mode(storemem) == mode_M);
1341 /* TODO there could be a sync between store and load... */
1342 if(storemem != loadmem && (!is_Proj(storemem) || get_Proj_pred(storemem) != load)) {
1343 DBG((dbg, LEVEL_2, "\tload/store using different memories, not using dest_mode"));
1348 if (dest_possible) {
1349 /* Compare Load and Store address */
1350 if (!load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1351 DBG((dbg, LEVEL_2, "\taddresses not equal, not using dest_mode"));
1356 if (dest_possible) {
1357 ir_mode *lsmode = get_ia32_ls_mode(load);
1358 if(get_mode_size_bits(lsmode) != 32) {
1363 if (dest_possible) {
1364 /* all conditions fullfilled, do the transformation */
1365 assert(cand & IA32_AM_CAND_LEFT);
1367 /* set new base, index and attributes */
1368 set_irn_n(irn, 0, addr_b);
1369 set_irn_n(irn, 1, addr_i);
1370 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1371 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1372 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1373 set_ia32_op_type(irn, ia32_AddrModeD);
1374 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1375 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1377 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1378 if (is_ia32_am_sc_sign(load))
1379 set_ia32_am_sc_sign(irn);
1381 /* connect to Load memory and disconnect Load */
1382 if (am_arity == ia32_am_binary) {
1384 set_irn_n(irn, 4, get_irn_n(load, 2));
1385 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1388 set_irn_n(irn, 3, get_irn_n(load, 2));
1389 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1392 /* change node mode and out register requirements */
1393 set_irn_mode(irn, mode_M);
1394 set_ia32_out_req_all(irn, dest_am_out_reqs);
1396 /* connect the memory Proj of the Store to the op */
1397 edges_reroute(store, irn, irg);
1399 /* clear remat flag */
1400 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1404 DBG_OPT_AM_D(load, store, irn);
1406 DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1407 need_exchange_on_fail = 0;
1408 source_possible = 0;
1411 if (source_possible) {
1412 /* normalize ops, we need the load on the right */
1413 if(cand == IA32_AM_CAND_LEFT) {
1414 if(node_is_ia32_comm(irn)) {
1415 exchange_left_right(irn, &left, &right, 3, 2);
1416 need_exchange_on_fail ^= 1;
1417 cand = IA32_AM_CAND_RIGHT;
1419 source_possible = 0;
1424 if (source_possible) {
1425 /* all conditions fullfilled, do transform */
1426 assert(cand & IA32_AM_CAND_RIGHT);
1427 load = get_Proj_pred(right);
1429 if(get_irn_n_edges(load) > 1) {
1430 source_possible = 0;
1434 if (source_possible) {
1435 ir_mode *ls_mode = get_ia32_ls_mode(load);
1436 if(get_mode_size_bits(ls_mode) != 32
1437 || ls_mode == mode_D)
1438 source_possible = 0;
1442 if (source_possible) {
1443 addr_b = get_irn_n(load, 0);
1444 addr_i = get_irn_n(load, 1);
1446 /* set new base, index and attributes */
1447 set_irn_n(irn, 0, addr_b);
1448 set_irn_n(irn, 1, addr_i);
1449 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1450 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1451 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1452 set_ia32_op_type(irn, ia32_AddrModeS);
1453 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1454 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1456 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1457 if (is_ia32_am_sc_sign(load))
1458 set_ia32_am_sc_sign(irn);
1460 /* clear remat flag */
1461 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1463 if (is_ia32_use_frame(load)) {
1464 if(get_ia32_frame_ent(load) == NULL) {
1465 set_ia32_need_stackent(irn);
1467 set_ia32_use_frame(irn);
1470 /* connect to Load memory and disconnect Load */
1471 if (am_arity == ia32_am_binary) {
1473 right = ia32_get_admissible_noreg(cg, irn, 3);
1474 set_irn_n(irn, 3, right);
1475 set_irn_n(irn, 4, get_irn_n(load, n_ia32_Load_mem));
1478 right = ia32_get_admissible_noreg(cg, irn, 2);
1479 set_irn_n(irn, 2, right);
1480 set_irn_n(irn, 3, get_irn_n(load, n_ia32_Load_mem));
1483 DBG_OPT_AM_S(load, irn);
1485 /* If Load has a memory Proj, connect it to the op */
1486 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1487 if (mem_proj != NULL) {
1489 ir_mode *mode = get_irn_mode(irn);
1491 assert(mode != mode_T);
1493 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1494 get_nodes_block(irn), new_Unknown(mode_T),
1496 set_irn_mode(irn, mode_T);
1497 edges_reroute(irn, res_proj, irg);
1498 set_Proj_pred(res_proj, irn);
1500 set_Proj_pred(mem_proj, irn);
1501 set_Proj_proj(mem_proj, 1);
1505 need_exchange_on_fail = 0;
1507 /* immediate are only allowed on the right side */
1508 if(is_ia32_Immediate(left)) {
1509 exchange_left_right(irn, &left, &right, 3, 2);
1512 DB((dbg, LEVEL_1, "merged with %+F into source AM\n", load));
1515 /* was exchanged but optimize failed: exchange back */
1516 if (need_exchange_on_fail) {
1517 exchange_left_right(irn, &left, &right, 3, 2);
1522 * Performs conv and address mode optimization.
1524 void ia32_optimize_graph(ia32_code_gen_t *cg) {
1525 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1526 if (! (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA))) {
1527 /* no optimizations at all */
1531 /* beware: we cannot optimize LEA and AM in one run because */
1532 /* LEA optimization adds new nodes to the irg which */
1533 /* invalidates the phase data */
1535 if (cg->opt & IA32_OPT_LEA) {
1536 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1540 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1542 /* hack for now, so these don't get created during optimize, because then
1543 * they will be unknown to the heights module
1545 ia32_new_NoReg_gp(cg);
1546 ia32_new_NoReg_fp(cg);
1547 ia32_new_NoReg_vfp(cg);
1549 if (cg->opt & IA32_OPT_DOAM) {
1550 /* we need height information for am optimization */
1551 heights_t *h = heights_new(cg->irg);
1552 ia32_am_opt_env_t env;
1557 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
1563 void ia32_init_optimize(void)
1565 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");