3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universität Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
27 #include "../benode_t.h"
28 #include "../besched_t.h"
30 #include "ia32_new_nodes.h"
31 #include "bearch_ia32_t.h"
32 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
33 #include "ia32_transform.h"
34 #include "ia32_dbg_stat.h"
37 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
39 typedef int is_op_func_t(const ir_node *n);
42 * checks if a node represents the NOREG value
44 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
45 be_abi_irg_t *babi = cg->birg->abi;
46 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
47 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
49 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
50 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
55 /*************************************************
58 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
59 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
60 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
61 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
63 *************************************************/
66 * creates a unique ident by adding a number to a tag
68 * @param tag the tag string, must contain a %d if a number
71 static ident *unique_id(const char *tag)
73 static unsigned id = 0;
76 snprintf(str, sizeof(str), tag, ++id);
77 return new_id_from_str(str);
83 * Transforms a SymConst.
85 * @param mod the debug module
86 * @param block the block the new node should belong to
87 * @param node the ir SymConst node
88 * @param mode mode of the SymConst
89 * @return the created ia32 Const node
91 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
93 dbg_info *dbg = env->dbg;
94 ir_mode *mode = env->mode;
95 ir_graph *irg = env->irg;
96 ir_node *block = env->block;
98 if (mode_is_float(mode)) {
100 if (USE_SSE2(env->cg))
101 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
103 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
106 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
108 set_ia32_Const_attr(cnst, env->irn);
114 * Get a primitive type for a mode.
116 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
118 pmap_entry *e = pmap_find(types, mode);
123 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
124 res = new_type_primitive(new_id_from_str(buf), mode);
125 pmap_insert(types, mode, res);
133 * Get an entity that is initialized with a tarval
135 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
137 tarval *tv = get_Const_tarval(cnst);
138 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
143 ir_mode *mode = get_irn_mode(cnst);
144 ir_type *tp = get_Const_type(cnst);
145 if (tp == firm_unknown_type)
146 tp = get_prim_type(cg->isa->types, mode);
148 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
150 set_entity_ld_ident(res, get_entity_ident(res));
151 set_entity_visibility(res, visibility_local);
152 set_entity_variability(res, variability_constant);
153 set_entity_allocation(res, allocation_static);
155 /* we create a new entity here: It's initialization must resist on the
157 rem = current_ir_graph;
158 current_ir_graph = get_const_code_irg();
159 set_atomic_ent_value(res, new_Const_type(tv, tp));
160 current_ir_graph = rem;
162 pmap_insert(cg->isa->tv_ent, tv, res);
170 * Transforms a Const.
172 * @param mod the debug module
173 * @param block the block the new node should belong to
174 * @param node the ir Const node
175 * @param mode mode of the Const
176 * @return the created ia32 Const node
178 static ir_node *gen_Const(ia32_transform_env_t *env) {
181 ir_graph *irg = env->irg;
182 ir_node *block = env->block;
183 ir_node *node = env->irn;
184 dbg_info *dbg = env->dbg;
185 ir_mode *mode = env->mode;
187 if (mode_is_float(mode)) {
189 if (! USE_SSE2(env->cg)) {
190 cnst_classify_t clss = classify_Const(node);
192 if (clss == CNST_NULL)
193 return new_rd_ia32_vfldz(dbg, irg, block, mode);
194 else if (clss == CNST_ONE)
195 return new_rd_ia32_vfld1(dbg, irg, block, mode);
197 sym.entity_p = get_entity_for_tv(env->cg, node);
199 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
201 cnst = gen_SymConst(env);
204 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
205 set_ia32_Const_attr(cnst, node);
213 * Transforms (all) Const's into ia32_Const and places them in the
214 * block where they are used (or in the cfg-pred Block in case of Phi's).
215 * Additionally all reference nodes are changed into mode_Is nodes.
217 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
218 ia32_code_gen_t *cg = env;
219 ia32_transform_env_t tenv;
221 ir_node *pred, *cnst;
228 mode = get_irn_mode(irn);
230 /* transform all reference nodes into mode_Is nodes */
231 if (mode_is_reference(mode)) {
233 set_irn_mode(irn, mode);
236 tenv.block = get_nodes_block(irn);
239 DEBUG_ONLY(tenv.mod = cg->mod;)
241 /* Loop over all predecessors and check for Sym/Const nodes */
242 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
243 pred = get_irn_n(irn, i);
245 opc = get_irn_opcode(pred);
247 tenv.mode = get_irn_mode(pred);
248 tenv.dbg = get_irn_dbg_info(pred);
250 /* If it's a Phi, then we need to create the */
251 /* new Const in it's predecessor block */
253 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
256 /* put the const into the block where the original const was */
257 if (! (cg->opt & IA32_OPT_PLACECNST)) {
258 tenv.block = get_nodes_block(pred);
263 cnst = gen_Const(&tenv);
266 cnst = gen_SymConst(&tenv);
272 /* if we found a const, then set it */
274 set_irn_n(irn, i, cnst);
281 /********************************************************************************************************
282 * _____ _ _ ____ _ _ _ _ _
283 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
284 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
285 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
286 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
287 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
290 ********************************************************************************************************/
293 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
296 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
297 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
301 * Checks for potential CJmp/CJmpAM optimization candidates.
303 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
304 ir_node *cand = NULL;
305 ir_node *prev = sched_prev(irn);
307 if (is_Block(prev)) {
308 if (get_Block_n_cfgpreds(prev) == 1)
309 prev = get_Block_cfgpred(prev, 0);
314 /* The predecessor must be a ProjX. */
315 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
316 prev = get_Proj_pred(prev);
318 if (is_op_func(prev))
325 static int is_TestJmp_cand(const ir_node *irn) {
326 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
330 * Checks if two consecutive arguments of cand matches
331 * the two arguments of irn (TestJmp).
333 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
334 ir_node *in1 = get_irn_n(irn, 0);
335 ir_node *in2 = get_irn_n(irn, 1);
336 int i, n = get_irn_arity(cand);
339 for (i = 0; i < n - 1; i++) {
340 if (get_irn_n(cand, i) == in1 &&
341 get_irn_n(cand, i + 1) == in2)
349 return ia32_cnst_compare(cand, irn);
355 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
357 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
358 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
361 /* we found a possible candidate */
362 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
365 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
367 if (is_ia32_And(cand))
368 set_irn_op(irn, op_ia32_CJmpAM);
370 set_irn_op(irn, op_ia32_CJmp);
372 DB((cg->mod, LEVEL_1, "%+F\n", irn));
376 static int is_CondJmp_cand(const ir_node *irn) {
377 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
381 * Checks if the arguments of cand are the same of irn.
383 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
384 int i, n = get_irn_arity(cand);
387 for (i = 0; i < n; i++) {
388 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
395 return ia32_cnst_compare(cand, irn);
401 * Tries to replace a CondJmp by a CJmpAM
403 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
404 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
407 /* we found a possible candidate */
408 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
411 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
414 set_irn_op(irn, op_ia32_CJmpAM);
416 DB((cg->mod, LEVEL_1, "%+F\n", irn));
421 * Creates a Push from Store(IncSP(gp_reg_size))
423 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
424 ir_node *sp = get_irn_n(irn, 0);
425 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
426 const ir_edge_t *edge;
428 if (get_ia32_am_offs(irn) || !be_is_IncSP(sp))
431 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
432 &ia32_gp_regs[REG_GP_NOREG])
435 val = get_irn_n(irn, 2);
436 if (mode_is_float(get_irn_mode(val)))
439 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
440 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
443 /* ok, translate into Push */
444 edge = get_irn_out_edge_first(irn);
445 old_proj_M = get_edge_src_irn(edge);
447 next = sched_next(irn);
451 bl = get_nodes_block(irn);
452 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
453 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
454 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
455 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
457 /* copy a possible constant from the store */
458 set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
459 set_ia32_immop_type(push, get_ia32_immop_type(irn));
461 /* the push must have SP out register */
462 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
464 exchange(old_proj_M, proj_M);
465 exchange(sp, proj_res);
466 sched_add_before(next, push);
467 sched_add_after(push, proj_res);
471 * Creates a Pop from IncSP(Load(sp))
473 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
474 ir_node *old_proj_M = be_get_IncSP_mem(irn);
475 ir_node *load = skip_Proj(old_proj_M);
476 ir_node *old_proj_res = NULL;
477 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
478 const ir_edge_t *edge;
479 const arch_register_t *reg, *sp;
481 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
484 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
485 &ia32_gp_regs[REG_GP_NOREG])
487 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
490 /* ok, translate into pop */
491 foreach_out_edge(load, edge) {
492 ir_node *succ = get_edge_src_irn(edge);
493 if (succ != old_proj_M) {
498 if (! old_proj_res) {
500 return; /* should not happen */
503 bl = get_nodes_block(load);
505 /* IncSP is typically scheduled after the load, so remove it first */
507 next = sched_next(old_proj_res);
508 sched_remove(old_proj_res);
511 reg = arch_get_irn_register(cg->arch_env, load);
512 sp = arch_get_irn_register(cg->arch_env, irn);
514 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
515 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
516 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
517 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
519 exchange(old_proj_M, proj_M);
520 exchange(old_proj_res, proj_res);
521 exchange(irn, proj_sp);
523 arch_set_irn_register(cg->arch_env, proj_res, reg);
524 arch_set_irn_register(cg->arch_env, proj_sp, sp);
526 sched_add_before(next, proj_sp);
527 sched_add_before(proj_sp, proj_res);
528 sched_add_before(proj_res,pop);
532 * Tries to optimize two following IncSP.
534 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
535 ir_node *prev = be_get_IncSP_pred(irn);
536 int real_uses = get_irn_n_edges(prev);
538 if (be_is_IncSP(prev) && real_uses == 1) {
539 /* first IncSP has only one IncSP user, kill the first one */
540 unsigned prev_offs = be_get_IncSP_offset(prev);
541 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
542 unsigned curr_offs = be_get_IncSP_offset(irn);
543 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
545 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
546 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
550 curr_dir = be_stack_dir_expand;
553 curr_dir = be_stack_dir_shrink;
554 be_set_IncSP_offset(prev, 0);
555 be_set_IncSP_offset(irn, (unsigned)new_ofs);
556 be_set_IncSP_direction(irn, curr_dir);
558 /* Omit the optimized IncSP */
559 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
564 * Performs Peephole Optimizations.
566 void ia32_peephole_optimization(ir_node *irn, void *env) {
567 ia32_code_gen_t *cg = env;
569 if (is_ia32_TestJmp(irn))
570 ia32_optimize_TestJmp(irn, cg);
571 else if (is_ia32_CondJmp(irn))
572 ia32_optimize_CondJmp(irn, cg);
573 /* seems to be buggy when using Pushes */
574 // else if (be_is_IncSP(irn))
575 // ia32_optimize_IncSP(irn, cg);
576 else if (is_ia32_Store(irn))
577 ia32_create_Push(irn, cg);
582 /******************************************************************
584 * /\ | | | | | \/ | | |
585 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
586 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
587 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
588 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
590 ******************************************************************/
597 static int node_is_ia32_comm(const ir_node *irn) {
598 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
601 static int ia32_get_irn_n_edges(const ir_node *irn) {
602 const ir_edge_t *edge;
605 foreach_out_edge(irn, edge) {
613 * Returns the first mode_M Proj connected to irn.
615 static ir_node *get_mem_proj(const ir_node *irn) {
616 const ir_edge_t *edge;
619 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
621 foreach_out_edge(irn, edge) {
622 src = get_edge_src_irn(edge);
624 assert(is_Proj(src) && "Proj expected");
626 if (get_irn_mode(src) == mode_M)
634 * Returns the first Proj with mode != mode_M connected to irn.
636 static ir_node *get_res_proj(const ir_node *irn) {
637 const ir_edge_t *edge;
640 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
642 foreach_out_edge(irn, edge) {
643 src = get_edge_src_irn(edge);
645 assert(is_Proj(src) && "Proj expected");
647 if (get_irn_mode(src) != mode_M)
655 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
657 * @param pred The node to be checked
658 * @param is_op_func The check-function
659 * @return 1 if conditions are fulfilled, 0 otherwise
661 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
662 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
670 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
671 * and if the predecessor is in block bl.
673 * @param bl The block
674 * @param pred The node to be checked
675 * @param is_op_func The check-function
676 * @return 1 if conditions are fulfilled, 0 otherwise
678 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
679 int (*is_op_func)(const ir_node *n))
682 pred = get_Proj_pred(pred);
683 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
692 * Checks if irn is a candidate for address calculation.
694 * - none of the operand must be a Load within the same block OR
695 * - all Loads must have more than one user OR
696 * - the irn has a frame entity (it's a former FrameAddr)
698 * @param block The block the Loads must/mustnot be in
699 * @param irn The irn to check
700 * return 1 if irn is a candidate, 0 otherwise
702 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
703 ir_node *in, *left, *right;
706 left = get_irn_n(irn, 2);
707 right = get_irn_n(irn, 3);
711 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
712 n = ia32_get_irn_n_edges(in);
713 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
718 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
719 n = ia32_get_irn_n_edges(in);
720 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
723 is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
729 * Checks if irn is a candidate for address mode.
732 * - at least one operand has to be a Load within the same block AND
733 * - the load must not have other users than the irn AND
734 * - the irn must not have a frame entity set
736 * @param h The height information of the irg
737 * @param block The block the Loads must/mustnot be in
738 * @param irn The irn to check
739 * return 1 if irn is a candidate, 0 otherwise
741 static int is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
742 ir_node *in, *load, *other, *left, *right;
745 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
748 left = get_irn_n(irn, 2);
749 right = get_irn_n(irn, 3);
753 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
754 n = ia32_get_irn_n_edges(in);
755 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
757 load = get_Proj_pred(in);
760 /* If there is a data dependency of other irn from load: cannot use AM */
761 if (get_nodes_block(other) == block)
762 is_cand = heights_reachable_in_block(h, load, other) ? 0 : is_cand;
767 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
768 n = ia32_get_irn_n_edges(in);
769 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
771 load = get_Proj_pred(in);
774 /* If there is a data dependency of other irn from load: cannot use load */
775 if (get_nodes_block(other) == block)
776 is_cand = heights_reachable_in_block(h, load, other) ? 0 : is_cand;
779 is_cand = get_ia32_frame_ent(irn) ? 0 : is_cand;
785 * Compares the base and index addr and the load/store entities
786 * and returns 1 if they are equal.
788 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
789 const ir_node *addr_b, const ir_node *addr_i)
791 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
792 entity *lent = get_ia32_frame_ent(load);
793 entity *sent = get_ia32_frame_ent(store);
794 ident *lid = get_ia32_am_sc(load);
795 ident *sid = get_ia32_am_sc(store);
796 char *loffs = get_ia32_am_offs(load);
797 char *soffs = get_ia32_am_offs(store);
799 /* are both entities set and equal? */
800 if (is_equal && (lent || sent))
801 is_equal = lent && sent && (lent == sent);
803 /* are address mode idents set and equal? */
804 if (is_equal && (lid || sid))
805 is_equal = lid && sid && (lid == sid);
807 /* are offsets set and equal */
808 if (is_equal && (loffs || soffs))
809 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
811 /* are the load and the store of the same mode? */
812 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
817 typedef enum _ia32_take_lea_attr {
818 IA32_LEA_ATTR_NONE = 0,
819 IA32_LEA_ATTR_BASE = (1 << 0),
820 IA32_LEA_ATTR_INDEX = (1 << 1),
821 IA32_LEA_ATTR_OFFS = (1 << 2),
822 IA32_LEA_ATTR_SCALE = (1 << 3),
823 IA32_LEA_ATTR_AMSC = (1 << 4),
824 IA32_LEA_ATTR_FENT = (1 << 5)
825 } ia32_take_lea_attr;
828 * Decides if we have to keep the LEA operand or if we can assimilate it.
830 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
831 int have_am_sc, ia32_code_gen_t *cg)
833 ir_node *lea_base = get_irn_n(lea, 0);
834 ir_node *lea_idx = get_irn_n(lea, 1);
835 entity *irn_ent = get_ia32_frame_ent(irn);
836 entity *lea_ent = get_ia32_frame_ent(lea);
838 int is_noreg_base = be_is_NoReg(cg, base);
839 int is_noreg_index = be_is_NoReg(cg, index);
840 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
842 /* If the Add and the LEA both have a different frame entity set: keep */
843 if (irn_ent && lea_ent && (irn_ent != lea_ent))
844 return IA32_LEA_ATTR_NONE;
845 else if (! irn_ent && lea_ent)
846 ret_val |= IA32_LEA_ATTR_FENT;
848 /* If the Add and the LEA both have already an address mode symconst: keep */
849 if (have_am_sc && get_ia32_am_sc(lea))
850 return IA32_LEA_ATTR_NONE;
851 else if (get_ia32_am_sc(lea))
852 ret_val |= IA32_LEA_ATTR_AMSC;
854 /* Check the different base-index combinations */
856 if (! is_noreg_base && ! is_noreg_index) {
857 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
858 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
859 if (am_flav & ia32_O)
860 ret_val |= IA32_LEA_ATTR_OFFS;
862 ret_val |= IA32_LEA_ATTR_BASE;
865 return IA32_LEA_ATTR_NONE;
867 else if (! is_noreg_base && is_noreg_index) {
868 /* Base is set but index not */
870 /* Base points to LEA: assimilate everything */
871 if (am_flav & ia32_O)
872 ret_val |= IA32_LEA_ATTR_OFFS;
873 if (am_flav & ia32_S)
874 ret_val |= IA32_LEA_ATTR_SCALE;
875 if (am_flav & ia32_I)
876 ret_val |= IA32_LEA_ATTR_INDEX;
878 ret_val |= IA32_LEA_ATTR_BASE;
880 else if (am_flav & ia32_B ? 0 : 1) {
881 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
882 if (am_flav & ia32_O)
883 ret_val |= IA32_LEA_ATTR_OFFS;
884 if (am_flav & ia32_S)
885 ret_val |= IA32_LEA_ATTR_SCALE;
887 ret_val |= IA32_LEA_ATTR_INDEX;
890 return IA32_LEA_ATTR_NONE;
892 else if (is_noreg_base && ! is_noreg_index) {
893 /* Index is set but not base */
895 /* Index points to LEA: assimilate everything */
896 if (am_flav & ia32_O)
897 ret_val |= IA32_LEA_ATTR_OFFS;
898 if (am_flav & ia32_S)
899 ret_val |= IA32_LEA_ATTR_SCALE;
900 if (am_flav & ia32_B)
901 ret_val |= IA32_LEA_ATTR_BASE;
903 ret_val |= IA32_LEA_ATTR_INDEX;
905 else if (am_flav & ia32_I ? 0 : 1) {
906 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
907 if (am_flav & ia32_O)
908 ret_val |= IA32_LEA_ATTR_OFFS;
909 if (am_flav & ia32_S)
910 ret_val |= IA32_LEA_ATTR_SCALE;
912 ret_val |= IA32_LEA_ATTR_BASE;
915 return IA32_LEA_ATTR_NONE;
918 assert(0 && "There must have been set base or index");
926 * Folds Add or Sub to LEA if possible
928 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
929 ir_graph *irg = get_irn_irg(irn);
930 dbg_info *dbg = get_irn_dbg_info(irn);
931 ir_node *block = get_nodes_block(irn);
933 ir_node *shift = NULL;
934 ir_node *lea_o = NULL;
937 const char *offs_cnst = NULL;
938 char *offs_lea = NULL;
945 entity *lea_ent = NULL;
946 ir_node *left, *right, *temp;
947 ir_node *base, *index;
948 ia32_am_flavour_t am_flav;
949 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
951 if (is_ia32_Add(irn))
954 left = get_irn_n(irn, 2);
955 right = get_irn_n(irn, 3);
957 /* "normalize" arguments in case of add with two operands */
958 if (isadd && ! be_is_NoReg(cg, right)) {
959 /* put LEA == ia32_am_O as right operand */
960 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
961 set_irn_n(irn, 2, right);
962 set_irn_n(irn, 3, left);
968 /* put LEA != ia32_am_O as left operand */
969 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
970 set_irn_n(irn, 2, right);
971 set_irn_n(irn, 3, left);
977 /* put SHL as left operand iff left is NOT a LEA */
978 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
979 set_irn_n(irn, 2, right);
980 set_irn_n(irn, 3, left);
993 /* check for operation with immediate */
994 if (is_ia32_ImmConst(irn)) {
995 DBG((mod, LEVEL_1, "\tfound op with imm const"));
997 offs_cnst = get_ia32_cnst(irn);
1000 else if (is_ia32_ImmSymConst(irn)) {
1001 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
1005 am_sc = get_ia32_id_cnst(irn);
1006 am_sc_sign = is_ia32_am_sc_sign(irn);
1009 /* determine the operand which needs to be checked */
1010 if (be_is_NoReg(cg, right)) {
1017 /* check if right operand is AMConst (LEA with ia32_am_O) */
1018 /* but we can only eat it up if there is no other symconst */
1019 /* because the linker won't accept two symconsts */
1020 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
1021 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
1023 offs_lea = get_ia32_am_offs(temp);
1024 am_sc = get_ia32_am_sc(temp);
1025 am_sc_sign = is_ia32_am_sc_sign(temp);
1032 /* default for add -> make right operand to index */
1036 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
1038 /* determine the operand which needs to be checked */
1040 if (is_ia32_Lea(left)) {
1044 /* check for SHL 1,2,3 */
1045 if (pred_is_specific_node(temp, is_ia32_Shl)) {
1046 temp = get_Proj_pred(temp);
1049 if (get_ia32_Immop_tarval(temp)) {
1050 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
1053 index = get_irn_n(temp, 2);
1055 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
1065 if (! be_is_NoReg(cg, index)) {
1066 /* if we have index, but left == right -> no base */
1067 if (left == right) {
1070 else if (! is_ia32_Lea(left) && (index != right)) {
1071 /* index != right -> we found a good Shl */
1072 /* left != LEA -> this Shl was the left operand */
1073 /* -> base is right operand */
1079 /* Try to assimilate a LEA as left operand */
1080 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1081 /* check if we can assimilate the LEA */
1082 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1084 if (take_attr == IA32_LEA_ATTR_NONE) {
1085 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1088 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1089 lea = left; /* for statistics */
1091 if (take_attr & IA32_LEA_ATTR_OFFS)
1092 offs = get_ia32_am_offs(left);
1094 if (take_attr & IA32_LEA_ATTR_AMSC) {
1095 am_sc = get_ia32_am_sc(left);
1097 am_sc_sign = is_ia32_am_sc_sign(left);
1100 if (take_attr & IA32_LEA_ATTR_SCALE)
1101 scale = get_ia32_am_scale(left);
1103 if (take_attr & IA32_LEA_ATTR_BASE)
1104 base = get_irn_n(left, 0);
1106 if (take_attr & IA32_LEA_ATTR_INDEX)
1107 index = get_irn_n(left, 1);
1109 if (take_attr & IA32_LEA_ATTR_FENT)
1110 lea_ent = get_ia32_frame_ent(left);
1114 /* ok, we can create a new LEA */
1116 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1118 /* add the old offset of a previous LEA */
1120 add_ia32_am_offs(res, offs);
1123 /* add the new offset */
1126 add_ia32_am_offs(res, offs_cnst);
1129 add_ia32_am_offs(res, offs_lea);
1133 /* either lea_O-cnst, -cnst or -lea_O */
1136 add_ia32_am_offs(res, offs_lea);
1139 sub_ia32_am_offs(res, offs_cnst);
1142 sub_ia32_am_offs(res, offs_lea);
1146 /* set the address mode symconst */
1148 set_ia32_am_sc(res, am_sc);
1150 set_ia32_am_sc_sign(res);
1153 /* copy the frame entity (could be set in case of Add */
1154 /* which was a FrameAddr) */
1156 set_ia32_frame_ent(res, lea_ent);
1158 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1160 if (get_ia32_frame_ent(res))
1161 set_ia32_use_frame(res);
1164 set_ia32_am_scale(res, scale);
1166 am_flav = ia32_am_N;
1167 /* determine new am flavour */
1168 if (offs || offs_cnst || offs_lea) {
1171 if (! be_is_NoReg(cg, base)) {
1174 if (! be_is_NoReg(cg, index)) {
1180 set_ia32_am_flavour(res, am_flav);
1182 set_ia32_op_type(res, ia32_AddrModeS);
1184 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1186 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1188 /* we will exchange it, report here before the Proj is created */
1189 if (shift && lea && lea_o)
1190 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1191 else if (shift && lea)
1192 DBG_OPT_LEA3(irn, lea, shift, res);
1193 else if (shift && lea_o)
1194 DBG_OPT_LEA3(irn, lea_o, shift, res);
1195 else if (lea && lea_o)
1196 DBG_OPT_LEA3(irn, lea_o, lea, res);
1198 DBG_OPT_LEA2(irn, shift, res);
1200 DBG_OPT_LEA2(irn, lea, res);
1202 DBG_OPT_LEA2(irn, lea_o, res);
1204 DBG_OPT_LEA1(irn, res);
1206 /* get the result Proj of the Add/Sub */
1207 irn = get_res_proj(irn);
1209 assert(irn && "Couldn't find result proj");
1211 /* exchange the old op with the new LEA */
1220 * Merges a Load/Store node with a LEA.
1221 * @param irn The Load/Store node
1222 * @param lea The LEA
1224 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1225 entity *irn_ent = get_ia32_frame_ent(irn);
1226 entity *lea_ent = get_ia32_frame_ent(lea);
1228 /* If the irn and the LEA both have a different frame entity set: do not merge */
1229 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1231 else if (! irn_ent && lea_ent) {
1232 set_ia32_frame_ent(irn, lea_ent);
1233 set_ia32_use_frame(irn);
1236 /* get the AM attributes from the LEA */
1237 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1238 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1239 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1241 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1242 if (is_ia32_am_sc_sign(lea))
1243 set_ia32_am_sc_sign(irn);
1245 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1247 /* set base and index */
1248 set_irn_n(irn, 0, get_irn_n(lea, 0));
1249 set_irn_n(irn, 1, get_irn_n(lea, 1));
1251 /* clear remat flag */
1252 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1254 if (is_ia32_Ld(irn))
1255 DBG_OPT_LOAD_LEA(lea, irn);
1257 DBG_OPT_STORE_LEA(lea, irn);
1262 * Sets new_right index of irn to right and new_left index to left.
1263 * Also exchange left and right
1265 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1268 set_irn_n(irn, new_right, *right);
1269 set_irn_n(irn, new_left, *left);
1275 /* this is only needed for Compares, but currently ALL nodes
1276 * have this attribute :-) */
1277 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1281 * Performs address calculation optimization (create LEAs if possible)
1283 static void optimize_lea(ir_node *irn, void *env) {
1284 ia32_code_gen_t *cg = env;
1285 ir_node *block, *noreg_gp, *left, *right;
1287 if (! is_ia32_irn(irn))
1290 /* Following cases can occur: */
1291 /* - Sub (l, imm) -> LEA [base - offset] */
1292 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1293 /* - Add (l, imm) -> LEA [base + offset] */
1294 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1295 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1296 /* - Add (l, r) -> LEA [base + index * scale] */
1297 /* with scale > 1 iff l/r == shl (1,2,3) */
1299 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1300 left = get_irn_n(irn, 2);
1301 right = get_irn_n(irn, 3);
1302 block = get_nodes_block(irn);
1303 noreg_gp = ia32_new_NoReg_gp(cg);
1305 /* Do not try to create a LEA if one of the operands is a Load. */
1306 /* check is irn is a candidate for address calculation */
1307 if (is_addr_candidate(block, irn)) {
1310 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1311 res = fold_addr(cg, irn, noreg_gp);
1314 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1316 DB((cg->mod, LEVEL_1, "not transformed\n"));
1319 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1320 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1321 /* - Store -> LEA into Store } it might be better to keep the LEA */
1322 left = get_irn_n(irn, 0);
1324 if (is_ia32_Lea(left)) {
1325 const ir_edge_t *edge, *ne;
1328 /* merge all Loads/Stores connected to this LEA with the LEA */
1329 foreach_out_edge_safe(left, edge, ne) {
1330 src = get_edge_src_irn(edge);
1332 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1333 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1334 merge_loadstore_lea(src, left);
1343 * Checks for address mode patterns and performs the
1344 * necessary transformations.
1345 * This function is called by a walker.
1347 static void optimize_am(ir_node *irn, void *env) {
1348 ia32_am_opt_env_t *am_opt_env = env;
1349 ia32_code_gen_t *cg = am_opt_env->cg;
1350 heights_t *h = am_opt_env->h;
1351 ir_node *block, *noreg_gp, *noreg_fp;
1352 ir_node *left, *right, *temp;
1353 ir_node *store, *load, *mem_proj;
1354 ir_node *succ, *addr_b, *addr_i;
1355 int check_am_src = 0;
1356 int need_exchange_on_fail = 0;
1357 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1359 if (! is_ia32_irn(irn))
1362 block = get_nodes_block(irn);
1363 noreg_gp = ia32_new_NoReg_gp(cg);
1364 noreg_fp = ia32_new_NoReg_fp(cg);
1366 DBG((mod, LEVEL_1, "checking for AM\n"));
1368 /* fold following patterns: */
1369 /* - op -> Load into AMop with am_Source */
1371 /* - op is am_Source capable AND */
1372 /* - the Load is only used by this op AND */
1373 /* - the Load is in the same block */
1374 /* - Store -> op -> Load into AMop with am_Dest */
1376 /* - op is am_Dest capable AND */
1377 /* - the Store uses the same address as the Load AND */
1378 /* - the Load is only used by this op AND */
1379 /* - the Load and Store are in the same block AND */
1380 /* - nobody else uses the result of the op */
1382 if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn) && is_am_candidate(h, block, irn)) {
1383 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1385 left = get_irn_n(irn, 2);
1386 if (get_irn_arity(irn) == 4) {
1387 /* it's an "unary" operation */
1391 right = get_irn_n(irn, 3);
1394 /* normalize commutative ops */
1395 if (node_is_ia32_comm(irn)) {
1396 /* Assure that right operand is always a Load if there is one */
1397 /* because non-commutative ops can only use Dest AM if the right */
1398 /* operand is a load, so we only need to check right operand. */
1399 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1401 exchange_left_right(irn, &left, &right, 3, 2);
1402 need_exchange_on_fail = 1;
1406 /* check for Store -> op -> Load */
1408 /* Store -> op -> Load optimization is only possible if supported by op */
1409 /* and if right operand is a Load */
1410 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1411 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1414 /* An address mode capable op always has a result Proj. */
1415 /* If this Proj is used by more than one other node, we don't need to */
1416 /* check further, otherwise we check for Store and remember the address, */
1417 /* the Store points to. */
1419 succ = get_res_proj(irn);
1420 assert(succ && "Couldn't find result proj");
1426 /* now check for users and Store */
1427 if (ia32_get_irn_n_edges(succ) == 1) {
1428 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1430 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1432 addr_b = get_irn_n(store, 0);
1433 addr_i = get_irn_n(store, 1);
1438 /* we found a Store as single user: Now check for Load */
1440 /* Extra check for commutative ops with two Loads */
1441 /* -> put the interesting Load right */
1442 if (node_is_ia32_comm(irn) &&
1443 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1445 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1446 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1448 /* We exchange left and right, so it's easier to kill */
1449 /* the correct Load later and to handle unary operations. */
1450 set_irn_n(irn, 2, right);
1451 set_irn_n(irn, 3, left);
1457 /* this is only needed for Compares, but currently ALL nodes
1458 * have this attribute :-) */
1459 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1463 /* skip the Proj for easier access */
1464 load = get_Proj_pred(right);
1466 /* Compare Load and Store address */
1467 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1468 /* Right Load is from same address, so we can */
1469 /* disconnect the Load and Store here */
1471 /* set new base, index and attributes */
1472 set_irn_n(irn, 0, addr_b);
1473 set_irn_n(irn, 1, addr_i);
1474 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1475 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1476 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1477 set_ia32_op_type(irn, ia32_AddrModeD);
1478 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1479 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1481 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1482 if (is_ia32_am_sc_sign(load))
1483 set_ia32_am_sc_sign(irn);
1485 if (is_ia32_use_frame(load))
1486 set_ia32_use_frame(irn);
1488 /* connect to Load memory and disconnect Load */
1489 if (get_irn_arity(irn) == 5) {
1491 set_irn_n(irn, 4, get_irn_n(load, 2));
1492 set_irn_n(irn, 3, noreg_gp);
1496 set_irn_n(irn, 3, get_irn_n(load, 2));
1497 set_irn_n(irn, 2, noreg_gp);
1500 /* connect the memory Proj of the Store to the op */
1501 mem_proj = get_mem_proj(store);
1502 set_Proj_pred(mem_proj, irn);
1503 set_Proj_proj(mem_proj, 1);
1505 /* clear remat flag */
1506 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1508 DBG_OPT_AM_D(load, store, irn);
1510 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1513 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1514 /* There was no store, check if we still can optimize for source address mode */
1517 } /* if (support AM Dest) */
1518 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1519 /* op doesn't support am AM Dest -> check for AM Source */
1523 /* was exchanged but optimize failed: exchange back */
1524 if (check_am_src && need_exchange_on_fail)
1525 exchange_left_right(irn, &left, &right, 3, 2);
1527 need_exchange_on_fail = 0;
1529 /* normalize commutative ops */
1530 if (check_am_src && node_is_ia32_comm(irn)) {
1531 /* Assure that left operand is always a Load if there is one */
1532 /* because non-commutative ops can only use Source AM if the */
1533 /* left operand is a Load, so we only need to check the left */
1534 /* operand afterwards. */
1535 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1536 exchange_left_right(irn, &left, &right, 3, 2);
1537 need_exchange_on_fail = 1;
1541 /* optimize op -> Load iff Load is only used by this op */
1542 /* and left operand is a Load which only used by this irn */
1544 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1545 (ia32_get_irn_n_edges(left) == 1))
1547 left = get_Proj_pred(left);
1549 addr_b = get_irn_n(left, 0);
1550 addr_i = get_irn_n(left, 1);
1552 /* set new base, index and attributes */
1553 set_irn_n(irn, 0, addr_b);
1554 set_irn_n(irn, 1, addr_i);
1555 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1556 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1557 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1558 set_ia32_op_type(irn, ia32_AddrModeS);
1559 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1560 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1562 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1563 if (is_ia32_am_sc_sign(left))
1564 set_ia32_am_sc_sign(irn);
1566 /* clear remat flag */
1567 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1569 if (is_ia32_use_frame(left))
1570 set_ia32_use_frame(irn);
1572 /* connect to Load memory */
1573 if (get_irn_arity(irn) == 5) {
1575 set_irn_n(irn, 4, get_irn_n(left, 2));
1577 /* this is only needed for Compares, but currently ALL nodes
1578 * have this attribute :-) */
1579 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1581 /* disconnect from Load */
1582 /* (make second op -> first, set second in to noreg) */
1583 set_irn_n(irn, 2, get_irn_n(irn, 3));
1584 set_irn_n(irn, 3, noreg_gp);
1588 set_irn_n(irn, 3, get_irn_n(left, 2));
1590 /* disconnect from Load */
1591 set_irn_n(irn, 2, noreg_gp);
1594 DBG_OPT_AM_S(left, irn);
1596 /* If Load has a memory Proj, connect it to the op */
1597 mem_proj = get_mem_proj(left);
1599 set_Proj_pred(mem_proj, irn);
1600 set_Proj_proj(mem_proj, 1);
1603 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
1606 /* was exchanged but optimize failed: exchange back */
1607 if (need_exchange_on_fail)
1608 exchange_left_right(irn, &left, &right, 3, 2);
1614 * Performs address mode optimization.
1616 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1617 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1618 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1619 edges_deactivate(cg->irg);
1620 edges_activate(cg->irg);
1623 /* no optimizations at all */
1627 /* beware: we cannot optimize LEA and AM in one run because */
1628 /* LEA optimization adds new nodes to the irg which */
1629 /* invalidates the phase data */
1631 if (cg->opt & IA32_OPT_LEA) {
1632 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1635 if (cg->opt & IA32_OPT_DOAM) {
1636 /* we need height information for am optimization */
1637 heights_t *h = heights_new(cg->irg);
1638 ia32_am_opt_env_t env;
1643 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);