2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
44 #include "../benode_t.h"
45 #include "../besched_t.h"
46 #include "../bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_util.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static ia32_code_gen_t *cg;
62 static void copy_mark(const ir_node *old, ir_node *new)
64 if (is_ia32_is_reload(old))
65 set_ia32_is_reload(new);
66 if (is_ia32_is_spill(old))
67 set_ia32_is_spill(new);
68 if (is_ia32_is_remat(old))
69 set_ia32_is_remat(new);
72 typedef enum produces_flag_t {
79 * Return which usable flag the given node produces
81 * @param node the node to check
82 * @param pn the projection number of the used result
84 static produces_flag_t produces_test_flag(ir_node *node, int pn)
87 const ia32_immediate_attr_t *imm_attr;
89 if (!is_ia32_irn(node))
90 return produces_no_flag;
92 switch (get_ia32_irn_opcode(node)) {
107 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
108 count = get_irn_n(node, n_ia32_ShlD_count);
109 goto check_shift_amount;
114 assert(n_ia32_Shl_count == n_ia32_Shr_count
115 && n_ia32_Shl_count == n_ia32_Sar_count);
116 count = get_irn_n(node, n_ia32_Shl_count);
118 /* when shift count is zero the flags are not affected, so we can only
119 * do this for constants != 0 */
120 if (!is_ia32_Immediate(count))
121 return produces_no_flag;
123 imm_attr = get_ia32_immediate_attr_const(count);
124 if (imm_attr->symconst != NULL)
125 return produces_no_flag;
126 if ((imm_attr->offset & 0x1f) == 0)
127 return produces_no_flag;
131 return pn == pn_ia32_Mul_res_high ?
132 produces_flag_carry : produces_no_flag;
135 return produces_no_flag;
138 return pn == pn_ia32_res ?
139 produces_flag_zero : produces_no_flag;
143 * Replace Cmp(x, 0) by a Test(x, x)
145 static void peephole_ia32_Cmp(ir_node *const node)
148 ia32_immediate_attr_t const *imm;
154 ia32_attr_t const *attr;
158 arch_register_t const *reg;
159 ir_edge_t const *edge;
160 ir_edge_t const *tmp;
162 if (get_ia32_op_type(node) != ia32_Normal)
165 right = get_irn_n(node, n_ia32_Cmp_right);
166 if (!is_ia32_Immediate(right))
169 imm = get_ia32_immediate_attr_const(right);
170 if (imm->symconst != NULL || imm->offset != 0)
173 dbgi = get_irn_dbg_info(node);
174 block = get_nodes_block(node);
175 noreg = ia32_new_NoReg_gp(cg);
176 nomem = get_irg_no_mem(current_ir_graph);
177 op = get_irn_n(node, n_ia32_Cmp_left);
178 attr = get_irn_generic_attr(node);
179 ins_permuted = attr->data.ins_permuted;
180 cmp_unsigned = attr->data.cmp_unsigned;
182 if (is_ia32_Cmp(node)) {
183 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
184 op, op, ins_permuted, cmp_unsigned);
186 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
187 op, op, ins_permuted, cmp_unsigned);
189 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
191 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
192 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
194 foreach_out_edge_safe(node, edge, tmp) {
195 ir_node *const user = get_edge_src_irn(edge);
198 exchange(user, test);
201 sched_add_before(node, test);
202 copy_mark(node, test);
203 be_peephole_exchange(node, test);
207 * Peephole optimization for Test instructions.
208 * - Remove the Test, if an appropriate flag was produced which is still live
209 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
211 static void peephole_ia32_Test(ir_node *node)
213 ir_node *left = get_irn_n(node, n_ia32_Test_left);
214 ir_node *right = get_irn_n(node, n_ia32_Test_right);
216 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
217 && n_ia32_Test_right == n_ia32_Test8Bit_right);
219 if (left == right) { /* we need a test for 0 */
220 ir_node *block = get_nodes_block(node);
221 int pn = pn_ia32_res;
225 const ir_edge_t *edge;
227 if (get_nodes_block(left) != block)
231 pn = get_Proj_proj(left);
232 left = get_Proj_pred(left);
235 /* happens rarely, but if it does code will panic' */
236 if (is_ia32_Unknown_GP(left))
239 /* walk schedule up and abort when we find left or some other node destroys
243 schedpoint = sched_prev(schedpoint);
244 if (schedpoint == left)
246 if (arch_irn_is(schedpoint, modify_flags))
248 if (schedpoint == block)
249 panic("couldn't find left");
252 /* make sure only Lg/Eq tests are used */
253 foreach_out_edge(node, edge) {
254 ir_node *user = get_edge_src_irn(edge);
255 int pnc = get_ia32_condcode(user);
257 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
262 switch (produces_test_flag(left, pn)) {
263 case produces_flag_zero:
266 case produces_flag_carry:
267 foreach_out_edge(node, edge) {
268 ir_node *user = get_edge_src_irn(edge);
269 int pnc = get_ia32_condcode(user);
272 case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
273 case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
274 default: panic("unexpected pn");
276 set_ia32_condcode(user, pnc);
284 if (get_irn_mode(left) != mode_T) {
285 set_irn_mode(left, mode_T);
287 /* If there are other users, reroute them to result proj */
288 if (get_irn_n_edges(left) != 2) {
289 ir_node *res = new_r_Proj(current_ir_graph, block, left,
290 mode_Iu, pn_ia32_res);
292 edges_reroute(left, res, current_ir_graph);
293 /* Reattach the result proj to left */
294 set_Proj_pred(res, left);
298 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
299 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
301 arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
303 assert(get_irn_mode(node) != mode_T);
305 be_peephole_exchange(node, flags_proj);
306 } else if (is_ia32_Immediate(right)) {
307 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
310 /* A test with a symconst is rather strange, but better safe than sorry */
311 if (imm->symconst != NULL)
314 offset = imm->offset;
315 if (get_ia32_op_type(node) == ia32_AddrModeS) {
316 ia32_attr_t *const attr = get_irn_generic_attr(node);
318 if ((offset & 0xFFFFFF00) == 0) {
319 /* attr->am_offs += 0; */
320 } else if ((offset & 0xFFFF00FF) == 0) {
321 ir_node *imm = create_Immediate(NULL, 0, offset >> 8);
322 set_irn_n(node, n_ia32_Test_right, imm);
324 } else if ((offset & 0xFF00FFFF) == 0) {
325 ir_node *imm = create_Immediate(NULL, 0, offset >> 16);
326 set_irn_n(node, n_ia32_Test_right, imm);
328 } else if ((offset & 0x00FFFFFF) == 0) {
329 ir_node *imm = create_Immediate(NULL, 0, offset >> 24);
330 set_irn_n(node, n_ia32_Test_right, imm);
335 } else if (offset < 256) {
336 arch_register_t const* const reg = arch_get_irn_register(left);
338 if (reg != &ia32_gp_regs[REG_EAX] &&
339 reg != &ia32_gp_regs[REG_EBX] &&
340 reg != &ia32_gp_regs[REG_ECX] &&
341 reg != &ia32_gp_regs[REG_EDX]) {
348 /* Technically we should build a Test8Bit because of the register
349 * constraints, but nobody changes registers at this point anymore. */
350 set_ia32_ls_mode(node, mode_Bu);
355 * AMD Athlon works faster when RET is not destination of
356 * conditional jump or directly preceded by other jump instruction.
357 * Can be avoided by placing a Rep prefix before the return.
359 static void peephole_ia32_Return(ir_node *node) {
360 ir_node *block, *irn;
362 if (!ia32_cg_config.use_pad_return)
365 block = get_nodes_block(node);
367 /* check if this return is the first on the block */
368 sched_foreach_reverse_from(node, irn) {
369 switch (get_irn_opcode(irn)) {
371 /* the return node itself, ignore */
376 /* ignore no code generated */
379 /* arg, IncSP 0 nodes might occur, ignore these */
380 if (be_get_IncSP_offset(irn) == 0)
390 /* ensure, that the 3 byte return is generated */
391 be_Return_set_emit_pop(node, 1);
394 /* only optimize up to 48 stores behind IncSPs */
395 #define MAXPUSH_OPTIMIZE 48
398 * Tries to create Push's from IncSP, Store combinations.
399 * The Stores are replaced by Push's, the IncSP is modified
400 * (possibly into IncSP 0, but not removed).
402 static void peephole_IncSP_Store_to_push(ir_node *irn)
408 ir_node *stores[MAXPUSH_OPTIMIZE];
413 ir_node *first_push = NULL;
414 ir_edge_t const *edge;
415 ir_edge_t const *next;
417 memset(stores, 0, sizeof(stores));
419 assert(be_is_IncSP(irn));
421 inc_ofs = be_get_IncSP_offset(irn);
426 * We first walk the schedule after the IncSP node as long as we find
427 * suitable Stores that could be transformed to a Push.
428 * We save them into the stores array which is sorted by the frame offset/4
429 * attached to the node
432 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
437 /* it has to be a Store */
438 if (!is_ia32_Store(node))
441 /* it has to use our sp value */
442 if (get_irn_n(node, n_ia32_base) != irn)
444 /* Store has to be attached to NoMem */
445 mem = get_irn_n(node, n_ia32_mem);
449 /* unfortunately we can't support the full AMs possible for push at the
450 * moment. TODO: fix this */
451 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
454 offset = get_ia32_am_offs_int(node);
455 /* we should NEVER access uninitialized stack BELOW the current SP */
458 /* storing at half-slots is bad */
459 if ((offset & 3) != 0)
462 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
464 storeslot = offset >> 2;
466 /* storing into the same slot twice is bad (and shouldn't happen...) */
467 if (stores[storeslot] != NULL)
470 stores[storeslot] = node;
471 if (storeslot > maxslot)
477 for (i = -1; i < maxslot; ++i) {
478 if (stores[i + 1] == NULL)
482 /* walk through the Stores and create Pushs for them */
483 block = get_nodes_block(irn);
484 spmode = get_irn_mode(irn);
486 for (; i >= 0; --i) {
487 const arch_register_t *spreg;
489 ir_node *val, *mem, *mem_proj;
490 ir_node *store = stores[i];
491 ir_node *noreg = ia32_new_NoReg_gp(cg);
493 val = get_irn_n(store, n_ia32_unary_op);
494 mem = get_irn_n(store, n_ia32_mem);
495 spreg = arch_get_irn_register(curr_sp);
497 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
498 copy_mark(store, push);
500 if (first_push == NULL)
503 sched_add_after(curr_sp, push);
505 /* create stackpointer Proj */
506 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
507 arch_set_irn_register(curr_sp, spreg);
509 /* create memory Proj */
510 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
512 /* use the memproj now */
513 be_peephole_exchange(store, mem_proj);
518 foreach_out_edge_safe(irn, edge, next) {
519 ir_node *const src = get_edge_src_irn(edge);
520 int const pos = get_edge_src_pos(edge);
522 if (src == first_push)
525 set_irn_n(src, pos, curr_sp);
528 be_set_IncSP_offset(irn, inc_ofs);
532 static void peephole_store_incsp(ir_node *store)
543 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
544 if (!be_is_IncSP(am_base)
545 || get_nodes_block(am_base) != get_nodes_block(store))
547 mem = get_irn_n(store, n_ia32_Store_mem);
548 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
552 int incsp_offset = be_get_IncSP_offset(am_base);
553 if (incsp_offset <= 0)
556 /* we have to be at offset 0 */
557 int my_offset = get_ia32_am_offs_int(store);
558 if (my_offset != 0) {
559 /* TODO here: find out wether there is a store with offset 0 before
560 * us and wether we can move it down to our place */
563 ir_mode *ls_mode = get_ia32_ls_mode(store);
564 int my_store_size = get_mode_size_bytes(ls_mode);
566 if (my_offset + my_store_size > incsp_offset)
569 /* correctness checking:
570 - noone else must write to that stackslot
571 (because after translation incsp won't allocate it anymore)
573 sched_foreach_reverse_from(store, node) {
579 /* make sure noone else can use the space on the stack */
580 arity = get_irn_arity(node);
581 for (i = 0; i < arity; ++i) {
582 ir_node *pred = get_irn_n(node, i);
586 if (i == n_ia32_base &&
587 (get_ia32_op_type(node) == ia32_AddrModeS
588 || get_ia32_op_type(node) == ia32_AddrModeD)) {
589 int node_offset = get_ia32_am_offs_int(node);
590 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
591 int node_size = get_mode_size_bytes(node_ls_mode);
592 /* overlapping with our position? abort */
593 if (node_offset < my_offset + my_store_size
594 && node_offset + node_size >= my_offset)
596 /* otherwise it's fine */
600 /* strange use of esp: abort */
605 /* all ok, change to push */
606 dbgi = get_irn_dbg_info(store);
607 block = get_nodes_block(store);
608 noreg = ia32_new_NoReg_gp(cg);
609 val = get_irn_n(store, n_ia32_Store_val);
611 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
613 create_push(dbgi, current_ir_graph, block, am_base, store);
618 * Return true if a mode can be stored in the GP register set
620 static inline int mode_needs_gp_reg(ir_mode *mode) {
621 if (mode == mode_fpcw)
623 if (get_mode_size_bits(mode) > 32)
625 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
629 * Tries to create Pops from Load, IncSP combinations.
630 * The Loads are replaced by Pops, the IncSP is modified
631 * (possibly into IncSP 0, but not removed).
633 static void peephole_Load_IncSP_to_pop(ir_node *irn)
635 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
636 int i, maxslot, inc_ofs, ofs;
637 ir_node *node, *pred_sp, *block;
638 ir_node *loads[MAXPUSH_OPTIMIZE];
640 unsigned regmask = 0;
641 unsigned copymask = ~0;
643 memset(loads, 0, sizeof(loads));
644 assert(be_is_IncSP(irn));
646 inc_ofs = -be_get_IncSP_offset(irn);
651 * We first walk the schedule before the IncSP node as long as we find
652 * suitable Loads that could be transformed to a Pop.
653 * We save them into the stores array which is sorted by the frame offset/4
654 * attached to the node
657 pred_sp = be_get_IncSP_pred(irn);
658 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
661 const arch_register_t *sreg, *dreg;
663 /* it has to be a Load */
664 if (!is_ia32_Load(node)) {
665 if (be_is_Copy(node)) {
666 if (!mode_needs_gp_reg(get_irn_mode(node))) {
667 /* not a GP copy, ignore */
670 dreg = arch_get_irn_register(node);
671 sreg = arch_get_irn_register(be_get_Copy_op(node));
672 if (regmask & copymask & (1 << sreg->index)) {
675 if (regmask & copymask & (1 << dreg->index)) {
678 /* we CAN skip Copies if neither the destination nor the source
679 * is not in our regmask, ie none of our future Pop will overwrite it */
680 regmask |= (1 << dreg->index) | (1 << sreg->index);
681 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
687 /* we can handle only GP loads */
688 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
691 /* it has to use our predecessor sp value */
692 if (get_irn_n(node, n_ia32_base) != pred_sp) {
693 /* it would be ok if this load does not use a Pop result,
694 * but we do not check this */
698 /* should have NO index */
699 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
702 offset = get_ia32_am_offs_int(node);
703 /* we should NEVER access uninitialized stack BELOW the current SP */
706 /* storing at half-slots is bad */
707 if ((offset & 3) != 0)
710 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
712 /* ignore those outside the possible windows */
713 if (offset > inc_ofs - 4)
715 loadslot = offset >> 2;
717 /* loading from the same slot twice is bad (and shouldn't happen...) */
718 if (loads[loadslot] != NULL)
721 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
722 if (regmask & (1 << dreg->index)) {
723 /* this register is already used */
726 regmask |= 1 << dreg->index;
728 loads[loadslot] = node;
729 if (loadslot > maxslot)
736 /* find the first slot */
737 for (i = maxslot; i >= 0; --i) {
738 ir_node *load = loads[i];
744 ofs = inc_ofs - (maxslot + 1) * 4;
747 /* create a new IncSP if needed */
748 block = get_nodes_block(irn);
751 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
752 sched_add_before(irn, pred_sp);
755 /* walk through the Loads and create Pops for them */
756 for (++i; i <= maxslot; ++i) {
757 ir_node *load = loads[i];
759 const ir_edge_t *edge, *tmp;
760 const arch_register_t *reg;
762 mem = get_irn_n(load, n_ia32_mem);
763 reg = arch_irn_get_register(load, pn_ia32_Load_res);
765 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
766 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
768 copy_mark(load, pop);
770 /* create stackpointer Proj */
771 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
772 arch_set_irn_register(pred_sp, esp);
774 sched_add_before(irn, pop);
777 foreach_out_edge_safe(load, edge, tmp) {
778 ir_node *proj = get_edge_src_irn(edge);
780 set_Proj_pred(proj, pop);
783 /* we can remove the Load now */
788 be_set_IncSP_offset(irn, -ofs);
789 be_set_IncSP_pred(irn, pred_sp);
794 * Find a free GP register if possible, else return NULL.
796 static const arch_register_t *get_free_gp_reg(void)
800 for(i = 0; i < N_ia32_gp_REGS; ++i) {
801 const arch_register_t *reg = &ia32_gp_regs[i];
802 if(arch_register_type_is(reg, ignore))
805 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
806 return &ia32_gp_regs[i];
813 * Creates a Pop instruction before the given schedule point.
815 * @param dbgi debug info
816 * @param irg the graph
817 * @param block the block
818 * @param stack the previous stack value
819 * @param schedpoint the new node is added before this node
820 * @param reg the register to pop
822 * @return the new stack value
824 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
825 ir_node *stack, ir_node *schedpoint,
826 const arch_register_t *reg)
828 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
834 pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
836 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
837 arch_set_irn_register(stack, esp);
838 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
839 arch_set_irn_register(val, reg);
841 sched_add_before(schedpoint, pop);
844 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
845 sched_add_before(schedpoint, keep);
851 * Creates a Push instruction before the given schedule point.
853 * @param dbgi debug info
854 * @param irg the graph
855 * @param block the block
856 * @param stack the previous stack value
857 * @param schedpoint the new node is added before this node
858 * @param reg the register to pop
860 * @return the new stack value
862 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
863 ir_node *stack, ir_node *schedpoint)
865 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
867 ir_node *val = ia32_new_Unknown_gp(cg);
868 ir_node *noreg = ia32_new_NoReg_gp(cg);
869 ir_node *nomem = get_irg_no_mem(irg);
870 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
871 sched_add_before(schedpoint, push);
873 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
874 arch_set_irn_register(stack, esp);
880 * Optimize an IncSp by replacing it with Push/Pop.
882 static void peephole_be_IncSP(ir_node *node)
884 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
885 const arch_register_t *reg;
886 ir_graph *irg = current_ir_graph;
892 /* first optimize incsp->incsp combinations */
893 node = be_peephole_IncSP_IncSP(node);
895 /* transform IncSP->Store combinations to Push where possible */
896 peephole_IncSP_Store_to_push(node);
898 /* transform Load->IncSP combinations to Pop where possible */
899 peephole_Load_IncSP_to_pop(node);
901 if (arch_get_irn_register(node) != esp)
904 /* replace IncSP -4 by Pop freereg when possible */
905 offset = be_get_IncSP_offset(node);
906 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
907 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
908 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
909 (offset != +8 || ia32_cg_config.use_sub_esp_8))
913 /* we need a free register for pop */
914 reg = get_free_gp_reg();
918 dbgi = get_irn_dbg_info(node);
919 block = get_nodes_block(node);
920 stack = be_get_IncSP_pred(node);
922 stack = create_pop(dbgi, irg, block, stack, node, reg);
925 stack = create_pop(dbgi, irg, block, stack, node, reg);
928 dbgi = get_irn_dbg_info(node);
929 block = get_nodes_block(node);
930 stack = be_get_IncSP_pred(node);
931 stack = create_push(dbgi, irg, block, stack, node);
934 stack = create_push(dbgi, irg, block, stack, node);
938 be_peephole_exchange(node, stack);
942 * Peephole optimisation for ia32_Const's
944 static void peephole_ia32_Const(ir_node *node)
946 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
947 const arch_register_t *reg;
952 /* try to transform a mov 0, reg to xor reg reg */
953 if (attr->offset != 0 || attr->symconst != NULL)
955 if (ia32_cg_config.use_mov_0)
957 /* xor destroys the flags, so no-one must be using them */
958 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
961 reg = arch_get_irn_register(node);
962 assert(be_peephole_get_reg_value(reg) == NULL);
964 /* create xor(produceval, produceval) */
965 block = get_nodes_block(node);
966 dbgi = get_irn_dbg_info(node);
967 xor = new_bd_ia32_Xor0(dbgi, block);
968 arch_set_irn_register(xor, reg);
970 sched_add_before(node, xor);
972 copy_mark(node, xor);
973 be_peephole_exchange(node, xor);
976 static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
978 return node == cg->noreg_gp;
981 static ir_node *create_immediate_from_int(int val)
983 ir_graph *irg = current_ir_graph;
984 ir_node *start_block = get_irg_start_block(irg);
985 ir_node *immediate = new_bd_ia32_Immediate(NULL, start_block, NULL, 0,
987 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
992 static ir_node *create_immediate_from_am(const ir_node *node)
994 ir_node *block = get_nodes_block(node);
995 int offset = get_ia32_am_offs_int(node);
996 int sc_sign = is_ia32_am_sc_sign(node);
997 ir_entity *entity = get_ia32_am_sc(node);
1000 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, offset);
1001 arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
1005 static int is_am_one(const ir_node *node)
1007 int offset = get_ia32_am_offs_int(node);
1008 ir_entity *entity = get_ia32_am_sc(node);
1010 return offset == 1 && entity == NULL;
1013 static int is_am_minus_one(const ir_node *node)
1015 int offset = get_ia32_am_offs_int(node);
1016 ir_entity *entity = get_ia32_am_sc(node);
1018 return offset == -1 && entity == NULL;
1022 * Transforms a LEA into an Add or SHL if possible.
1024 static void peephole_ia32_Lea(ir_node *node)
1028 const arch_register_t *base_reg;
1029 const arch_register_t *index_reg;
1030 const arch_register_t *out_reg;
1041 assert(is_ia32_Lea(node));
1043 /* we can only do this if it is allowed to clobber the flags */
1044 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1047 base = get_irn_n(node, n_ia32_Lea_base);
1048 index = get_irn_n(node, n_ia32_Lea_index);
1050 if(is_noreg(cg, base)) {
1054 base_reg = arch_get_irn_register(base);
1056 if(is_noreg(cg, index)) {
1060 index_reg = arch_get_irn_register(index);
1063 if(base == NULL && index == NULL) {
1064 /* we shouldn't construct these in the first place... */
1065 #ifdef DEBUG_libfirm
1066 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1071 out_reg = arch_get_irn_register(node);
1072 scale = get_ia32_am_scale(node);
1073 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1074 /* check if we have immediates values (frame entities should already be
1075 * expressed in the offsets) */
1076 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1082 /* we can transform leas where the out register is the same as either the
1083 * base or index register back to an Add or Shl */
1084 if(out_reg == base_reg) {
1086 #ifdef DEBUG_libfirm
1087 if(!has_immediates) {
1088 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1093 goto make_add_immediate;
1095 if(scale == 0 && !has_immediates) {
1100 /* can't create an add */
1102 } else if(out_reg == index_reg) {
1104 if(has_immediates && scale == 0) {
1106 goto make_add_immediate;
1107 } else if(!has_immediates && scale > 0) {
1109 op2 = create_immediate_from_int(scale);
1111 } else if(!has_immediates) {
1112 #ifdef DEBUG_libfirm
1113 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1117 } else if(scale == 0 && !has_immediates) {
1122 /* can't create an add */
1125 /* can't create an add */
1130 if(ia32_cg_config.use_incdec) {
1131 if(is_am_one(node)) {
1132 dbgi = get_irn_dbg_info(node);
1133 block = get_nodes_block(node);
1134 res = new_bd_ia32_Inc(dbgi, block, op1);
1135 arch_set_irn_register(res, out_reg);
1138 if(is_am_minus_one(node)) {
1139 dbgi = get_irn_dbg_info(node);
1140 block = get_nodes_block(node);
1141 res = new_bd_ia32_Dec(dbgi, block, op1);
1142 arch_set_irn_register(res, out_reg);
1146 op2 = create_immediate_from_am(node);
1149 dbgi = get_irn_dbg_info(node);
1150 block = get_nodes_block(node);
1151 noreg = ia32_new_NoReg_gp(cg);
1152 nomem = new_NoMem();
1153 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1154 arch_set_irn_register(res, out_reg);
1155 set_ia32_commutative(res);
1159 dbgi = get_irn_dbg_info(node);
1160 block = get_nodes_block(node);
1161 noreg = ia32_new_NoReg_gp(cg);
1162 nomem = new_NoMem();
1163 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1164 arch_set_irn_register(res, out_reg);
1168 SET_IA32_ORIG_NODE(res, node);
1170 /* add new ADD/SHL to schedule */
1171 DBG_OPT_LEA2ADD(node, res);
1173 /* exchange the Add and the LEA */
1174 sched_add_before(node, res);
1175 copy_mark(node, res);
1176 be_peephole_exchange(node, res);
1180 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1182 static void peephole_ia32_Imul_split(ir_node *imul)
1184 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1185 const arch_register_t *reg;
1188 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1189 /* no memory, imm form ignore */
1192 /* we need a free register */
1193 reg = get_free_gp_reg();
1197 /* fine, we can rebuild it */
1198 res = turn_back_am(imul);
1199 arch_set_irn_register(res, reg);
1203 * Replace xorps r,r and xorpd r,r by pxor r,r
1205 static void peephole_ia32_xZero(ir_node *xor)
1207 set_irn_op(xor, op_ia32_xPzero);
1211 * Replace 16bit sign extension from ax to eax by shorter cwtl
1213 static void peephole_ia32_Conv_I2I(ir_node *node)
1215 const arch_register_t *eax = &ia32_gp_regs[REG_EAX];
1216 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1217 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1222 if (get_mode_size_bits(smaller_mode) != 16 ||
1223 !mode_is_signed(smaller_mode) ||
1224 eax != arch_get_irn_register(val) ||
1225 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1228 dbgi = get_irn_dbg_info(node);
1229 block = get_nodes_block(node);
1230 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1231 arch_set_irn_register(cwtl, eax);
1232 sched_add_before(node, cwtl);
1233 be_peephole_exchange(node, cwtl);
1237 * Register a peephole optimisation function.
1239 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1241 assert(op->ops.generic == NULL);
1242 op->ops.generic = (op_func)func;
1245 /* Perform peephole-optimizations. */
1246 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1250 /* register peephole optimisations */
1251 clear_irp_opcodes_generic_func();
1252 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1253 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1254 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1255 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1256 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1257 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1258 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1259 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1260 if (! ia32_cg_config.use_imul_mem_imm32)
1261 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1262 if (ia32_cg_config.use_pxor)
1263 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1264 if (ia32_cg_config.use_short_sex_eax)
1265 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1267 be_peephole_opt(cg->birg);
1271 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1272 * all it's Projs are removed as well.
1273 * @param irn The irn to be removed from schedule
1275 static inline void try_kill(ir_node *node)
1277 if(get_irn_mode(node) == mode_T) {
1278 const ir_edge_t *edge, *next;
1279 foreach_out_edge_safe(node, edge, next) {
1280 ir_node *proj = get_edge_src_irn(edge);
1285 if(get_irn_n_edges(node) != 0)
1288 if (sched_is_scheduled(node)) {
1295 static void optimize_conv_store(ir_node *node)
1300 ir_mode *store_mode;
1302 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1305 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1306 pred_proj = get_irn_n(node, n_ia32_Store_val);
1307 if(is_Proj(pred_proj)) {
1308 pred = get_Proj_pred(pred_proj);
1312 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1314 if(get_ia32_op_type(pred) != ia32_Normal)
1317 /* the store only stores the lower bits, so we only need the conv
1318 * it it shrinks the mode */
1319 conv_mode = get_ia32_ls_mode(pred);
1320 store_mode = get_ia32_ls_mode(node);
1321 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1324 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1325 if(get_irn_n_edges(pred_proj) == 0) {
1326 kill_node(pred_proj);
1327 if(pred != pred_proj)
1332 static void optimize_load_conv(ir_node *node)
1334 ir_node *pred, *predpred;
1338 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1341 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1342 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1346 predpred = get_Proj_pred(pred);
1347 if(!is_ia32_Load(predpred))
1350 /* the load is sign extending the upper bits, so we only need the conv
1351 * if it shrinks the mode */
1352 load_mode = get_ia32_ls_mode(predpred);
1353 conv_mode = get_ia32_ls_mode(node);
1354 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1357 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1358 /* change the load if it has only 1 user */
1359 if(get_irn_n_edges(pred) == 1) {
1361 if(get_mode_sign(conv_mode)) {
1362 newmode = find_signed_mode(load_mode);
1364 newmode = find_unsigned_mode(load_mode);
1366 assert(newmode != NULL);
1367 set_ia32_ls_mode(predpred, newmode);
1369 /* otherwise we have to keep the conv */
1375 exchange(node, pred);
1378 static void optimize_conv_conv(ir_node *node)
1380 ir_node *pred_proj, *pred, *result_conv;
1381 ir_mode *pred_mode, *conv_mode;
1385 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1388 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1389 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1390 if(is_Proj(pred_proj))
1391 pred = get_Proj_pred(pred_proj);
1395 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1398 /* we know that after a conv, the upper bits are sign extended
1399 * so we only need the 2nd conv if it shrinks the mode */
1400 conv_mode = get_ia32_ls_mode(node);
1401 conv_mode_bits = get_mode_size_bits(conv_mode);
1402 pred_mode = get_ia32_ls_mode(pred);
1403 pred_mode_bits = get_mode_size_bits(pred_mode);
1405 if(conv_mode_bits == pred_mode_bits
1406 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1407 result_conv = pred_proj;
1408 } else if(conv_mode_bits <= pred_mode_bits) {
1409 /* if 2nd conv is smaller then first conv, then we can always take the
1411 if(get_irn_n_edges(pred_proj) == 1) {
1412 result_conv = pred_proj;
1413 set_ia32_ls_mode(pred, conv_mode);
1415 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1416 if (get_mode_size_bits(conv_mode) == 8) {
1417 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1418 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1421 /* we don't want to end up with 2 loads, so we better do nothing */
1422 if(get_irn_mode(pred) == mode_T) {
1426 result_conv = exact_copy(pred);
1427 set_ia32_ls_mode(result_conv, conv_mode);
1429 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1430 if (get_mode_size_bits(conv_mode) == 8) {
1431 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1432 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1436 /* if both convs have the same sign, then we can take the smaller one */
1437 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1438 result_conv = pred_proj;
1440 /* no optimisation possible if smaller conv is sign-extend */
1441 if(mode_is_signed(pred_mode)) {
1444 /* we can take the smaller conv if it is unsigned */
1445 result_conv = pred_proj;
1449 /* Some user (like Phis) won't be happy if we change the mode. */
1450 set_irn_mode(result_conv, get_irn_mode(node));
1453 exchange(node, result_conv);
1455 if(get_irn_n_edges(pred_proj) == 0) {
1456 kill_node(pred_proj);
1457 if(pred != pred_proj)
1460 optimize_conv_conv(result_conv);
1463 static void optimize_node(ir_node *node, void *env)
1467 optimize_load_conv(node);
1468 optimize_conv_store(node);
1469 optimize_conv_conv(node);
1473 * Performs conv and address mode optimization.
1475 void ia32_optimize_graph(ia32_code_gen_t *cg)
1477 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1480 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1483 void ia32_init_optimize(void)
1485 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");