8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
23 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
25 typedef int is_op_func_t(const ir_node *n);
28 * checks if a node represents the NOREG value
30 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
31 be_abi_irg_t *babi = cg->birg->abi;
32 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
33 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
35 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
36 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
41 /*************************************************
44 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
45 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
46 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
47 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
49 *************************************************/
52 * creates a unique ident by adding a number to a tag
54 * @param tag the tag string, must contain a %d if a number
57 static ident *unique_id(const char *tag)
59 static unsigned id = 0;
62 snprintf(str, sizeof(str), tag, ++id);
63 return new_id_from_str(str);
69 * Transforms a SymConst.
71 * @param mod the debug module
72 * @param block the block the new node should belong to
73 * @param node the ir SymConst node
74 * @param mode mode of the SymConst
75 * @return the created ia32 Const node
77 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
79 dbg_info *dbg = env->dbg;
80 ir_mode *mode = env->mode;
81 ir_graph *irg = env->irg;
82 ir_node *block = env->block;
84 if (mode_is_float(mode)) {
85 if (USE_SSE2(env->cg))
86 cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
88 cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
91 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
93 set_ia32_Const_attr(cnst, env->irn);
98 * Get a primitive type for a mode.
100 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
102 pmap_entry *e = pmap_find(types, mode);
107 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
108 res = new_type_primitive(new_id_from_str(buf), mode);
109 pmap_insert(types, mode, res);
117 * Get an entity that is initialized with a tarval
119 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
121 tarval *tv = get_Const_tarval(cnst);
122 pmap_entry *e = pmap_find(cg->tv_ent, tv);
127 ir_mode *mode = get_irn_mode(cnst);
128 ir_type *tp = get_Const_type(cnst);
129 if (tp == firm_unknown_type)
130 tp = get_prim_type(cg->types, mode);
132 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
134 set_entity_ld_ident(res, get_entity_ident(res));
135 set_entity_visibility(res, visibility_local);
136 set_entity_variability(res, variability_constant);
137 set_entity_allocation(res, allocation_static);
139 /* we create a new entity here: It's initialization must resist on the
141 rem = current_ir_graph;
142 current_ir_graph = get_const_code_irg();
143 set_atomic_ent_value(res, new_Const_type(tv, tp));
144 current_ir_graph = rem;
152 * Transforms a Const.
154 * @param mod the debug module
155 * @param block the block the new node should belong to
156 * @param node the ir Const node
157 * @param mode mode of the Const
158 * @return the created ia32 Const node
160 static ir_node *gen_Const(ia32_transform_env_t *env) {
163 ir_graph *irg = env->irg;
164 ir_node *block = env->block;
165 ir_node *node = env->irn;
166 dbg_info *dbg = env->dbg;
167 ir_mode *mode = env->mode;
169 if (mode_is_float(mode)) {
170 if (! USE_SSE2(env->cg)) {
171 cnst_classify_t clss = classify_Const(node);
173 if (clss == CNST_NULL)
174 return new_rd_ia32_vfldz(dbg, irg, block, mode);
175 else if (clss == CNST_ONE)
176 return new_rd_ia32_vfld1(dbg, irg, block, mode);
178 sym.entity_p = get_entity_for_tv(env->cg, node);
180 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
182 cnst = gen_SymConst(env);
185 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
186 set_ia32_Const_attr(cnst, node);
194 * Transforms (all) Const's into ia32_Const and places them in the
195 * block where they are used (or in the cfg-pred Block in case of Phi's).
196 * Additionally all reference nodes are changed into mode_Is nodes.
198 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
199 ia32_code_gen_t *cg = env;
200 ia32_transform_env_t tenv;
202 ir_node *pred, *cnst;
209 mode = get_irn_mode(irn);
211 /* transform all reference nodes into mode_Is nodes */
212 if (mode_is_reference(mode)) {
214 set_irn_mode(irn, mode);
217 tenv.block = get_nodes_block(irn);
222 /* Loop over all predecessors and check for Sym/Const nodes */
223 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
224 pred = get_irn_n(irn, i);
226 opc = get_irn_opcode(pred);
228 tenv.mode = get_irn_mode(pred);
229 tenv.dbg = get_irn_dbg_info(pred);
231 /* If it's a Phi, then we need to create the */
232 /* new Const in it's predecessor block */
234 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
237 /* put the const into the block where the original const was */
238 if (! cg->opt.placecnst) {
239 tenv.block = get_nodes_block(pred);
244 cnst = gen_Const(&tenv);
247 cnst = gen_SymConst(&tenv);
253 /* if we found a const, then set it */
255 set_irn_n(irn, i, cnst);
262 /********************************************************************************************************
263 * _____ _ _ ____ _ _ _ _ _
264 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
265 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
266 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
267 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
268 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
271 ********************************************************************************************************/
274 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
277 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
278 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
282 * Checks for potential CJmp/CJmpAM optimization candidates.
284 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
285 ir_node *cand = NULL;
286 ir_node *prev = sched_prev(irn);
288 if (is_Block(prev)) {
289 if (get_Block_n_cfgpreds(prev) == 1)
290 prev = get_Block_cfgpred(prev, 0);
295 /* The predecessor must be a ProjX. */
296 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
297 prev = get_Proj_pred(prev);
299 if (is_op_func(prev))
306 static int is_TestJmp_cand(const ir_node *irn) {
307 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
311 * Checks if two consecutive arguments of cand matches
312 * the two arguments of irn (TestJmp).
314 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
315 ir_node *in1 = get_irn_n(irn, 0);
316 ir_node *in2 = get_irn_n(irn, 1);
317 int i, n = get_irn_arity(cand);
320 for (i = 0; i < n - 1; i++) {
321 if (get_irn_n(cand, i) == in1 &&
322 get_irn_n(cand, i + 1) == in2)
330 return ia32_cnst_compare(cand, irn);
336 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
338 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
339 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
342 /* we found a possible candidate */
343 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
346 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
348 if (is_ia32_And(cand))
349 set_irn_op(irn, op_ia32_CJmpAM);
351 set_irn_op(irn, op_ia32_CJmp);
353 DB((cg->mod, LEVEL_1, "%+F\n", irn));
357 static int is_CondJmp_cand(const ir_node *irn) {
358 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
362 * Checks if the arguments of cand are the same of irn.
364 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
365 int i, n = get_irn_arity(cand);
368 for (i = 0; i < n; i++) {
369 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
376 return ia32_cnst_compare(cand, irn);
382 * Tries to replace a CondJmp by a CJmpAM
384 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
385 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
388 /* we found a possible candidate */
389 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
392 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
394 set_irn_op(irn, op_ia32_CJmp);
396 DB((cg->mod, LEVEL_1, "%+F\n", irn));
401 * Performs Peephole Optimizations
403 void ia32_peephole_optimization(ir_node *irn, void *env) {
404 if (is_ia32_TestJmp(irn)) {
405 ia32_optimize_TestJmp(irn, env);
407 else if (is_ia32_CondJmp(irn)) {
408 ia32_optimize_CondJmp(irn, env);
414 /******************************************************************
416 * /\ | | | | | \/ | | |
417 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
418 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
419 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
420 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
422 ******************************************************************/
424 static int node_is_ia32_comm(const ir_node *irn) {
425 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
428 static int ia32_get_irn_n_edges(const ir_node *irn) {
429 const ir_edge_t *edge;
432 foreach_out_edge(irn, edge) {
440 * Returns the first mode_M Proj connected to irn.
442 static ir_node *get_mem_proj(const ir_node *irn) {
443 const ir_edge_t *edge;
446 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
448 foreach_out_edge(irn, edge) {
449 src = get_edge_src_irn(edge);
451 assert(is_Proj(src) && "Proj expected");
453 if (get_irn_mode(src) == mode_M)
461 * Returns the first Proj with mode != mode_M connected to irn.
463 static ir_node *get_res_proj(const ir_node *irn) {
464 const ir_edge_t *edge;
467 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
469 foreach_out_edge(irn, edge) {
470 src = get_edge_src_irn(edge);
472 assert(is_Proj(src) && "Proj expected");
474 if (get_irn_mode(src) != mode_M)
482 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
484 * @param pred The node to be checked
485 * @param is_op_func The check-function
486 * @return 1 if conditions are fulfilled, 0 otherwise
488 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
489 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
497 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
498 * and if the predecessor is in block bl.
500 * @param bl The block
501 * @param pred The node to be checked
502 * @param is_op_func The check-function
503 * @return 1 if conditions are fulfilled, 0 otherwise
505 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
506 int (*is_op_func)(const ir_node *n))
509 pred = get_Proj_pred(pred);
510 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
521 * Checks if irn is a candidate for address calculation or address mode.
523 * address calculation (AC):
524 * - none of the operand must be a Load within the same block OR
525 * - all Loads must have more than one user OR
526 * - the irn has a frame entity (it's a former FrameAddr)
529 * - at least one operand has to be a Load within the same block AND
530 * - the load must not have other users than the irn AND
531 * - the irn must not have a frame entity set
533 * @param block The block the Loads must/not be in
534 * @param irn The irn to check
535 * @param check_addr 1 if to check for address calculation, 0 otherwise
536 * return 1 if irn is a candidate for AC or AM, 0 otherwise
538 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
540 int n, is_cand = check_addr;
542 in = get_irn_n(irn, 2);
544 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
545 n = ia32_get_irn_n_edges(in);
546 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
549 in = get_irn_n(irn, 3);
551 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
552 n = ia32_get_irn_n_edges(in);
553 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
556 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
562 * Compares the base and index addr and the load/store entities
563 * and returns 1 if they are equal.
565 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
566 const ir_node *addr_b, const ir_node *addr_i)
568 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
569 entity *lent = get_ia32_frame_ent(load);
570 entity *sent = get_ia32_frame_ent(store);
571 ident *lid = get_ia32_am_sc(load);
572 ident *sid = get_ia32_am_sc(store);
573 char *loffs = get_ia32_am_offs(load);
574 char *soffs = get_ia32_am_offs(store);
576 /* are both entities set and equal? */
577 if (is_equal && (lent || sent))
578 is_equal = lent && sent && (lent == sent);
580 /* are address mode idents set and equal? */
581 if (is_equal && (lid || sid))
582 is_equal = lid && sid && (lid == sid);
584 /* are offsets set and equal */
585 if (is_equal && (loffs || soffs))
586 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
588 /* are the load and the store of the same mode? */
589 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
597 * Folds Add or Sub to LEA if possible
599 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
600 ir_graph *irg = get_irn_irg(irn);
601 dbg_info *dbg = get_irn_dbg_info(irn);
602 ir_node *block = get_nodes_block(irn);
605 const char *offs_cnst = NULL;
606 char *offs_lea = NULL;
613 ir_node *left, *right, *temp;
614 ir_node *base, *index;
615 ia32_am_flavour_t am_flav;
617 if (is_ia32_Add(irn))
620 left = get_irn_n(irn, 2);
621 right = get_irn_n(irn, 3);
623 /* "normalize" arguments in case of add with two operands */
624 if (isadd && ! be_is_NoReg(cg, right)) {
625 /* put LEA == ia32_am_O as right operand */
626 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
627 set_irn_n(irn, 2, right);
628 set_irn_n(irn, 3, left);
634 /* put LEA != ia32_am_O as left operand */
635 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
636 set_irn_n(irn, 2, right);
637 set_irn_n(irn, 3, left);
643 /* put SHL as left operand iff left is NOT a LEA */
644 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
645 set_irn_n(irn, 2, right);
646 set_irn_n(irn, 3, left);
659 /* check for operation with immediate */
660 if (is_ia32_ImmConst(irn)) {
661 DBG((mod, LEVEL_1, "\tfound op with imm const"));
663 offs_cnst = get_ia32_cnst(irn);
666 else if (is_ia32_ImmSymConst(irn)) {
667 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
671 am_sc = get_ia32_id_cnst(irn);
672 am_sc_sign = is_ia32_am_sc_sign(irn);
675 /* determine the operand which needs to be checked */
676 if (be_is_NoReg(cg, right)) {
683 /* check if right operand is AMConst (LEA with ia32_am_O) */
684 /* but we can only eat it up if there is no other symconst */
685 /* because the linker won't accept two symconsts */
686 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
687 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
689 offs_lea = get_ia32_am_offs(temp);
690 am_sc = get_ia32_am_sc(temp);
691 am_sc_sign = is_ia32_am_sc_sign(temp);
697 /* default for add -> make right operand to index */
701 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
703 /* determine the operand which needs to be checked */
705 if (is_ia32_Lea(left)) {
709 /* check for SHL 1,2,3 */
710 if (pred_is_specific_node(temp, is_ia32_Shl)) {
711 temp = get_Proj_pred(temp);
713 if (get_ia32_Immop_tarval(temp)) {
714 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
717 index = get_irn_n(temp, 2);
719 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
725 if (! be_is_NoReg(cg, index)) {
726 /* if we have index, but left == right -> no base */
730 else if (! is_ia32_Lea(left) && (index != right)) {
731 /* index != right -> we found a good Shl */
732 /* left != LEA -> this Shl was the left operand */
733 /* -> base is right operand */
739 /* Try to assimilate a LEA as left operand */
740 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
741 am_flav = get_ia32_am_flavour(left);
743 /* If we have an Add with a real right operand (not NoReg) and */
744 /* the LEA contains already an index calculation then we create */
746 /* If the LEA contains already a frame_entity then we also */
747 /* create a new one otherwise we would loose it. */
748 if ((isadd && !be_is_NoReg(cg, index) && (am_flav & ia32_am_I)) || /* no new LEA if index already set */
749 get_ia32_frame_ent(left) || /* no new LEA if stack access */
750 (have_am_sc && get_ia32_am_sc(left))) /* no new LEA if AM symconst already present */
752 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
755 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
756 offs = get_ia32_am_offs(left);
757 am_sc = have_am_sc ? am_sc : get_ia32_am_sc(left);
758 have_am_sc = am_sc ? 1 : 0;
759 am_sc_sign = is_ia32_am_sc_sign(left);
760 base = get_irn_n(left, 0);
761 index = get_irn_n(left, 1);
762 scale = get_ia32_am_scale(left);
766 /* ok, we can create a new LEA */
768 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
770 /* add the old offset of a previous LEA */
772 add_ia32_am_offs(res, offs);
775 /* add the new offset */
778 add_ia32_am_offs(res, offs_cnst);
781 add_ia32_am_offs(res, offs_lea);
785 /* either lea_O-cnst, -cnst or -lea_O */
788 add_ia32_am_offs(res, offs_lea);
791 sub_ia32_am_offs(res, offs_cnst);
794 sub_ia32_am_offs(res, offs_lea);
798 /* set the address mode symconst */
800 set_ia32_am_sc(res, am_sc);
802 set_ia32_am_sc_sign(res);
805 /* copy the frame entity (could be set in case of Add */
806 /* which was a FrameAddr) */
807 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
809 if (is_ia32_use_frame(irn))
810 set_ia32_use_frame(res);
813 set_ia32_am_scale(res, scale);
816 /* determine new am flavour */
817 if (offs || offs_cnst || offs_lea) {
820 if (! be_is_NoReg(cg, base)) {
823 if (! be_is_NoReg(cg, index)) {
829 set_ia32_am_flavour(res, am_flav);
831 set_ia32_op_type(res, ia32_AddrModeS);
833 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
835 /* get the result Proj of the Add/Sub */
836 irn = get_res_proj(irn);
838 assert(irn && "Couldn't find result proj");
840 /* exchange the old op with the new LEA */
848 * Optimizes a pattern around irn to address mode if possible.
850 void ia32_optimize_am(ir_node *irn, void *env) {
851 ia32_code_gen_t *cg = env;
852 firm_dbg_module_t *mod = cg->mod;
856 ir_node *block, *noreg_gp, *noreg_fp;
857 ir_node *left, *right, *temp;
858 ir_node *store, *load, *mem_proj;
859 ir_node *succ, *addr_b, *addr_i;
860 int check_am_src = 0;
862 if (! is_ia32_irn(irn))
865 dbg = get_irn_dbg_info(irn);
866 mode = get_irn_mode(irn);
867 block = get_nodes_block(irn);
868 noreg_gp = ia32_new_NoReg_gp(cg);
869 noreg_fp = ia32_new_NoReg_fp(cg);
871 DBG((mod, LEVEL_1, "checking for AM\n"));
873 /* 1st part: check for address calculations and transform the into Lea */
875 /* Following cases can occur: */
876 /* - Sub (l, imm) -> LEA [base - offset] */
877 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
878 /* - Add (l, imm) -> LEA [base + offset] */
879 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
880 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
881 /* - Add (l, r) -> LEA [base + index * scale] */
882 /* with scale > 1 iff l/r == shl (1,2,3) */
884 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
885 left = get_irn_n(irn, 2);
886 right = get_irn_n(irn, 3);
888 /* Do not try to create a LEA if one of the operands is a Load. */
889 /* check is irn is a candidate for address calculation */
890 if (is_candidate(block, irn, 1)) {
891 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
892 res = fold_addr(cg, irn, mod, noreg_gp);
895 DB((mod, LEVEL_1, "transformed into %+F\n", res));
897 DB((mod, LEVEL_1, "not transformed\n"));
901 /* 2nd part: fold following patterns: */
902 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
903 /* - Store -> LEA into Store } it might be better to keep the LEA */
904 /* - op -> Load into AMop with am_Source */
906 /* - op is am_Source capable AND */
907 /* - the Load is only used by this op AND */
908 /* - the Load is in the same block */
909 /* - Store -> op -> Load into AMop with am_Dest */
911 /* - op is am_Dest capable AND */
912 /* - the Store uses the same address as the Load AND */
913 /* - the Load is only used by this op AND */
914 /* - the Load and Store are in the same block AND */
915 /* - nobody else uses the result of the op */
917 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
918 /* 1st: check for Load/Store -> LEA */
919 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
920 left = get_irn_n(irn, 0);
922 if (is_ia32_Lea(left)) {
923 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
925 /* get the AM attributes from the LEA */
926 add_ia32_am_offs(irn, get_ia32_am_offs(left));
927 set_ia32_am_scale(irn, get_ia32_am_scale(left));
928 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
930 set_ia32_am_sc(irn, get_ia32_am_sc(left));
931 if (is_ia32_am_sc_sign(left))
932 set_ia32_am_sc_sign(irn);
934 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
936 /* set base and index */
937 set_irn_n(irn, 0, get_irn_n(left, 0));
938 set_irn_n(irn, 1, get_irn_n(left, 1));
940 /* clear remat flag */
941 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
944 /* check if the node is an address mode candidate */
945 else if (is_candidate(block, irn, 0)) {
946 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
948 left = get_irn_n(irn, 2);
949 if (get_irn_arity(irn) == 4) {
950 /* it's an "unary" operation */
954 right = get_irn_n(irn, 3);
957 /* normalize commutative ops */
958 if (node_is_ia32_comm(irn)) {
959 /* Assure that right operand is always a Load if there is one */
960 /* because non-commutative ops can only use Dest AM if the right */
961 /* operand is a load, so we only need to check right operand. */
962 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
964 set_irn_n(irn, 2, right);
965 set_irn_n(irn, 3, left);
973 /* check for Store -> op -> Load */
975 /* Store -> op -> Load optimization is only possible if supported by op */
976 /* and if right operand is a Load */
977 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
978 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
981 /* An address mode capable op always has a result Proj. */
982 /* If this Proj is used by more than one other node, we don't need to */
983 /* check further, otherwise we check for Store and remember the address, */
984 /* the Store points to. */
986 succ = get_res_proj(irn);
987 assert(succ && "Couldn't find result proj");
993 /* now check for users and Store */
994 if (ia32_get_irn_n_edges(succ) == 1) {
995 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
997 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
999 addr_b = get_irn_n(store, 0);
1001 /* Could be that the Store is connected to the address */
1002 /* calculating LEA while the Load is already transformed. */
1003 if (is_ia32_Lea(addr_b)) {
1005 addr_b = get_irn_n(succ, 0);
1006 addr_i = get_irn_n(succ, 1);
1015 /* we found a Store as single user: Now check for Load */
1017 /* Extra check for commutative ops with two Loads */
1018 /* -> put the interesting Load right */
1019 if (node_is_ia32_comm(irn) &&
1020 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1022 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1023 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1025 /* We exchange left and right, so it's easier to kill */
1026 /* the correct Load later and to handle unary operations. */
1027 set_irn_n(irn, 2, right);
1028 set_irn_n(irn, 3, left);
1036 /* skip the Proj for easier access */
1037 load = get_Proj_pred(right);
1039 /* Compare Load and Store address */
1040 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1041 /* Right Load is from same address, so we can */
1042 /* disconnect the Load and Store here */
1044 /* set new base, index and attributes */
1045 set_irn_n(irn, 0, addr_b);
1046 set_irn_n(irn, 1, addr_i);
1047 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1048 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1049 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1050 set_ia32_op_type(irn, ia32_AddrModeD);
1051 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1052 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1054 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1055 if (is_ia32_am_sc_sign(load))
1056 set_ia32_am_sc_sign(irn);
1058 if (is_ia32_use_frame(load))
1059 set_ia32_use_frame(irn);
1061 /* connect to Load memory and disconnect Load */
1062 if (get_irn_arity(irn) == 5) {
1064 set_irn_n(irn, 4, get_irn_n(load, 2));
1065 set_irn_n(irn, 3, noreg_gp);
1069 set_irn_n(irn, 3, get_irn_n(load, 2));
1070 set_irn_n(irn, 2, noreg_gp);
1073 /* connect the memory Proj of the Store to the op */
1074 mem_proj = get_mem_proj(store);
1075 set_Proj_pred(mem_proj, irn);
1076 set_Proj_proj(mem_proj, 1);
1078 /* clear remat flag */
1079 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1081 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1084 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1085 /* There was no store, check if we still can optimize for source address mode */
1088 } /* if (support AM Dest) */
1089 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1090 /* op doesn't support am AM Dest -> check for AM Source */
1094 /* normalize commutative ops */
1095 if (node_is_ia32_comm(irn)) {
1096 /* Assure that left operand is always a Load if there is one */
1097 /* because non-commutative ops can only use Source AM if the */
1098 /* left operand is a Load, so we only need to check the left */
1099 /* operand afterwards. */
1100 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1101 set_irn_n(irn, 2, right);
1102 set_irn_n(irn, 3, left);
1110 /* optimize op -> Load iff Load is only used by this op */
1111 /* and left operand is a Load which only used by this irn */
1113 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1114 (ia32_get_irn_n_edges(left) == 1))
1116 left = get_Proj_pred(left);
1118 addr_b = get_irn_n(left, 0);
1119 addr_i = get_irn_n(left, 1);
1121 /* set new base, index and attributes */
1122 set_irn_n(irn, 0, addr_b);
1123 set_irn_n(irn, 1, addr_i);
1124 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1125 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1126 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1127 set_ia32_op_type(irn, ia32_AddrModeS);
1128 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1129 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1131 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1132 if (is_ia32_am_sc_sign(left))
1133 set_ia32_am_sc_sign(irn);
1135 /* clear remat flag */
1136 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1138 if (is_ia32_use_frame(left))
1139 set_ia32_use_frame(irn);
1141 /* connect to Load memory */
1142 if (get_irn_arity(irn) == 5) {
1144 set_irn_n(irn, 4, get_irn_n(left, 2));
1148 set_irn_n(irn, 3, get_irn_n(left, 2));
1151 /* disconnect from Load */
1152 set_irn_n(irn, 2, noreg_gp);
1154 /* If Load has a memory Proj, connect it to the op */
1155 mem_proj = get_mem_proj(left);
1157 set_Proj_pred(mem_proj, irn);
1158 set_Proj_proj(mem_proj, 1);
1161 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));