2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* happens rarely, but if it does code will panic' */
258 if (is_ia32_Unknown_GP(left))
261 /* walk schedule up and abort when we find left or some other node destroys
263 schedpoint = sched_prev(node);
264 while(schedpoint != left) {
265 schedpoint = sched_prev(schedpoint);
266 if(arch_irn_is(arch_env, schedpoint, modify_flags))
268 if(schedpoint == block)
269 panic("couldn't find left");
272 /* make sure only Lg/Eq tests are used */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 int pnc = get_ia32_condcode(user);
277 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
282 if(!produces_zero_flag(left, pn))
285 left = turn_into_mode_t(left);
287 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
288 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
290 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
292 assert(get_irn_mode(node) != mode_T);
294 be_peephole_before_exchange(node, flags_proj);
295 exchange(node, flags_proj);
297 be_peephole_after_exchange(flags_proj);
300 // only optimize up to 48 stores behind IncSPs
301 #define MAXPUSH_OPTIMIZE 48
304 * Tries to create pushs from IncSP,Store combinations.
305 * The Stores are replaced by Push's, the IncSP is modified
306 * (possibly into IncSP 0, but not removed).
308 static void peephole_IncSP_Store_to_push(ir_node *irn)
313 ir_node *stores[MAXPUSH_OPTIMIZE];
314 ir_node *block = get_nodes_block(irn);
315 ir_graph *irg = cg->irg;
317 ir_mode *spmode = get_irn_mode(irn);
319 memset(stores, 0, sizeof(stores));
321 assert(be_is_IncSP(irn));
323 offset = be_get_IncSP_offset(irn);
328 * We first walk the schedule after the IncSP node as long as we find
329 * suitable stores that could be transformed to a push.
330 * We save them into the stores array which is sorted by the frame offset/4
331 * attached to the node
333 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
338 // it has to be a store
339 if(!is_ia32_Store(node))
342 // it has to use our sp value
343 if(get_irn_n(node, n_ia32_base) != irn)
345 // store has to be attached to NoMem
346 mem = get_irn_n(node, n_ia32_mem);
351 /* unfortunately we can't support the full AMs possible for push at the
352 * moment. TODO: fix this */
353 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
356 offset = get_ia32_am_offs_int(node);
358 storeslot = offset / 4;
359 if(storeslot >= MAXPUSH_OPTIMIZE)
362 // storing into the same slot twice is bad (and shouldn't happen...)
363 if(stores[storeslot] != NULL)
366 // storing at half-slots is bad
370 stores[storeslot] = node;
373 curr_sp = be_get_IncSP_pred(irn);
375 // walk the stores in inverse order and create pushs for them
376 i = (offset / 4) - 1;
377 if(i >= MAXPUSH_OPTIMIZE) {
378 i = MAXPUSH_OPTIMIZE - 1;
381 for( ; i >= 0; --i) {
382 const arch_register_t *spreg;
384 ir_node *val, *mem, *mem_proj;
385 ir_node *store = stores[i];
386 ir_node *noreg = ia32_new_NoReg_gp(cg);
388 if(store == NULL || is_Bad(store))
391 val = get_irn_n(store, n_ia32_unary_op);
392 mem = get_irn_n(store, n_ia32_mem);
393 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
395 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val);
397 sched_add_before(irn, push);
399 // create stackpointer proj
400 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
401 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
403 // create memory proj
404 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
406 // use the memproj now
407 exchange(store, mem_proj);
409 // we can remove the store now
415 be_set_IncSP_offset(irn, offset);
416 be_set_IncSP_pred(irn, curr_sp);
420 * Tries to optimize two following IncSP.
422 static void peephole_IncSP_IncSP(ir_node *node)
427 ir_node *pred = be_get_IncSP_pred(node);
430 if(!be_is_IncSP(pred))
433 if(get_irn_n_edges(pred) > 1)
436 pred_offs = be_get_IncSP_offset(pred);
437 curr_offs = be_get_IncSP_offset(node);
439 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
440 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
444 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
445 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
449 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
450 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
453 offs = curr_offs + pred_offs;
456 /* add pred offset to ours and remove pred IncSP */
457 be_set_IncSP_offset(node, offs);
459 predpred = be_get_IncSP_pred(pred);
460 be_peephole_before_exchange(pred, predpred);
462 /* rewire dependency edges */
463 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
464 be_set_IncSP_pred(node, predpred);
468 be_peephole_after_exchange(predpred);
472 * Find a free GP register if possible, else return NULL.
474 static const arch_register_t *get_free_gp_reg(void)
478 for(i = 0; i < N_ia32_gp_REGS; ++i) {
479 const arch_register_t *reg = &ia32_gp_regs[i];
480 if(arch_register_type_is(reg, ignore))
483 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
484 return &ia32_gp_regs[i];
490 static void peephole_be_IncSP(ir_node *node)
492 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
493 const arch_register_t *reg;
504 /* first optimize incsp->incsp combinations */
505 peephole_IncSP_IncSP(node);
507 /* transform IncSP->Store combinations to Push where possible */
508 peephole_IncSP_Store_to_push(node);
510 if (arch_get_irn_register(arch_env, node) != esp)
513 /* replace IncSP -4 by Pop freereg when possible */
514 offset = be_get_IncSP_offset(node);
515 if (!(offset == -4 && !ia32_cg_config.use_add_esp_4) &&
516 !(offset == -8 && !ia32_cg_config.use_add_esp_8) &&
517 !(offset == +4 && !ia32_cg_config.use_sub_esp_4) &&
518 !(offset == +8 && !ia32_cg_config.use_sub_esp_8))
522 /* we need a free register for pop */
523 reg = get_free_gp_reg();
527 irg = current_ir_graph;
528 dbgi = get_irn_dbg_info(node);
529 block = get_nodes_block(node);
530 noreg = ia32_new_NoReg_gp(cg);
531 stack = be_get_IncSP_pred(node);
532 pop = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack);
534 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
535 arch_set_irn_register(arch_env, stack, esp);
536 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
537 arch_set_irn_register(arch_env, val, reg);
539 sched_add_before(node, pop);
541 keep = sched_next(node);
542 if (!be_is_Keep(keep)) {
545 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
546 sched_add_before(node, keep);
548 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
552 pop2 = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack);
554 stack = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_stack);
555 arch_set_irn_register(arch_env, stack, esp);
556 val = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_res);
557 arch_set_irn_register(arch_env, val, reg);
559 sched_add_after(pop, pop2);
560 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
567 be_peephole_before_exchange(node, stack);
569 exchange(node, stack);
570 be_peephole_after_exchange(stack);
574 * Peephole optimisation for ia32_Const's
576 static void peephole_ia32_Const(ir_node *node)
578 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
579 const arch_register_t *reg;
580 ir_graph *irg = current_ir_graph;
587 /* try to transform a mov 0, reg to xor reg reg */
588 if(attr->offset != 0 || attr->symconst != NULL)
590 /* xor destroys the flags, so no-one must be using them */
591 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
594 reg = arch_get_irn_register(arch_env, node);
595 assert(be_peephole_get_reg_value(reg) == NULL);
597 /* create xor(produceval, produceval) */
598 block = get_nodes_block(node);
599 dbgi = get_irn_dbg_info(node);
600 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
601 arch_set_irn_register(arch_env, produceval, reg);
603 noreg = ia32_new_NoReg_gp(cg);
604 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
605 produceval, produceval);
606 arch_set_irn_register(arch_env, xor, reg);
608 sched_add_before(node, produceval);
609 sched_add_before(node, xor);
611 be_peephole_before_exchange(node, xor);
614 be_peephole_after_exchange(xor);
617 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
619 return node == cg->noreg_gp;
622 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
624 ir_graph *irg = current_ir_graph;
625 ir_node *start_block = get_irg_start_block(irg);
626 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
628 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
633 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
636 ir_graph *irg = get_irn_irg(node);
637 ir_node *block = get_nodes_block(node);
638 int offset = get_ia32_am_offs_int(node);
639 int sc_sign = is_ia32_am_sc_sign(node);
640 ir_entity *entity = get_ia32_am_sc(node);
643 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
644 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
648 static int is_am_one(const ir_node *node)
650 int offset = get_ia32_am_offs_int(node);
651 ir_entity *entity = get_ia32_am_sc(node);
653 return offset == 1 && entity == NULL;
656 static int is_am_minus_one(const ir_node *node)
658 int offset = get_ia32_am_offs_int(node);
659 ir_entity *entity = get_ia32_am_sc(node);
661 return offset == -1 && entity == NULL;
665 * Transforms a LEA into an Add or SHL if possible.
667 static void peephole_ia32_Lea(ir_node *node)
669 const arch_env_t *arch_env = cg->arch_env;
670 ir_graph *irg = current_ir_graph;
673 const arch_register_t *base_reg;
674 const arch_register_t *index_reg;
675 const arch_register_t *out_reg;
686 assert(is_ia32_Lea(node));
688 /* we can only do this if are allowed to globber the flags */
689 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
692 base = get_irn_n(node, n_ia32_Lea_base);
693 index = get_irn_n(node, n_ia32_Lea_index);
695 if(is_noreg(cg, base)) {
699 base_reg = arch_get_irn_register(arch_env, base);
701 if(is_noreg(cg, index)) {
705 index_reg = arch_get_irn_register(arch_env, index);
708 if(base == NULL && index == NULL) {
709 /* we shouldn't construct these in the first place... */
711 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
716 out_reg = arch_get_irn_register(arch_env, node);
717 scale = get_ia32_am_scale(node);
718 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
719 /* check if we have immediates values (frame entities should already be
720 * expressed in the offsets) */
721 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
727 /* we can transform leas where the out register is the same as either the
728 * base or index register back to an Add or Shl */
729 if(out_reg == base_reg) {
732 if(!has_immediates) {
733 ir_fprintf(stderr, "Optimisation warning: found lea which is "
738 goto make_add_immediate;
740 if(scale == 0 && !has_immediates) {
745 /* can't create an add */
747 } else if(out_reg == index_reg) {
749 if(has_immediates && scale == 0) {
751 goto make_add_immediate;
752 } else if(!has_immediates && scale > 0) {
754 op2 = create_immediate_from_int(cg, scale);
756 } else if(!has_immediates) {
758 ir_fprintf(stderr, "Optimisation warning: found lea which is "
762 } else if(scale == 0 && !has_immediates) {
767 /* can't create an add */
770 /* can't create an add */
775 if(ia32_cg_config.use_incdec) {
776 if(is_am_one(node)) {
777 dbgi = get_irn_dbg_info(node);
778 block = get_nodes_block(node);
779 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
780 arch_set_irn_register(arch_env, res, out_reg);
783 if(is_am_minus_one(node)) {
784 dbgi = get_irn_dbg_info(node);
785 block = get_nodes_block(node);
786 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
787 arch_set_irn_register(arch_env, res, out_reg);
791 op2 = create_immediate_from_am(cg, node);
794 dbgi = get_irn_dbg_info(node);
795 block = get_nodes_block(node);
796 noreg = ia32_new_NoReg_gp(cg);
798 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
799 arch_set_irn_register(arch_env, res, out_reg);
800 set_ia32_commutative(res);
804 dbgi = get_irn_dbg_info(node);
805 block = get_nodes_block(node);
806 noreg = ia32_new_NoReg_gp(cg);
808 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
809 arch_set_irn_register(arch_env, res, out_reg);
813 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
815 /* add new ADD/SHL to schedule */
816 DBG_OPT_LEA2ADD(node, res);
818 /* exchange the Add and the LEA */
819 be_peephole_before_exchange(node, res);
820 sched_add_before(node, res);
823 be_peephole_after_exchange(res);
827 * Register a peephole optimisation function.
829 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
830 assert(op->ops.generic == NULL);
831 op->ops.generic = (void*) func;
834 /* Perform peephole-optimizations. */
835 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
838 arch_env = cg->arch_env;
840 /* register peephole optimisations */
841 clear_irp_opcodes_generic_func();
842 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
843 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
844 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
845 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
846 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
847 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
849 be_peephole_opt(cg->birg);
853 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
854 * all it's Projs are removed as well.
855 * @param irn The irn to be removed from schedule
857 static INLINE void try_kill(ir_node *node)
859 if(get_irn_mode(node) == mode_T) {
860 const ir_edge_t *edge, *next;
861 foreach_out_edge_safe(node, edge, next) {
862 ir_node *proj = get_edge_src_irn(edge);
867 if(get_irn_n_edges(node) != 0)
870 if (sched_is_scheduled(node)) {
877 static void optimize_conv_store(ir_node *node)
884 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
887 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
888 pred_proj = get_irn_n(node, n_ia32_Store_val);
889 if(is_Proj(pred_proj)) {
890 pred = get_Proj_pred(pred_proj);
894 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
896 if(get_ia32_op_type(pred) != ia32_Normal)
899 /* the store only stores the lower bits, so we only need the conv
900 * it it shrinks the mode */
901 conv_mode = get_ia32_ls_mode(pred);
902 store_mode = get_ia32_ls_mode(node);
903 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
906 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
907 if(get_irn_n_edges(pred_proj) == 0) {
908 be_kill_node(pred_proj);
909 if(pred != pred_proj)
914 static void optimize_load_conv(ir_node *node)
916 ir_node *pred, *predpred;
920 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
923 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
924 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
928 predpred = get_Proj_pred(pred);
929 if(!is_ia32_Load(predpred))
932 /* the load is sign extending the upper bits, so we only need the conv
933 * if it shrinks the mode */
934 load_mode = get_ia32_ls_mode(predpred);
935 conv_mode = get_ia32_ls_mode(node);
936 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
939 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
940 /* change the load if it has only 1 user */
941 if(get_irn_n_edges(pred) == 1) {
943 if(get_mode_sign(conv_mode)) {
944 newmode = find_signed_mode(load_mode);
946 newmode = find_unsigned_mode(load_mode);
948 assert(newmode != NULL);
949 set_ia32_ls_mode(predpred, newmode);
951 /* otherwise we have to keep the conv */
957 exchange(node, pred);
960 static void optimize_conv_conv(ir_node *node)
962 ir_node *pred_proj, *pred, *result_conv;
963 ir_mode *pred_mode, *conv_mode;
967 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
970 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
971 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
972 if(is_Proj(pred_proj))
973 pred = get_Proj_pred(pred_proj);
977 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
980 /* we know that after a conv, the upper bits are sign extended
981 * so we only need the 2nd conv if it shrinks the mode */
982 conv_mode = get_ia32_ls_mode(node);
983 conv_mode_bits = get_mode_size_bits(conv_mode);
984 pred_mode = get_ia32_ls_mode(pred);
985 pred_mode_bits = get_mode_size_bits(pred_mode);
987 if(conv_mode_bits == pred_mode_bits
988 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
989 result_conv = pred_proj;
990 } else if(conv_mode_bits <= pred_mode_bits) {
991 /* if 2nd conv is smaller then first conv, then we can always take the
993 if(get_irn_n_edges(pred_proj) == 1) {
994 result_conv = pred_proj;
995 set_ia32_ls_mode(pred, conv_mode);
997 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
998 if (get_mode_size_bits(conv_mode) == 8) {
999 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1000 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1003 /* we don't want to end up with 2 loads, so we better do nothing */
1004 if(get_irn_mode(pred) == mode_T) {
1008 result_conv = exact_copy(pred);
1009 set_ia32_ls_mode(result_conv, conv_mode);
1011 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1012 if (get_mode_size_bits(conv_mode) == 8) {
1013 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1014 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1018 /* if both convs have the same sign, then we can take the smaller one */
1019 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1020 result_conv = pred_proj;
1022 /* no optimisation possible if smaller conv is sign-extend */
1023 if(mode_is_signed(pred_mode)) {
1026 /* we can take the smaller conv if it is unsigned */
1027 result_conv = pred_proj;
1032 exchange(node, result_conv);
1034 if(get_irn_n_edges(pred_proj) == 0) {
1035 be_kill_node(pred_proj);
1036 if(pred != pred_proj)
1039 optimize_conv_conv(result_conv);
1042 static void optimize_node(ir_node *node, void *env)
1046 optimize_load_conv(node);
1047 optimize_conv_store(node);
1048 optimize_conv_conv(node);
1052 * Performs conv and address mode optimization.
1054 void ia32_optimize_graph(ia32_code_gen_t *cg)
1056 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1059 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1062 void ia32_init_optimize(void)
1064 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");