2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
44 #include "../benode_t.h"
45 #include "../besched_t.h"
46 #include "../bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_util.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static ia32_code_gen_t *cg;
62 static void copy_mark(const ir_node *old, ir_node *new)
64 if (is_ia32_is_reload(old))
65 set_ia32_is_reload(new);
66 if (is_ia32_is_spill(old))
67 set_ia32_is_spill(new);
68 if (is_ia32_is_remat(old))
69 set_ia32_is_remat(new);
72 typedef enum produces_flag_t {
79 * Return which usable flag the given node produces
81 * @param node the node to check
82 * @param pn the projection number of the used result
84 static produces_flag_t produces_test_flag(ir_node *node, int pn)
87 const ia32_immediate_attr_t *imm_attr;
89 if (!is_ia32_irn(node))
90 return produces_no_flag;
92 switch (get_ia32_irn_opcode(node)) {
107 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
108 count = get_irn_n(node, n_ia32_ShlD_count);
109 goto check_shift_amount;
114 assert(n_ia32_Shl_count == n_ia32_Shr_count
115 && n_ia32_Shl_count == n_ia32_Sar_count);
116 count = get_irn_n(node, n_ia32_Shl_count);
118 /* when shift count is zero the flags are not affected, so we can only
119 * do this for constants != 0 */
120 if (!is_ia32_Immediate(count))
121 return produces_no_flag;
123 imm_attr = get_ia32_immediate_attr_const(count);
124 if (imm_attr->symconst != NULL)
125 return produces_no_flag;
126 if ((imm_attr->offset & 0x1f) == 0)
127 return produces_no_flag;
131 return pn == pn_ia32_Mul_res_high ?
132 produces_flag_carry : produces_no_flag;
135 return produces_no_flag;
138 return pn == pn_ia32_res ?
139 produces_flag_zero : produces_no_flag;
143 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
145 * @param node the node to change
147 * @return the new mode_T node (if the mode was changed) or node itself
149 static ir_node *turn_into_mode_t(ir_node *node)
154 const arch_register_t *reg;
156 if(get_irn_mode(node) == mode_T)
159 assert(get_irn_mode(node) == mode_Iu);
161 new_node = exact_copy(node);
162 set_irn_mode(new_node, mode_T);
164 block = get_nodes_block(new_node);
165 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
168 reg = arch_get_irn_register(node);
169 arch_set_irn_register(res_proj, reg);
171 sched_add_before(node, new_node);
172 be_peephole_exchange(node, res_proj);
177 * Replace Cmp(x, 0) by a Test(x, x)
179 static void peephole_ia32_Cmp(ir_node *const node)
182 ia32_immediate_attr_t const *imm;
189 ia32_attr_t const *attr;
193 arch_register_t const *reg;
194 ir_edge_t const *edge;
195 ir_edge_t const *tmp;
197 if (get_ia32_op_type(node) != ia32_Normal)
200 right = get_irn_n(node, n_ia32_Cmp_right);
201 if (!is_ia32_Immediate(right))
204 imm = get_ia32_immediate_attr_const(right);
205 if (imm->symconst != NULL || imm->offset != 0)
208 dbgi = get_irn_dbg_info(node);
209 irg = current_ir_graph;
210 block = get_nodes_block(node);
211 noreg = ia32_new_NoReg_gp(cg);
212 nomem = get_irg_no_mem(irg);
213 op = get_irn_n(node, n_ia32_Cmp_left);
214 attr = get_irn_generic_attr(node);
215 ins_permuted = attr->data.ins_permuted;
216 cmp_unsigned = attr->data.cmp_unsigned;
218 if (is_ia32_Cmp(node)) {
219 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
220 op, op, ins_permuted, cmp_unsigned);
222 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
223 op, op, ins_permuted, cmp_unsigned);
225 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
227 reg = arch_get_irn_register(node);
228 arch_set_irn_register(test, reg);
230 foreach_out_edge_safe(node, edge, tmp) {
231 ir_node *const user = get_edge_src_irn(edge);
234 exchange(user, test);
237 sched_add_before(node, test);
238 copy_mark(node, test);
239 be_peephole_exchange(node, test);
243 * Peephole optimization for Test instructions.
244 * - Remove the Test, if an appropriate flag was produced which is still live
245 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
247 static void peephole_ia32_Test(ir_node *node)
249 ir_node *left = get_irn_n(node, n_ia32_Test_left);
250 ir_node *right = get_irn_n(node, n_ia32_Test_right);
252 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
253 && n_ia32_Test_right == n_ia32_Test8Bit_right);
255 if (left == right) { /* we need a test for 0 */
256 ir_node *block = get_nodes_block(node);
257 int pn = pn_ia32_res;
261 const ir_edge_t *edge;
263 if (get_nodes_block(left) != block)
267 pn = get_Proj_proj(left);
268 left = get_Proj_pred(left);
271 /* happens rarely, but if it does code will panic' */
272 if (is_ia32_Unknown_GP(left))
275 /* walk schedule up and abort when we find left or some other node destroys
279 schedpoint = sched_prev(schedpoint);
280 if (schedpoint == left)
282 if (arch_irn_is(schedpoint, modify_flags))
284 if (schedpoint == block)
285 panic("couldn't find left");
288 /* make sure only Lg/Eq tests are used */
289 foreach_out_edge(node, edge) {
290 ir_node *user = get_edge_src_irn(edge);
291 int pnc = get_ia32_condcode(user);
293 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
298 switch (produces_test_flag(left, pn)) {
299 case produces_flag_zero:
302 case produces_flag_carry:
303 foreach_out_edge(node, edge) {
304 ir_node *user = get_edge_src_irn(edge);
305 int pnc = get_ia32_condcode(user);
308 case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
309 case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
310 default: panic("unexpected pn");
312 set_ia32_condcode(user, pnc);
320 left = turn_into_mode_t(left);
322 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
323 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
325 arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
327 assert(get_irn_mode(node) != mode_T);
329 be_peephole_exchange(node, flags_proj);
330 } else if (is_ia32_Immediate(right)) {
331 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
334 /* A test with a symconst is rather strange, but better safe than sorry */
335 if (imm->symconst != NULL)
338 offset = imm->offset;
339 if (get_ia32_op_type(node) == ia32_AddrModeS) {
340 ia32_attr_t *const attr = get_irn_generic_attr(node);
342 if ((offset & 0xFFFFFF00) == 0) {
343 /* attr->am_offs += 0; */
344 } else if ((offset & 0xFFFF00FF) == 0) {
345 ir_node *imm = create_Immediate(NULL, 0, offset >> 8);
346 set_irn_n(node, n_ia32_Test_right, imm);
348 } else if ((offset & 0xFF00FFFF) == 0) {
349 ir_node *imm = create_Immediate(NULL, 0, offset >> 16);
350 set_irn_n(node, n_ia32_Test_right, imm);
352 } else if ((offset & 0x00FFFFFF) == 0) {
353 ir_node *imm = create_Immediate(NULL, 0, offset >> 24);
354 set_irn_n(node, n_ia32_Test_right, imm);
359 } else if (offset < 256) {
360 arch_register_t const* const reg = arch_get_irn_register(left);
362 if (reg != &ia32_gp_regs[REG_EAX] &&
363 reg != &ia32_gp_regs[REG_EBX] &&
364 reg != &ia32_gp_regs[REG_ECX] &&
365 reg != &ia32_gp_regs[REG_EDX]) {
372 /* Technically we should build a Test8Bit because of the register
373 * constraints, but nobody changes registers at this point anymore. */
374 set_ia32_ls_mode(node, mode_Bu);
379 * AMD Athlon works faster when RET is not destination of
380 * conditional jump or directly preceded by other jump instruction.
381 * Can be avoided by placing a Rep prefix before the return.
383 static void peephole_ia32_Return(ir_node *node) {
384 ir_node *block, *irn;
386 if (!ia32_cg_config.use_pad_return)
389 block = get_nodes_block(node);
391 /* check if this return is the first on the block */
392 sched_foreach_reverse_from(node, irn) {
393 switch (get_irn_opcode(irn)) {
395 /* the return node itself, ignore */
400 /* ignore no code generated */
403 /* arg, IncSP 0 nodes might occur, ignore these */
404 if (be_get_IncSP_offset(irn) == 0)
414 /* ensure, that the 3 byte return is generated */
415 be_Return_set_emit_pop(node, 1);
418 /* only optimize up to 48 stores behind IncSPs */
419 #define MAXPUSH_OPTIMIZE 48
422 * Tries to create Push's from IncSP, Store combinations.
423 * The Stores are replaced by Push's, the IncSP is modified
424 * (possibly into IncSP 0, but not removed).
426 static void peephole_IncSP_Store_to_push(ir_node *irn)
432 ir_node *stores[MAXPUSH_OPTIMIZE];
437 ir_node *first_push = NULL;
438 ir_edge_t const *edge;
439 ir_edge_t const *next;
441 memset(stores, 0, sizeof(stores));
443 assert(be_is_IncSP(irn));
445 inc_ofs = be_get_IncSP_offset(irn);
450 * We first walk the schedule after the IncSP node as long as we find
451 * suitable Stores that could be transformed to a Push.
452 * We save them into the stores array which is sorted by the frame offset/4
453 * attached to the node
456 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
461 /* it has to be a Store */
462 if (!is_ia32_Store(node))
465 /* it has to use our sp value */
466 if (get_irn_n(node, n_ia32_base) != irn)
468 /* Store has to be attached to NoMem */
469 mem = get_irn_n(node, n_ia32_mem);
473 /* unfortunately we can't support the full AMs possible for push at the
474 * moment. TODO: fix this */
475 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
478 offset = get_ia32_am_offs_int(node);
479 /* we should NEVER access uninitialized stack BELOW the current SP */
482 /* storing at half-slots is bad */
483 if ((offset & 3) != 0)
486 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
488 storeslot = offset >> 2;
490 /* storing into the same slot twice is bad (and shouldn't happen...) */
491 if (stores[storeslot] != NULL)
494 stores[storeslot] = node;
495 if (storeslot > maxslot)
501 for (i = -1; i < maxslot; ++i) {
502 if (stores[i + 1] == NULL)
506 /* walk through the Stores and create Pushs for them */
507 block = get_nodes_block(irn);
508 spmode = get_irn_mode(irn);
510 for (; i >= 0; --i) {
511 const arch_register_t *spreg;
513 ir_node *val, *mem, *mem_proj;
514 ir_node *store = stores[i];
515 ir_node *noreg = ia32_new_NoReg_gp(cg);
517 val = get_irn_n(store, n_ia32_unary_op);
518 mem = get_irn_n(store, n_ia32_mem);
519 spreg = arch_get_irn_register(curr_sp);
521 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
522 copy_mark(store, push);
524 if (first_push == NULL)
527 sched_add_after(curr_sp, push);
529 /* create stackpointer Proj */
530 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
531 arch_set_irn_register(curr_sp, spreg);
533 /* create memory Proj */
534 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
536 /* use the memproj now */
537 be_peephole_exchange(store, mem_proj);
542 foreach_out_edge_safe(irn, edge, next) {
543 ir_node *const src = get_edge_src_irn(edge);
544 int const pos = get_edge_src_pos(edge);
546 if (src == first_push)
549 set_irn_n(src, pos, curr_sp);
552 be_set_IncSP_offset(irn, inc_ofs);
556 static void peephole_store_incsp(ir_node *store)
565 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
566 if (!be_is_IncSP(am_base)
567 || get_nodes_block(am_base) != get_nodes_block(store))
569 mem = get_irn_n(store, n_ia32_Store_mem);
570 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
574 int incsp_offset = be_get_IncSP_offset(am_base);
575 if (incsp_offset <= 0)
578 /* we have to be at offset 0 */
579 int my_offset = get_ia32_am_offs_int(store);
580 if (my_offset != 0) {
581 /* TODO here: find out wether there is a store with offset 0 before
582 * us and wether we can move it down to our place */
585 ir_mode *ls_mode = get_ia32_ls_mode(store);
586 int my_store_size = get_mode_size_bytes(ls_mode);
588 if (my_offset + my_store_size > incsp_offset)
591 /* correctness checking:
592 - noone else must write to that stackslot
593 (because after translation incsp won't allocate it anymore)
595 sched_foreach_reverse_from(store, node) {
601 /* make sure noone else can use the space on the stack */
602 arity = get_irn_arity(node);
603 for (i = 0; i < arity; ++i) {
604 ir_node *pred = get_irn_n(node, i);
608 if (i == n_ia32_base &&
609 (get_ia32_op_type(node) == ia32_AddrModeS
610 || get_ia32_op_type(node) == ia32_AddrModeD)) {
611 int node_offset = get_ia32_am_offs_int(node);
612 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
613 int node_size = get_mode_size_bytes(node);
614 /* overlapping with our position? abort */
615 if (node_offset < my_offset + my_store_size
616 && node_offset + node_size >= my_offset)
618 /* otherwise it's fine */
622 /* strange use of esp: abort */
627 /* all ok, change to push */
628 dbgi = get_irn_dbg_info(store);
629 block = get_nodes_block(store);
630 noreg = ia32_new_NoReg_gp(cg);
633 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem,
635 create_push(dbgi, current_ir_graph, block, am_base, store);
640 * Return true if a mode can be stored in the GP register set
642 static inline int mode_needs_gp_reg(ir_mode *mode) {
643 if (mode == mode_fpcw)
645 if (get_mode_size_bits(mode) > 32)
647 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
651 * Tries to create Pops from Load, IncSP combinations.
652 * The Loads are replaced by Pops, the IncSP is modified
653 * (possibly into IncSP 0, but not removed).
655 static void peephole_Load_IncSP_to_pop(ir_node *irn)
657 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
658 int i, maxslot, inc_ofs, ofs;
659 ir_node *node, *pred_sp, *block;
660 ir_node *loads[MAXPUSH_OPTIMIZE];
662 unsigned regmask = 0;
663 unsigned copymask = ~0;
665 memset(loads, 0, sizeof(loads));
666 assert(be_is_IncSP(irn));
668 inc_ofs = -be_get_IncSP_offset(irn);
673 * We first walk the schedule before the IncSP node as long as we find
674 * suitable Loads that could be transformed to a Pop.
675 * We save them into the stores array which is sorted by the frame offset/4
676 * attached to the node
679 pred_sp = be_get_IncSP_pred(irn);
680 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
683 const arch_register_t *sreg, *dreg;
685 /* it has to be a Load */
686 if (!is_ia32_Load(node)) {
687 if (be_is_Copy(node)) {
688 if (!mode_needs_gp_reg(get_irn_mode(node))) {
689 /* not a GP copy, ignore */
692 dreg = arch_get_irn_register(node);
693 sreg = arch_get_irn_register(be_get_Copy_op(node));
694 if (regmask & copymask & (1 << sreg->index)) {
697 if (regmask & copymask & (1 << dreg->index)) {
700 /* we CAN skip Copies if neither the destination nor the source
701 * is not in our regmask, ie none of our future Pop will overwrite it */
702 regmask |= (1 << dreg->index) | (1 << sreg->index);
703 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
709 /* we can handle only GP loads */
710 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
713 /* it has to use our predecessor sp value */
714 if (get_irn_n(node, n_ia32_base) != pred_sp) {
715 /* it would be ok if this load does not use a Pop result,
716 * but we do not check this */
720 /* should have NO index */
721 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
724 offset = get_ia32_am_offs_int(node);
725 /* we should NEVER access uninitialized stack BELOW the current SP */
728 /* storing at half-slots is bad */
729 if ((offset & 3) != 0)
732 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
734 /* ignore those outside the possible windows */
735 if (offset > inc_ofs - 4)
737 loadslot = offset >> 2;
739 /* loading from the same slot twice is bad (and shouldn't happen...) */
740 if (loads[loadslot] != NULL)
743 dreg = arch_get_irn_register(node);
744 if (regmask & (1 << dreg->index)) {
745 /* this register is already used */
748 regmask |= 1 << dreg->index;
750 loads[loadslot] = node;
751 if (loadslot > maxslot)
758 /* find the first slot */
759 for (i = maxslot; i >= 0; --i) {
760 ir_node *load = loads[i];
766 ofs = inc_ofs - (maxslot + 1) * 4;
769 /* create a new IncSP if needed */
770 block = get_nodes_block(irn);
773 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
774 sched_add_before(irn, pred_sp);
777 /* walk through the Loads and create Pops for them */
778 for (++i; i <= maxslot; ++i) {
779 ir_node *load = loads[i];
781 const ir_edge_t *edge, *tmp;
782 const arch_register_t *reg;
784 mem = get_irn_n(load, n_ia32_mem);
785 reg = arch_get_irn_register(load);
787 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
788 arch_set_irn_register(pop, reg);
790 copy_mark(load, pop);
792 /* create stackpointer Proj */
793 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
794 arch_set_irn_register(pred_sp, esp);
796 sched_add_before(irn, pop);
799 foreach_out_edge_safe(load, edge, tmp) {
800 ir_node *proj = get_edge_src_irn(edge);
802 set_Proj_pred(proj, pop);
805 /* we can remove the Load now */
810 be_set_IncSP_offset(irn, -ofs);
811 be_set_IncSP_pred(irn, pred_sp);
816 * Find a free GP register if possible, else return NULL.
818 static const arch_register_t *get_free_gp_reg(void)
822 for(i = 0; i < N_ia32_gp_REGS; ++i) {
823 const arch_register_t *reg = &ia32_gp_regs[i];
824 if(arch_register_type_is(reg, ignore))
827 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
828 return &ia32_gp_regs[i];
835 * Creates a Pop instruction before the given schedule point.
837 * @param dbgi debug info
838 * @param irg the graph
839 * @param block the block
840 * @param stack the previous stack value
841 * @param schedpoint the new node is added before this node
842 * @param reg the register to pop
844 * @return the new stack value
846 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
847 ir_node *stack, ir_node *schedpoint,
848 const arch_register_t *reg)
850 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
856 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
858 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
859 arch_set_irn_register(stack, esp);
860 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
861 arch_set_irn_register(val, reg);
863 sched_add_before(schedpoint, pop);
866 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
867 sched_add_before(schedpoint, keep);
873 * Creates a Push instruction before the given schedule point.
875 * @param dbgi debug info
876 * @param irg the graph
877 * @param block the block
878 * @param stack the previous stack value
879 * @param schedpoint the new node is added before this node
880 * @param reg the register to pop
882 * @return the new stack value
884 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
885 ir_node *stack, ir_node *schedpoint)
887 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
889 ir_node *val = ia32_new_Unknown_gp(cg);
890 ir_node *noreg = ia32_new_NoReg_gp(cg);
891 ir_node *nomem = get_irg_no_mem(irg);
892 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
893 sched_add_before(schedpoint, push);
895 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
896 arch_set_irn_register(stack, esp);
902 * Optimize an IncSp by replacing it with Push/Pop.
904 static void peephole_be_IncSP(ir_node *node)
906 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
907 const arch_register_t *reg;
908 ir_graph *irg = current_ir_graph;
914 /* first optimize incsp->incsp combinations */
915 node = be_peephole_IncSP_IncSP(node);
917 /* transform IncSP->Store combinations to Push where possible */
918 peephole_IncSP_Store_to_push(node);
920 /* transform Load->IncSP combinations to Pop where possible */
921 peephole_Load_IncSP_to_pop(node);
923 if (arch_get_irn_register(node) != esp)
926 /* replace IncSP -4 by Pop freereg when possible */
927 offset = be_get_IncSP_offset(node);
928 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
929 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
930 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
931 (offset != +8 || ia32_cg_config.use_sub_esp_8))
935 /* we need a free register for pop */
936 reg = get_free_gp_reg();
940 dbgi = get_irn_dbg_info(node);
941 block = get_nodes_block(node);
942 stack = be_get_IncSP_pred(node);
944 stack = create_pop(dbgi, irg, block, stack, node, reg);
947 stack = create_pop(dbgi, irg, block, stack, node, reg);
950 dbgi = get_irn_dbg_info(node);
951 block = get_nodes_block(node);
952 stack = be_get_IncSP_pred(node);
953 stack = create_push(dbgi, irg, block, stack, node);
956 stack = create_push(dbgi, irg, block, stack, node);
960 be_peephole_exchange(node, stack);
964 * Peephole optimisation for ia32_Const's
966 static void peephole_ia32_Const(ir_node *node)
968 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
969 const arch_register_t *reg;
970 ir_graph *irg = current_ir_graph;
977 /* try to transform a mov 0, reg to xor reg reg */
978 if (attr->offset != 0 || attr->symconst != NULL)
980 if (ia32_cg_config.use_mov_0)
982 /* xor destroys the flags, so no-one must be using them */
983 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
986 reg = arch_get_irn_register(node);
987 assert(be_peephole_get_reg_value(reg) == NULL);
989 /* create xor(produceval, produceval) */
990 block = get_nodes_block(node);
991 dbgi = get_irn_dbg_info(node);
992 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
993 arch_set_irn_register(produceval, reg);
995 noreg = ia32_new_NoReg_gp(cg);
996 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
997 produceval, produceval);
998 arch_set_irn_register(xor, reg);
1000 sched_add_before(node, produceval);
1001 sched_add_before(node, xor);
1003 copy_mark(node, xor);
1004 be_peephole_exchange(node, xor);
1007 static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
1009 return node == cg->noreg_gp;
1012 static ir_node *create_immediate_from_int(int val)
1014 ir_graph *irg = current_ir_graph;
1015 ir_node *start_block = get_irg_start_block(irg);
1016 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
1018 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
1023 static ir_node *create_immediate_from_am(const ir_node *node)
1025 ir_graph *irg = get_irn_irg(node);
1026 ir_node *block = get_nodes_block(node);
1027 int offset = get_ia32_am_offs_int(node);
1028 int sc_sign = is_ia32_am_sc_sign(node);
1029 ir_entity *entity = get_ia32_am_sc(node);
1032 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
1033 arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
1037 static int is_am_one(const ir_node *node)
1039 int offset = get_ia32_am_offs_int(node);
1040 ir_entity *entity = get_ia32_am_sc(node);
1042 return offset == 1 && entity == NULL;
1045 static int is_am_minus_one(const ir_node *node)
1047 int offset = get_ia32_am_offs_int(node);
1048 ir_entity *entity = get_ia32_am_sc(node);
1050 return offset == -1 && entity == NULL;
1054 * Transforms a LEA into an Add or SHL if possible.
1056 static void peephole_ia32_Lea(ir_node *node)
1058 ir_graph *irg = current_ir_graph;
1061 const arch_register_t *base_reg;
1062 const arch_register_t *index_reg;
1063 const arch_register_t *out_reg;
1074 assert(is_ia32_Lea(node));
1076 /* we can only do this if are allowed to globber the flags */
1077 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1080 base = get_irn_n(node, n_ia32_Lea_base);
1081 index = get_irn_n(node, n_ia32_Lea_index);
1083 if(is_noreg(cg, base)) {
1087 base_reg = arch_get_irn_register(base);
1089 if(is_noreg(cg, index)) {
1093 index_reg = arch_get_irn_register(index);
1096 if(base == NULL && index == NULL) {
1097 /* we shouldn't construct these in the first place... */
1098 #ifdef DEBUG_libfirm
1099 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1104 out_reg = arch_get_irn_register(node);
1105 scale = get_ia32_am_scale(node);
1106 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1107 /* check if we have immediates values (frame entities should already be
1108 * expressed in the offsets) */
1109 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1115 /* we can transform leas where the out register is the same as either the
1116 * base or index register back to an Add or Shl */
1117 if(out_reg == base_reg) {
1119 #ifdef DEBUG_libfirm
1120 if(!has_immediates) {
1121 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1126 goto make_add_immediate;
1128 if(scale == 0 && !has_immediates) {
1133 /* can't create an add */
1135 } else if(out_reg == index_reg) {
1137 if(has_immediates && scale == 0) {
1139 goto make_add_immediate;
1140 } else if(!has_immediates && scale > 0) {
1142 op2 = create_immediate_from_int(scale);
1144 } else if(!has_immediates) {
1145 #ifdef DEBUG_libfirm
1146 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1150 } else if(scale == 0 && !has_immediates) {
1155 /* can't create an add */
1158 /* can't create an add */
1163 if(ia32_cg_config.use_incdec) {
1164 if(is_am_one(node)) {
1165 dbgi = get_irn_dbg_info(node);
1166 block = get_nodes_block(node);
1167 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
1168 arch_set_irn_register(res, out_reg);
1171 if(is_am_minus_one(node)) {
1172 dbgi = get_irn_dbg_info(node);
1173 block = get_nodes_block(node);
1174 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
1175 arch_set_irn_register(res, out_reg);
1179 op2 = create_immediate_from_am(node);
1182 dbgi = get_irn_dbg_info(node);
1183 block = get_nodes_block(node);
1184 noreg = ia32_new_NoReg_gp(cg);
1185 nomem = new_NoMem();
1186 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1187 arch_set_irn_register(res, out_reg);
1188 set_ia32_commutative(res);
1192 dbgi = get_irn_dbg_info(node);
1193 block = get_nodes_block(node);
1194 noreg = ia32_new_NoReg_gp(cg);
1195 nomem = new_NoMem();
1196 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1197 arch_set_irn_register(res, out_reg);
1201 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1203 /* add new ADD/SHL to schedule */
1204 DBG_OPT_LEA2ADD(node, res);
1206 /* exchange the Add and the LEA */
1207 sched_add_before(node, res);
1208 copy_mark(node, res);
1209 be_peephole_exchange(node, res);
1213 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1215 static void peephole_ia32_Imul_split(ir_node *imul)
1217 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1218 const arch_register_t *reg;
1221 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1222 /* no memory, imm form ignore */
1225 /* we need a free register */
1226 reg = get_free_gp_reg();
1230 /* fine, we can rebuild it */
1231 res = turn_back_am(imul);
1232 arch_set_irn_register(res, reg);
1236 * Replace xorps r,r and xorpd r,r by pxor r,r
1238 static void peephole_ia32_xZero(ir_node *xor) {
1239 set_irn_op(xor, op_ia32_xPzero);
1243 * Register a peephole optimisation function.
1245 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1246 assert(op->ops.generic == NULL);
1247 op->ops.generic = (op_func)func;
1250 /* Perform peephole-optimizations. */
1251 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1255 /* register peephole optimisations */
1256 clear_irp_opcodes_generic_func();
1257 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1258 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1259 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1260 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1261 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1262 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1263 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1264 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1265 if (! ia32_cg_config.use_imul_mem_imm32)
1266 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1267 if (ia32_cg_config.use_pxor)
1268 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1270 be_peephole_opt(cg->birg);
1274 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1275 * all it's Projs are removed as well.
1276 * @param irn The irn to be removed from schedule
1278 static inline void try_kill(ir_node *node)
1280 if(get_irn_mode(node) == mode_T) {
1281 const ir_edge_t *edge, *next;
1282 foreach_out_edge_safe(node, edge, next) {
1283 ir_node *proj = get_edge_src_irn(edge);
1288 if(get_irn_n_edges(node) != 0)
1291 if (sched_is_scheduled(node)) {
1298 static void optimize_conv_store(ir_node *node)
1303 ir_mode *store_mode;
1305 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1308 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1309 pred_proj = get_irn_n(node, n_ia32_Store_val);
1310 if(is_Proj(pred_proj)) {
1311 pred = get_Proj_pred(pred_proj);
1315 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1317 if(get_ia32_op_type(pred) != ia32_Normal)
1320 /* the store only stores the lower bits, so we only need the conv
1321 * it it shrinks the mode */
1322 conv_mode = get_ia32_ls_mode(pred);
1323 store_mode = get_ia32_ls_mode(node);
1324 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1327 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1328 if(get_irn_n_edges(pred_proj) == 0) {
1329 kill_node(pred_proj);
1330 if(pred != pred_proj)
1335 static void optimize_load_conv(ir_node *node)
1337 ir_node *pred, *predpred;
1341 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1344 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1345 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1349 predpred = get_Proj_pred(pred);
1350 if(!is_ia32_Load(predpred))
1353 /* the load is sign extending the upper bits, so we only need the conv
1354 * if it shrinks the mode */
1355 load_mode = get_ia32_ls_mode(predpred);
1356 conv_mode = get_ia32_ls_mode(node);
1357 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1360 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1361 /* change the load if it has only 1 user */
1362 if(get_irn_n_edges(pred) == 1) {
1364 if(get_mode_sign(conv_mode)) {
1365 newmode = find_signed_mode(load_mode);
1367 newmode = find_unsigned_mode(load_mode);
1369 assert(newmode != NULL);
1370 set_ia32_ls_mode(predpred, newmode);
1372 /* otherwise we have to keep the conv */
1378 exchange(node, pred);
1381 static void optimize_conv_conv(ir_node *node)
1383 ir_node *pred_proj, *pred, *result_conv;
1384 ir_mode *pred_mode, *conv_mode;
1388 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1391 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1392 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1393 if(is_Proj(pred_proj))
1394 pred = get_Proj_pred(pred_proj);
1398 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1401 /* we know that after a conv, the upper bits are sign extended
1402 * so we only need the 2nd conv if it shrinks the mode */
1403 conv_mode = get_ia32_ls_mode(node);
1404 conv_mode_bits = get_mode_size_bits(conv_mode);
1405 pred_mode = get_ia32_ls_mode(pred);
1406 pred_mode_bits = get_mode_size_bits(pred_mode);
1408 if(conv_mode_bits == pred_mode_bits
1409 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1410 result_conv = pred_proj;
1411 } else if(conv_mode_bits <= pred_mode_bits) {
1412 /* if 2nd conv is smaller then first conv, then we can always take the
1414 if(get_irn_n_edges(pred_proj) == 1) {
1415 result_conv = pred_proj;
1416 set_ia32_ls_mode(pred, conv_mode);
1418 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1419 if (get_mode_size_bits(conv_mode) == 8) {
1420 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1421 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1424 /* we don't want to end up with 2 loads, so we better do nothing */
1425 if(get_irn_mode(pred) == mode_T) {
1429 result_conv = exact_copy(pred);
1430 set_ia32_ls_mode(result_conv, conv_mode);
1432 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1433 if (get_mode_size_bits(conv_mode) == 8) {
1434 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1435 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1439 /* if both convs have the same sign, then we can take the smaller one */
1440 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1441 result_conv = pred_proj;
1443 /* no optimisation possible if smaller conv is sign-extend */
1444 if(mode_is_signed(pred_mode)) {
1447 /* we can take the smaller conv if it is unsigned */
1448 result_conv = pred_proj;
1453 exchange(node, result_conv);
1455 if(get_irn_n_edges(pred_proj) == 0) {
1456 kill_node(pred_proj);
1457 if(pred != pred_proj)
1460 optimize_conv_conv(result_conv);
1463 static void optimize_node(ir_node *node, void *env)
1467 optimize_load_conv(node);
1468 optimize_conv_store(node);
1469 optimize_conv_conv(node);
1473 * Performs conv and address mode optimization.
1475 void ia32_optimize_graph(ia32_code_gen_t *cg)
1477 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1480 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1483 void ia32_init_optimize(void)
1485 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");