2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_common_transform.h"
55 #include "ia32_transform.h"
56 #include "ia32_dbg_stat.h"
57 #include "ia32_util.h"
58 #include "ia32_architecture.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static const arch_env_t *arch_env;
63 static ia32_code_gen_t *cg;
66 * Returns non-zero if the given node produces
69 * @param node the node to check
70 * @param pn if >= 0, the projection number of the used result
72 static int produces_zero_flag(ir_node *node, int pn)
75 const ia32_immediate_attr_t *imm_attr;
77 if (!is_ia32_irn(node))
81 if (pn != pn_ia32_res)
85 switch (get_ia32_irn_opcode(node)) {
103 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
104 assert(n_ia32_Shl_count == n_ia32_Shr_count
105 && n_ia32_Shl_count == n_ia32_Sar_count);
106 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
107 count = get_irn_n(node, n_ia32_ShlD_count);
109 count = get_irn_n(node, n_ia32_Shl_count);
111 /* when shift count is zero the flags are not affected, so we can only
112 * do this for constants != 0 */
113 if (!is_ia32_Immediate(count))
116 imm_attr = get_ia32_immediate_attr_const(count);
117 if (imm_attr->symconst != NULL)
119 if ((imm_attr->offset & 0x1f) == 0)
130 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
132 * @param node the node to change
134 * @return the new mode_T node (if the mode was changed) or node itself
136 static ir_node *turn_into_mode_t(ir_node *node)
141 const arch_register_t *reg;
143 if(get_irn_mode(node) == mode_T)
146 assert(get_irn_mode(node) == mode_Iu);
148 new_node = exact_copy(node);
149 set_irn_mode(new_node, mode_T);
151 block = get_nodes_block(new_node);
152 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
155 reg = arch_get_irn_register(arch_env, node);
156 arch_set_irn_register(arch_env, res_proj, reg);
158 sched_add_before(node, new_node);
159 be_peephole_exchange(node, res_proj);
164 * Replace Cmp(x, 0) by a Test(x, x)
166 static void peephole_ia32_Cmp(ir_node *const node)
169 ia32_immediate_attr_t const *imm;
176 ia32_attr_t const *attr;
180 arch_register_t const *reg;
182 if (get_ia32_op_type(node) != ia32_Normal)
185 right = get_irn_n(node, n_ia32_Cmp_right);
186 if (!is_ia32_Immediate(right))
189 imm = get_ia32_immediate_attr_const(right);
190 if (imm->symconst != NULL || imm->offset != 0)
193 dbgi = get_irn_dbg_info(node);
194 irg = current_ir_graph;
195 block = get_nodes_block(node);
196 noreg = ia32_new_NoReg_gp(cg);
197 nomem = get_irg_no_mem(irg);
198 op = get_irn_n(node, n_ia32_Cmp_left);
199 attr = get_irn_generic_attr(node);
200 ins_permuted = attr->data.ins_permuted;
201 cmp_unsigned = attr->data.cmp_unsigned;
203 if (is_ia32_Cmp(node)) {
204 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
205 op, op, ins_permuted, cmp_unsigned);
207 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
208 op, op, ins_permuted, cmp_unsigned);
210 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
212 reg = arch_get_irn_register(arch_env, node);
213 arch_set_irn_register(arch_env, test, reg);
215 sched_add_before(node, test);
216 be_peephole_exchange(node, test);
220 * Peephole optimization for Test instructions.
221 * We can remove the Test, if a zero flags was produced which is still
224 static void peephole_ia32_Test(ir_node *node)
226 ir_node *left = get_irn_n(node, n_ia32_Test_left);
227 ir_node *right = get_irn_n(node, n_ia32_Test_right);
233 const ir_edge_t *edge;
235 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
236 && n_ia32_Test_right == n_ia32_Test8Bit_right);
238 /* we need a test for 0 */
242 block = get_nodes_block(node);
243 if(get_nodes_block(left) != block)
247 pn = get_Proj_proj(left);
248 left = get_Proj_pred(left);
251 /* happens rarely, but if it does code will panic' */
252 if (is_ia32_Unknown_GP(left))
255 /* walk schedule up and abort when we find left or some other node destroys
257 schedpoint = sched_prev(node);
258 while(schedpoint != left) {
259 schedpoint = sched_prev(schedpoint);
260 if(arch_irn_is(arch_env, schedpoint, modify_flags))
262 if(schedpoint == block)
263 panic("couldn't find left");
266 /* make sure only Lg/Eq tests are used */
267 foreach_out_edge(node, edge) {
268 ir_node *user = get_edge_src_irn(edge);
269 int pnc = get_ia32_condcode(user);
271 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
276 if(!produces_zero_flag(left, pn))
279 left = turn_into_mode_t(left);
281 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
282 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
284 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
286 assert(get_irn_mode(node) != mode_T);
288 be_peephole_exchange(node, flags_proj);
292 * AMD Athlon works faster when RET is not destination of
293 * conditional jump or directly preceded by other jump instruction.
294 * Can be avoided by placing a Rep prefix before the return.
296 static void peephole_ia32_Return(ir_node *node) {
297 ir_node *block, *irn;
299 if (!ia32_cg_config.use_pad_return)
302 block = get_nodes_block(node);
304 /* check if this return is the first on the block */
305 sched_foreach_reverse_from(node, irn) {
306 switch (get_irn_opcode(irn)) {
308 /* the return node itself, ignore */
311 /* ignore the barrier, no code generated */
314 /* arg, IncSP 0 nodes might occur, ignore these */
315 if (be_get_IncSP_offset(irn) == 0)
325 /* ensure, that the 3 byte return is generated
326 * actually the emitter tests again if the block beginning has a label and
327 * isn't just a fallthrough */
328 be_Return_set_emit_pop(node, 1);
331 /* only optimize up to 48 stores behind IncSPs */
332 #define MAXPUSH_OPTIMIZE 48
335 * Tries to create Push's from IncSP, Store combinations.
336 * The Stores are replaced by Push's, the IncSP is modified
337 * (possibly into IncSP 0, but not removed).
339 static void peephole_IncSP_Store_to_push(ir_node *irn)
341 int i, maxslot, inc_ofs;
343 ir_node *stores[MAXPUSH_OPTIMIZE];
349 memset(stores, 0, sizeof(stores));
351 assert(be_is_IncSP(irn));
353 inc_ofs = be_get_IncSP_offset(irn);
358 * We first walk the schedule after the IncSP node as long as we find
359 * suitable Stores that could be transformed to a Push.
360 * We save them into the stores array which is sorted by the frame offset/4
361 * attached to the node
364 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
369 /* it has to be a Store */
370 if (!is_ia32_Store(node))
373 /* it has to use our sp value */
374 if (get_irn_n(node, n_ia32_base) != irn)
376 /* Store has to be attached to NoMem */
377 mem = get_irn_n(node, n_ia32_mem);
381 /* unfortunately we can't support the full AMs possible for push at the
382 * moment. TODO: fix this */
383 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
386 offset = get_ia32_am_offs_int(node);
387 /* we should NEVER access uninitialized stack BELOW the current SP */
390 offset = inc_ofs - 4 - offset;
392 /* storing at half-slots is bad */
393 if ((offset & 3) != 0)
396 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
398 storeslot = offset >> 2;
400 /* storing into the same slot twice is bad (and shouldn't happen...) */
401 if (stores[storeslot] != NULL)
404 stores[storeslot] = node;
405 if (storeslot > maxslot)
409 curr_sp = be_get_IncSP_pred(irn);
411 /* walk through the Stores and create Pushs for them */
412 block = get_nodes_block(irn);
413 spmode = get_irn_mode(irn);
415 for (i = 0; i <= maxslot; ++i) {
416 const arch_register_t *spreg;
418 ir_node *val, *mem, *mem_proj;
419 ir_node *store = stores[i];
420 ir_node *noreg = ia32_new_NoReg_gp(cg);
425 val = get_irn_n(store, n_ia32_unary_op);
426 mem = get_irn_n(store, n_ia32_mem);
427 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
429 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
431 sched_add_before(irn, push);
433 /* create stackpointer Proj */
434 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
435 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
437 /* create memory Proj */
438 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
440 /* use the memproj now */
441 be_peephole_exchange(store, mem_proj);
446 be_set_IncSP_offset(irn, inc_ofs);
447 be_set_IncSP_pred(irn, curr_sp);
451 * Return true if a mode can be stored in the GP register set
453 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
454 if (mode == mode_fpcw)
456 if (get_mode_size_bits(mode) > 32)
458 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
462 * Tries to create Pops from Load, IncSP combinations.
463 * The Loads are replaced by Pops, the IncSP is modified
464 * (possibly into IncSP 0, but not removed).
466 static void peephole_Load_IncSP_to_pop(ir_node *irn)
468 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
469 int i, maxslot, inc_ofs, ofs;
470 ir_node *node, *pred_sp, *block;
471 ir_node *loads[MAXPUSH_OPTIMIZE];
473 unsigned regmask = 0;
474 unsigned copymask = ~0;
476 memset(loads, 0, sizeof(loads));
477 assert(be_is_IncSP(irn));
479 inc_ofs = -be_get_IncSP_offset(irn);
484 * We first walk the schedule before the IncSP node as long as we find
485 * suitable Loads that could be transformed to a Pop.
486 * We save them into the stores array which is sorted by the frame offset/4
487 * attached to the node
490 pred_sp = be_get_IncSP_pred(irn);
491 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
495 const arch_register_t *sreg, *dreg;
497 /* it has to be a Load */
498 if (!is_ia32_Load(node)) {
499 if (be_is_Copy(node)) {
500 if (!mode_needs_gp_reg(get_irn_mode(node))) {
501 /* not a GP copy, ignore */
504 dreg = arch_get_irn_register(arch_env, node);
505 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
506 if (regmask & copymask & (1 << sreg->index)) {
509 if (regmask & copymask & (1 << dreg->index)) {
512 /* we CAN skip Copies if neither the destination nor the source
513 * is not in our regmask, ie none of our future Pop will overwrite it */
514 regmask |= (1 << dreg->index) | (1 << sreg->index);
515 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
521 /* we can handle only GP loads */
522 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
525 /* it has to use our predecessor sp value */
526 if (get_irn_n(node, n_ia32_base) != pred_sp) {
527 /* it would be ok if this load does not use a Pop result,
528 * but we do not check this */
531 /* Load has to be attached to Spill-Mem */
532 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
533 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
536 /* should have NO index */
537 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
540 offset = get_ia32_am_offs_int(node);
541 /* we should NEVER access uninitialized stack BELOW the current SP */
544 /* storing at half-slots is bad */
545 if ((offset & 3) != 0)
548 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
550 /* ignore those outside the possible windows */
551 if (offset > inc_ofs - 4)
553 loadslot = offset >> 2;
555 /* loading from the same slot twice is bad (and shouldn't happen...) */
556 if (loads[loadslot] != NULL)
559 dreg = arch_get_irn_register(arch_env, node);
560 if (regmask & (1 << dreg->index)) {
561 /* this register is already used */
564 regmask |= 1 << dreg->index;
566 loads[loadslot] = node;
567 if (loadslot > maxslot)
574 /* find the first slot */
575 for (i = maxslot; i >= 0; --i) {
576 ir_node *load = loads[i];
582 ofs = inc_ofs - (maxslot + 1) * 4;
585 /* create a new IncSP if needed */
586 block = get_nodes_block(irn);
589 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
590 sched_add_before(irn, pred_sp);
593 /* walk through the Loads and create Pops for them */
594 for (++i; i <= maxslot; ++i) {
595 ir_node *load = loads[i];
597 const ir_edge_t *edge, *tmp;
598 const arch_register_t *reg;
600 mem = get_irn_n(load, n_ia32_mem);
601 reg = arch_get_irn_register(arch_env, load);
603 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
604 arch_set_irn_register(arch_env, pop, reg);
606 /* create stackpointer Proj */
607 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
608 arch_set_irn_register(arch_env, pred_sp, esp);
610 sched_add_before(irn, pop);
613 foreach_out_edge_safe(load, edge, tmp) {
614 ir_node *proj = get_edge_src_irn(edge);
616 set_Proj_pred(proj, pop);
619 /* we can remove the Load now */
624 be_set_IncSP_offset(irn, -ofs);
625 be_set_IncSP_pred(irn, pred_sp);
630 * Find a free GP register if possible, else return NULL.
632 static const arch_register_t *get_free_gp_reg(void)
636 for(i = 0; i < N_ia32_gp_REGS; ++i) {
637 const arch_register_t *reg = &ia32_gp_regs[i];
638 if(arch_register_type_is(reg, ignore))
641 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
642 return &ia32_gp_regs[i];
649 * Creates a Pop instruction before the given schedule point.
651 * @param dbgi debug info
652 * @param irg the graph
653 * @param block the block
654 * @param stack the previous stack value
655 * @param schedpoint the new node is added before this node
656 * @param reg the register to pop
658 * @return the new stack value
660 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
661 ir_node *stack, ir_node *schedpoint,
662 const arch_register_t *reg)
664 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
670 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
672 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
673 arch_set_irn_register(arch_env, stack, esp);
674 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
675 arch_set_irn_register(arch_env, val, reg);
677 sched_add_before(schedpoint, pop);
680 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
681 sched_add_before(schedpoint, keep);
687 * Creates a Push instruction before the given schedule point.
689 * @param dbgi debug info
690 * @param irg the graph
691 * @param block the block
692 * @param stack the previous stack value
693 * @param schedpoint the new node is added before this node
694 * @param reg the register to pop
696 * @return the new stack value
698 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
699 ir_node *stack, ir_node *schedpoint)
701 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
703 ir_node *val = ia32_new_Unknown_gp(cg);
704 ir_node *noreg = ia32_new_NoReg_gp(cg);
705 ir_node *nomem = get_irg_no_mem(irg);
706 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
707 sched_add_before(schedpoint, push);
709 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
710 arch_set_irn_register(arch_env, stack, esp);
716 * Optimize an IncSp by replacing it with Push/Pop.
718 static void peephole_be_IncSP(ir_node *node)
720 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
721 const arch_register_t *reg;
722 ir_graph *irg = current_ir_graph;
728 /* first optimize incsp->incsp combinations */
729 node = be_peephole_IncSP_IncSP(node);
731 /* transform IncSP->Store combinations to Push where possible */
732 peephole_IncSP_Store_to_push(node);
734 /* transform Load->IncSP combinations to Pop where possible */
735 peephole_Load_IncSP_to_pop(node);
737 if (arch_get_irn_register(arch_env, node) != esp)
740 /* replace IncSP -4 by Pop freereg when possible */
741 offset = be_get_IncSP_offset(node);
742 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
743 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
744 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
745 (offset != +8 || ia32_cg_config.use_sub_esp_8))
749 /* we need a free register for pop */
750 reg = get_free_gp_reg();
754 dbgi = get_irn_dbg_info(node);
755 block = get_nodes_block(node);
756 stack = be_get_IncSP_pred(node);
758 stack = create_pop(dbgi, irg, block, stack, node, reg);
761 stack = create_pop(dbgi, irg, block, stack, node, reg);
764 dbgi = get_irn_dbg_info(node);
765 block = get_nodes_block(node);
766 stack = be_get_IncSP_pred(node);
767 stack = create_push(dbgi, irg, block, stack, node);
770 stack = create_push(dbgi, irg, block, stack, node);
774 be_peephole_exchange(node, stack);
778 * Peephole optimisation for ia32_Const's
780 static void peephole_ia32_Const(ir_node *node)
782 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
783 const arch_register_t *reg;
784 ir_graph *irg = current_ir_graph;
791 /* try to transform a mov 0, reg to xor reg reg */
792 if (attr->offset != 0 || attr->symconst != NULL)
794 if (ia32_cg_config.use_mov_0)
796 /* xor destroys the flags, so no-one must be using them */
797 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
800 reg = arch_get_irn_register(arch_env, node);
801 assert(be_peephole_get_reg_value(reg) == NULL);
803 /* create xor(produceval, produceval) */
804 block = get_nodes_block(node);
805 dbgi = get_irn_dbg_info(node);
806 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
807 arch_set_irn_register(arch_env, produceval, reg);
809 noreg = ia32_new_NoReg_gp(cg);
810 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
811 produceval, produceval);
812 arch_set_irn_register(arch_env, xor, reg);
814 sched_add_before(node, produceval);
815 sched_add_before(node, xor);
817 be_peephole_exchange(node, xor);
820 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
822 return node == cg->noreg_gp;
825 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
827 ir_graph *irg = current_ir_graph;
828 ir_node *start_block = get_irg_start_block(irg);
829 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
831 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
836 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
839 ir_graph *irg = get_irn_irg(node);
840 ir_node *block = get_nodes_block(node);
841 int offset = get_ia32_am_offs_int(node);
842 int sc_sign = is_ia32_am_sc_sign(node);
843 ir_entity *entity = get_ia32_am_sc(node);
846 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
847 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
851 static int is_am_one(const ir_node *node)
853 int offset = get_ia32_am_offs_int(node);
854 ir_entity *entity = get_ia32_am_sc(node);
856 return offset == 1 && entity == NULL;
859 static int is_am_minus_one(const ir_node *node)
861 int offset = get_ia32_am_offs_int(node);
862 ir_entity *entity = get_ia32_am_sc(node);
864 return offset == -1 && entity == NULL;
868 * Transforms a LEA into an Add or SHL if possible.
870 static void peephole_ia32_Lea(ir_node *node)
872 const arch_env_t *arch_env = cg->arch_env;
873 ir_graph *irg = current_ir_graph;
876 const arch_register_t *base_reg;
877 const arch_register_t *index_reg;
878 const arch_register_t *out_reg;
889 assert(is_ia32_Lea(node));
891 /* we can only do this if are allowed to globber the flags */
892 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
895 base = get_irn_n(node, n_ia32_Lea_base);
896 index = get_irn_n(node, n_ia32_Lea_index);
898 if(is_noreg(cg, base)) {
902 base_reg = arch_get_irn_register(arch_env, base);
904 if(is_noreg(cg, index)) {
908 index_reg = arch_get_irn_register(arch_env, index);
911 if(base == NULL && index == NULL) {
912 /* we shouldn't construct these in the first place... */
914 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
919 out_reg = arch_get_irn_register(arch_env, node);
920 scale = get_ia32_am_scale(node);
921 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
922 /* check if we have immediates values (frame entities should already be
923 * expressed in the offsets) */
924 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
930 /* we can transform leas where the out register is the same as either the
931 * base or index register back to an Add or Shl */
932 if(out_reg == base_reg) {
935 if(!has_immediates) {
936 ir_fprintf(stderr, "Optimisation warning: found lea which is "
941 goto make_add_immediate;
943 if(scale == 0 && !has_immediates) {
948 /* can't create an add */
950 } else if(out_reg == index_reg) {
952 if(has_immediates && scale == 0) {
954 goto make_add_immediate;
955 } else if(!has_immediates && scale > 0) {
957 op2 = create_immediate_from_int(cg, scale);
959 } else if(!has_immediates) {
961 ir_fprintf(stderr, "Optimisation warning: found lea which is "
965 } else if(scale == 0 && !has_immediates) {
970 /* can't create an add */
973 /* can't create an add */
978 if(ia32_cg_config.use_incdec) {
979 if(is_am_one(node)) {
980 dbgi = get_irn_dbg_info(node);
981 block = get_nodes_block(node);
982 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
983 arch_set_irn_register(arch_env, res, out_reg);
986 if(is_am_minus_one(node)) {
987 dbgi = get_irn_dbg_info(node);
988 block = get_nodes_block(node);
989 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
990 arch_set_irn_register(arch_env, res, out_reg);
994 op2 = create_immediate_from_am(cg, node);
997 dbgi = get_irn_dbg_info(node);
998 block = get_nodes_block(node);
999 noreg = ia32_new_NoReg_gp(cg);
1000 nomem = new_NoMem();
1001 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1002 arch_set_irn_register(arch_env, res, out_reg);
1003 set_ia32_commutative(res);
1007 dbgi = get_irn_dbg_info(node);
1008 block = get_nodes_block(node);
1009 noreg = ia32_new_NoReg_gp(cg);
1010 nomem = new_NoMem();
1011 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1012 arch_set_irn_register(arch_env, res, out_reg);
1016 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1018 /* add new ADD/SHL to schedule */
1019 DBG_OPT_LEA2ADD(node, res);
1021 /* exchange the Add and the LEA */
1022 sched_add_before(node, res);
1023 be_peephole_exchange(node, res);
1027 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1029 static void peephole_ia32_Imul_split(ir_node *imul) {
1030 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1031 const arch_register_t *reg;
1032 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
1036 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1037 /* no memory, imm form ignore */
1040 /* we need a free register */
1041 reg = get_free_gp_reg();
1045 /* fine, we can rebuild it */
1046 dbgi = get_irn_dbg_info(imul);
1047 block = get_nodes_block(imul);
1048 irg = current_ir_graph;
1049 base = get_irn_n(imul, n_ia32_IMul_base);
1050 index = get_irn_n(imul, n_ia32_IMul_index);
1051 mem = get_irn_n(imul, n_ia32_IMul_mem);
1052 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1054 /* copy all attributes */
1055 set_irn_pinned(load, get_irn_pinned(imul));
1056 set_ia32_op_type(load, ia32_AddrModeS);
1057 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1059 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1060 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1061 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1062 if (is_ia32_am_sc_sign(imul))
1063 set_ia32_am_sc_sign(load);
1064 if (is_ia32_use_frame(imul))
1065 set_ia32_use_frame(load);
1066 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1068 sched_add_before(imul, load);
1070 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1071 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1073 arch_set_irn_register(arch_env, res, reg);
1074 be_peephole_new_node(res);
1076 set_irn_n(imul, n_ia32_IMul_mem, mem);
1077 noreg = get_irn_n(imul, n_ia32_IMul_left);
1078 set_irn_n(imul, n_ia32_IMul_left, res);
1079 set_ia32_op_type(imul, ia32_Normal);
1083 * Replace xorps r,r and xorpd r,r by pxor r,r
1085 static void peephole_ia32_xZero(ir_node *xor) {
1086 set_irn_op(xor, op_ia32_xPzero);
1090 * Register a peephole optimisation function.
1092 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1093 assert(op->ops.generic == NULL);
1094 op->ops.generic = (op_func)func;
1097 /* Perform peephole-optimizations. */
1098 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1101 arch_env = cg->arch_env;
1103 /* register peephole optimisations */
1104 clear_irp_opcodes_generic_func();
1105 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1106 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1107 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1108 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1109 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1110 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1111 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1112 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1113 if (! ia32_cg_config.use_imul_mem_imm32)
1114 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1115 if (ia32_cg_config.use_pxor)
1116 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1118 be_peephole_opt(cg->birg);
1122 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1123 * all it's Projs are removed as well.
1124 * @param irn The irn to be removed from schedule
1126 static INLINE void try_kill(ir_node *node)
1128 if(get_irn_mode(node) == mode_T) {
1129 const ir_edge_t *edge, *next;
1130 foreach_out_edge_safe(node, edge, next) {
1131 ir_node *proj = get_edge_src_irn(edge);
1136 if(get_irn_n_edges(node) != 0)
1139 if (sched_is_scheduled(node)) {
1146 static void optimize_conv_store(ir_node *node)
1151 ir_mode *store_mode;
1153 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1156 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1157 pred_proj = get_irn_n(node, n_ia32_Store_val);
1158 if(is_Proj(pred_proj)) {
1159 pred = get_Proj_pred(pred_proj);
1163 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1165 if(get_ia32_op_type(pred) != ia32_Normal)
1168 /* the store only stores the lower bits, so we only need the conv
1169 * it it shrinks the mode */
1170 conv_mode = get_ia32_ls_mode(pred);
1171 store_mode = get_ia32_ls_mode(node);
1172 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1175 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1176 if(get_irn_n_edges(pred_proj) == 0) {
1177 kill_node(pred_proj);
1178 if(pred != pred_proj)
1183 static void optimize_load_conv(ir_node *node)
1185 ir_node *pred, *predpred;
1189 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1192 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1193 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1197 predpred = get_Proj_pred(pred);
1198 if(!is_ia32_Load(predpred))
1201 /* the load is sign extending the upper bits, so we only need the conv
1202 * if it shrinks the mode */
1203 load_mode = get_ia32_ls_mode(predpred);
1204 conv_mode = get_ia32_ls_mode(node);
1205 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1208 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1209 /* change the load if it has only 1 user */
1210 if(get_irn_n_edges(pred) == 1) {
1212 if(get_mode_sign(conv_mode)) {
1213 newmode = find_signed_mode(load_mode);
1215 newmode = find_unsigned_mode(load_mode);
1217 assert(newmode != NULL);
1218 set_ia32_ls_mode(predpred, newmode);
1220 /* otherwise we have to keep the conv */
1226 exchange(node, pred);
1229 static void optimize_conv_conv(ir_node *node)
1231 ir_node *pred_proj, *pred, *result_conv;
1232 ir_mode *pred_mode, *conv_mode;
1236 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1239 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1240 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1241 if(is_Proj(pred_proj))
1242 pred = get_Proj_pred(pred_proj);
1246 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1249 /* we know that after a conv, the upper bits are sign extended
1250 * so we only need the 2nd conv if it shrinks the mode */
1251 conv_mode = get_ia32_ls_mode(node);
1252 conv_mode_bits = get_mode_size_bits(conv_mode);
1253 pred_mode = get_ia32_ls_mode(pred);
1254 pred_mode_bits = get_mode_size_bits(pred_mode);
1256 if(conv_mode_bits == pred_mode_bits
1257 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1258 result_conv = pred_proj;
1259 } else if(conv_mode_bits <= pred_mode_bits) {
1260 /* if 2nd conv is smaller then first conv, then we can always take the
1262 if(get_irn_n_edges(pred_proj) == 1) {
1263 result_conv = pred_proj;
1264 set_ia32_ls_mode(pred, conv_mode);
1266 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1267 if (get_mode_size_bits(conv_mode) == 8) {
1268 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1269 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1272 /* we don't want to end up with 2 loads, so we better do nothing */
1273 if(get_irn_mode(pred) == mode_T) {
1277 result_conv = exact_copy(pred);
1278 set_ia32_ls_mode(result_conv, conv_mode);
1280 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1281 if (get_mode_size_bits(conv_mode) == 8) {
1282 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1283 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1287 /* if both convs have the same sign, then we can take the smaller one */
1288 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1289 result_conv = pred_proj;
1291 /* no optimisation possible if smaller conv is sign-extend */
1292 if(mode_is_signed(pred_mode)) {
1295 /* we can take the smaller conv if it is unsigned */
1296 result_conv = pred_proj;
1301 exchange(node, result_conv);
1303 if(get_irn_n_edges(pred_proj) == 0) {
1304 kill_node(pred_proj);
1305 if(pred != pred_proj)
1308 optimize_conv_conv(result_conv);
1311 static void optimize_node(ir_node *node, void *env)
1315 optimize_load_conv(node);
1316 optimize_conv_store(node);
1317 optimize_conv_conv(node);
1321 * Performs conv and address mode optimization.
1323 void ia32_optimize_graph(ia32_code_gen_t *cg)
1325 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1328 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1331 void ia32_init_optimize(void)
1333 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");