2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_common_transform.h"
55 #include "ia32_transform.h"
56 #include "ia32_dbg_stat.h"
57 #include "ia32_util.h"
58 #include "ia32_architecture.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static const arch_env_t *arch_env;
63 static ia32_code_gen_t *cg;
66 * Returns non-zero if the given node produces
69 * @param node the node to check
70 * @param pn if >= 0, the projection number of the used result
72 static int produces_zero_flag(ir_node *node, int pn)
75 const ia32_immediate_attr_t *imm_attr;
77 if (!is_ia32_irn(node))
81 if (pn != pn_ia32_res)
85 switch (get_ia32_irn_opcode(node)) {
103 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
104 assert(n_ia32_Shl_count == n_ia32_Shr_count
105 && n_ia32_Shl_count == n_ia32_Sar_count);
106 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
107 count = get_irn_n(node, n_ia32_ShlD_count);
109 count = get_irn_n(node, n_ia32_Shl_count);
111 /* when shift count is zero the flags are not affected, so we can only
112 * do this for constants != 0 */
113 if (!is_ia32_Immediate(count))
116 imm_attr = get_ia32_immediate_attr_const(count);
117 if (imm_attr->symconst != NULL)
119 if ((imm_attr->offset & 0x1f) == 0)
130 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
132 * @param node the node to change
134 * @return the new mode_T node (if the mode was changed) or node itself
136 static ir_node *turn_into_mode_t(ir_node *node)
141 const arch_register_t *reg;
143 if(get_irn_mode(node) == mode_T)
146 assert(get_irn_mode(node) == mode_Iu);
148 new_node = exact_copy(node);
149 set_irn_mode(new_node, mode_T);
151 block = get_nodes_block(new_node);
152 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
155 reg = arch_get_irn_register(arch_env, node);
156 arch_set_irn_register(arch_env, res_proj, reg);
158 sched_add_before(node, new_node);
159 be_peephole_exchange(node, res_proj);
164 * Replace Cmp(x, 0) by a Test(x, x)
166 static void peephole_ia32_Cmp(ir_node *const node)
169 ia32_immediate_attr_t const *imm;
176 ia32_attr_t const *attr;
180 arch_register_t const *reg;
181 ir_edge_t const *edge;
182 ir_edge_t const *tmp;
184 if (get_ia32_op_type(node) != ia32_Normal)
187 right = get_irn_n(node, n_ia32_Cmp_right);
188 if (!is_ia32_Immediate(right))
191 imm = get_ia32_immediate_attr_const(right);
192 if (imm->symconst != NULL || imm->offset != 0)
195 dbgi = get_irn_dbg_info(node);
196 irg = current_ir_graph;
197 block = get_nodes_block(node);
198 noreg = ia32_new_NoReg_gp(cg);
199 nomem = get_irg_no_mem(irg);
200 op = get_irn_n(node, n_ia32_Cmp_left);
201 attr = get_irn_generic_attr(node);
202 ins_permuted = attr->data.ins_permuted;
203 cmp_unsigned = attr->data.cmp_unsigned;
205 if (is_ia32_Cmp(node)) {
206 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
207 op, op, ins_permuted, cmp_unsigned);
209 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
210 op, op, ins_permuted, cmp_unsigned);
212 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
214 reg = arch_get_irn_register(arch_env, node);
215 arch_set_irn_register(arch_env, test, reg);
217 foreach_out_edge_safe(node, edge, tmp) {
218 ir_node *const user = get_edge_src_irn(edge);
221 exchange(user, test);
224 sched_add_before(node, test);
225 be_peephole_exchange(node, test);
229 * Peephole optimization for Test instructions.
230 * We can remove the Test, if a zero flags was produced which is still
233 static void peephole_ia32_Test(ir_node *node)
235 ir_node *left = get_irn_n(node, n_ia32_Test_left);
236 ir_node *right = get_irn_n(node, n_ia32_Test_right);
242 const ir_edge_t *edge;
244 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
245 && n_ia32_Test_right == n_ia32_Test8Bit_right);
247 /* we need a test for 0 */
251 block = get_nodes_block(node);
252 if(get_nodes_block(left) != block)
256 pn = get_Proj_proj(left);
257 left = get_Proj_pred(left);
260 /* happens rarely, but if it does code will panic' */
261 if (is_ia32_Unknown_GP(left))
264 /* walk schedule up and abort when we find left or some other node destroys
266 schedpoint = sched_prev(node);
267 while(schedpoint != left) {
268 schedpoint = sched_prev(schedpoint);
269 if(arch_irn_is(arch_env, schedpoint, modify_flags))
271 if(schedpoint == block)
272 panic("couldn't find left");
275 /* make sure only Lg/Eq tests are used */
276 foreach_out_edge(node, edge) {
277 ir_node *user = get_edge_src_irn(edge);
278 int pnc = get_ia32_condcode(user);
280 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
285 if(!produces_zero_flag(left, pn))
288 left = turn_into_mode_t(left);
290 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
291 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
293 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
295 assert(get_irn_mode(node) != mode_T);
297 be_peephole_exchange(node, flags_proj);
301 * AMD Athlon works faster when RET is not destination of
302 * conditional jump or directly preceded by other jump instruction.
303 * Can be avoided by placing a Rep prefix before the return.
305 static void peephole_ia32_Return(ir_node *node) {
306 ir_node *block, *irn;
308 if (!ia32_cg_config.use_pad_return)
311 block = get_nodes_block(node);
313 /* check if this return is the first on the block */
314 sched_foreach_reverse_from(node, irn) {
315 switch (get_irn_opcode(irn)) {
317 /* the return node itself, ignore */
320 /* ignore the barrier, no code generated */
323 /* arg, IncSP 0 nodes might occur, ignore these */
324 if (be_get_IncSP_offset(irn) == 0)
334 /* ensure, that the 3 byte return is generated */
335 be_Return_set_emit_pop(node, 1);
338 /* only optimize up to 48 stores behind IncSPs */
339 #define MAXPUSH_OPTIMIZE 48
342 * Tries to create Push's from IncSP, Store combinations.
343 * The Stores are replaced by Push's, the IncSP is modified
344 * (possibly into IncSP 0, but not removed).
346 static void peephole_IncSP_Store_to_push(ir_node *irn)
352 ir_node *stores[MAXPUSH_OPTIMIZE];
357 ir_node *first_push = NULL;
358 ir_edge_t const *edge;
359 ir_edge_t const *next;
361 memset(stores, 0, sizeof(stores));
363 assert(be_is_IncSP(irn));
365 inc_ofs = be_get_IncSP_offset(irn);
370 * We first walk the schedule after the IncSP node as long as we find
371 * suitable Stores that could be transformed to a Push.
372 * We save them into the stores array which is sorted by the frame offset/4
373 * attached to the node
376 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
381 /* it has to be a Store */
382 if (!is_ia32_Store(node))
385 /* it has to use our sp value */
386 if (get_irn_n(node, n_ia32_base) != irn)
388 /* Store has to be attached to NoMem */
389 mem = get_irn_n(node, n_ia32_mem);
393 /* unfortunately we can't support the full AMs possible for push at the
394 * moment. TODO: fix this */
395 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
398 offset = get_ia32_am_offs_int(node);
399 /* we should NEVER access uninitialized stack BELOW the current SP */
402 /* storing at half-slots is bad */
403 if ((offset & 3) != 0)
406 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
408 storeslot = offset >> 2;
410 /* storing into the same slot twice is bad (and shouldn't happen...) */
411 if (stores[storeslot] != NULL)
414 stores[storeslot] = node;
415 if (storeslot > maxslot)
421 for (i = -1; i < maxslot; ++i) {
422 if (stores[i + 1] == NULL)
426 /* walk through the Stores and create Pushs for them */
427 block = get_nodes_block(irn);
428 spmode = get_irn_mode(irn);
430 for (; i >= 0; --i) {
431 const arch_register_t *spreg;
433 ir_node *val, *mem, *mem_proj;
434 ir_node *store = stores[i];
435 ir_node *noreg = ia32_new_NoReg_gp(cg);
437 val = get_irn_n(store, n_ia32_unary_op);
438 mem = get_irn_n(store, n_ia32_mem);
439 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
441 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
443 if (first_push == NULL)
446 sched_add_after(curr_sp, push);
448 /* create stackpointer Proj */
449 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
450 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
452 /* create memory Proj */
453 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
455 /* use the memproj now */
456 be_peephole_exchange(store, mem_proj);
461 foreach_out_edge_safe(irn, edge, next) {
462 ir_node *const src = get_edge_src_irn(edge);
463 int const pos = get_edge_src_pos(edge);
465 if (src == first_push)
468 set_irn_n(src, pos, curr_sp);
471 be_set_IncSP_offset(irn, inc_ofs);
475 * Return true if a mode can be stored in the GP register set
477 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
478 if (mode == mode_fpcw)
480 if (get_mode_size_bits(mode) > 32)
482 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
486 * Tries to create Pops from Load, IncSP combinations.
487 * The Loads are replaced by Pops, the IncSP is modified
488 * (possibly into IncSP 0, but not removed).
490 static void peephole_Load_IncSP_to_pop(ir_node *irn)
492 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
493 int i, maxslot, inc_ofs, ofs;
494 ir_node *node, *pred_sp, *block;
495 ir_node *loads[MAXPUSH_OPTIMIZE];
497 unsigned regmask = 0;
498 unsigned copymask = ~0;
500 memset(loads, 0, sizeof(loads));
501 assert(be_is_IncSP(irn));
503 inc_ofs = -be_get_IncSP_offset(irn);
508 * We first walk the schedule before the IncSP node as long as we find
509 * suitable Loads that could be transformed to a Pop.
510 * We save them into the stores array which is sorted by the frame offset/4
511 * attached to the node
514 pred_sp = be_get_IncSP_pred(irn);
515 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
518 const arch_register_t *sreg, *dreg;
520 /* it has to be a Load */
521 if (!is_ia32_Load(node)) {
522 if (be_is_Copy(node)) {
523 if (!mode_needs_gp_reg(get_irn_mode(node))) {
524 /* not a GP copy, ignore */
527 dreg = arch_get_irn_register(arch_env, node);
528 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
529 if (regmask & copymask & (1 << sreg->index)) {
532 if (regmask & copymask & (1 << dreg->index)) {
535 /* we CAN skip Copies if neither the destination nor the source
536 * is not in our regmask, ie none of our future Pop will overwrite it */
537 regmask |= (1 << dreg->index) | (1 << sreg->index);
538 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
544 /* we can handle only GP loads */
545 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
548 /* it has to use our predecessor sp value */
549 if (get_irn_n(node, n_ia32_base) != pred_sp) {
550 /* it would be ok if this load does not use a Pop result,
551 * but we do not check this */
555 /* should have NO index */
556 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
559 offset = get_ia32_am_offs_int(node);
560 /* we should NEVER access uninitialized stack BELOW the current SP */
563 /* storing at half-slots is bad */
564 if ((offset & 3) != 0)
567 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
569 /* ignore those outside the possible windows */
570 if (offset > inc_ofs - 4)
572 loadslot = offset >> 2;
574 /* loading from the same slot twice is bad (and shouldn't happen...) */
575 if (loads[loadslot] != NULL)
578 dreg = arch_get_irn_register(arch_env, node);
579 if (regmask & (1 << dreg->index)) {
580 /* this register is already used */
583 regmask |= 1 << dreg->index;
585 loads[loadslot] = node;
586 if (loadslot > maxslot)
593 /* find the first slot */
594 for (i = maxslot; i >= 0; --i) {
595 ir_node *load = loads[i];
601 ofs = inc_ofs - (maxslot + 1) * 4;
604 /* create a new IncSP if needed */
605 block = get_nodes_block(irn);
608 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
609 sched_add_before(irn, pred_sp);
612 /* walk through the Loads and create Pops for them */
613 for (++i; i <= maxslot; ++i) {
614 ir_node *load = loads[i];
616 const ir_edge_t *edge, *tmp;
617 const arch_register_t *reg;
619 mem = get_irn_n(load, n_ia32_mem);
620 reg = arch_get_irn_register(arch_env, load);
622 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
623 arch_set_irn_register(arch_env, pop, reg);
625 /* create stackpointer Proj */
626 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
627 arch_set_irn_register(arch_env, pred_sp, esp);
629 sched_add_before(irn, pop);
632 foreach_out_edge_safe(load, edge, tmp) {
633 ir_node *proj = get_edge_src_irn(edge);
635 set_Proj_pred(proj, pop);
638 /* we can remove the Load now */
643 be_set_IncSP_offset(irn, -ofs);
644 be_set_IncSP_pred(irn, pred_sp);
649 * Find a free GP register if possible, else return NULL.
651 static const arch_register_t *get_free_gp_reg(void)
655 for(i = 0; i < N_ia32_gp_REGS; ++i) {
656 const arch_register_t *reg = &ia32_gp_regs[i];
657 if(arch_register_type_is(reg, ignore))
660 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
661 return &ia32_gp_regs[i];
668 * Creates a Pop instruction before the given schedule point.
670 * @param dbgi debug info
671 * @param irg the graph
672 * @param block the block
673 * @param stack the previous stack value
674 * @param schedpoint the new node is added before this node
675 * @param reg the register to pop
677 * @return the new stack value
679 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
680 ir_node *stack, ir_node *schedpoint,
681 const arch_register_t *reg)
683 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
689 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
691 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
692 arch_set_irn_register(arch_env, stack, esp);
693 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
694 arch_set_irn_register(arch_env, val, reg);
696 sched_add_before(schedpoint, pop);
699 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
700 sched_add_before(schedpoint, keep);
706 * Creates a Push instruction before the given schedule point.
708 * @param dbgi debug info
709 * @param irg the graph
710 * @param block the block
711 * @param stack the previous stack value
712 * @param schedpoint the new node is added before this node
713 * @param reg the register to pop
715 * @return the new stack value
717 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
718 ir_node *stack, ir_node *schedpoint)
720 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
722 ir_node *val = ia32_new_Unknown_gp(cg);
723 ir_node *noreg = ia32_new_NoReg_gp(cg);
724 ir_node *nomem = get_irg_no_mem(irg);
725 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
726 sched_add_before(schedpoint, push);
728 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
729 arch_set_irn_register(arch_env, stack, esp);
735 * Optimize an IncSp by replacing it with Push/Pop.
737 static void peephole_be_IncSP(ir_node *node)
739 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
740 const arch_register_t *reg;
741 ir_graph *irg = current_ir_graph;
747 /* first optimize incsp->incsp combinations */
748 node = be_peephole_IncSP_IncSP(node);
750 /* transform IncSP->Store combinations to Push where possible */
751 peephole_IncSP_Store_to_push(node);
753 /* transform Load->IncSP combinations to Pop where possible */
754 peephole_Load_IncSP_to_pop(node);
756 if (arch_get_irn_register(arch_env, node) != esp)
759 /* replace IncSP -4 by Pop freereg when possible */
760 offset = be_get_IncSP_offset(node);
761 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
762 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
763 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
764 (offset != +8 || ia32_cg_config.use_sub_esp_8))
768 /* we need a free register for pop */
769 reg = get_free_gp_reg();
773 dbgi = get_irn_dbg_info(node);
774 block = get_nodes_block(node);
775 stack = be_get_IncSP_pred(node);
777 stack = create_pop(dbgi, irg, block, stack, node, reg);
780 stack = create_pop(dbgi, irg, block, stack, node, reg);
783 dbgi = get_irn_dbg_info(node);
784 block = get_nodes_block(node);
785 stack = be_get_IncSP_pred(node);
786 stack = create_push(dbgi, irg, block, stack, node);
789 stack = create_push(dbgi, irg, block, stack, node);
793 be_peephole_exchange(node, stack);
797 * Peephole optimisation for ia32_Const's
799 static void peephole_ia32_Const(ir_node *node)
801 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
802 const arch_register_t *reg;
803 ir_graph *irg = current_ir_graph;
810 /* try to transform a mov 0, reg to xor reg reg */
811 if (attr->offset != 0 || attr->symconst != NULL)
813 if (ia32_cg_config.use_mov_0)
815 /* xor destroys the flags, so no-one must be using them */
816 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
819 reg = arch_get_irn_register(arch_env, node);
820 assert(be_peephole_get_reg_value(reg) == NULL);
822 /* create xor(produceval, produceval) */
823 block = get_nodes_block(node);
824 dbgi = get_irn_dbg_info(node);
825 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
826 arch_set_irn_register(arch_env, produceval, reg);
828 noreg = ia32_new_NoReg_gp(cg);
829 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
830 produceval, produceval);
831 arch_set_irn_register(arch_env, xor, reg);
833 sched_add_before(node, produceval);
834 sched_add_before(node, xor);
836 be_peephole_exchange(node, xor);
839 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
841 return node == cg->noreg_gp;
844 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
846 ir_graph *irg = current_ir_graph;
847 ir_node *start_block = get_irg_start_block(irg);
848 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
850 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
855 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
858 ir_graph *irg = get_irn_irg(node);
859 ir_node *block = get_nodes_block(node);
860 int offset = get_ia32_am_offs_int(node);
861 int sc_sign = is_ia32_am_sc_sign(node);
862 ir_entity *entity = get_ia32_am_sc(node);
865 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
866 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
870 static int is_am_one(const ir_node *node)
872 int offset = get_ia32_am_offs_int(node);
873 ir_entity *entity = get_ia32_am_sc(node);
875 return offset == 1 && entity == NULL;
878 static int is_am_minus_one(const ir_node *node)
880 int offset = get_ia32_am_offs_int(node);
881 ir_entity *entity = get_ia32_am_sc(node);
883 return offset == -1 && entity == NULL;
887 * Transforms a LEA into an Add or SHL if possible.
889 static void peephole_ia32_Lea(ir_node *node)
891 const arch_env_t *arch_env = cg->arch_env;
892 ir_graph *irg = current_ir_graph;
895 const arch_register_t *base_reg;
896 const arch_register_t *index_reg;
897 const arch_register_t *out_reg;
908 assert(is_ia32_Lea(node));
910 /* we can only do this if are allowed to globber the flags */
911 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
914 base = get_irn_n(node, n_ia32_Lea_base);
915 index = get_irn_n(node, n_ia32_Lea_index);
917 if(is_noreg(cg, base)) {
921 base_reg = arch_get_irn_register(arch_env, base);
923 if(is_noreg(cg, index)) {
927 index_reg = arch_get_irn_register(arch_env, index);
930 if(base == NULL && index == NULL) {
931 /* we shouldn't construct these in the first place... */
933 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
938 out_reg = arch_get_irn_register(arch_env, node);
939 scale = get_ia32_am_scale(node);
940 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
941 /* check if we have immediates values (frame entities should already be
942 * expressed in the offsets) */
943 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
949 /* we can transform leas where the out register is the same as either the
950 * base or index register back to an Add or Shl */
951 if(out_reg == base_reg) {
954 if(!has_immediates) {
955 ir_fprintf(stderr, "Optimisation warning: found lea which is "
960 goto make_add_immediate;
962 if(scale == 0 && !has_immediates) {
967 /* can't create an add */
969 } else if(out_reg == index_reg) {
971 if(has_immediates && scale == 0) {
973 goto make_add_immediate;
974 } else if(!has_immediates && scale > 0) {
976 op2 = create_immediate_from_int(cg, scale);
978 } else if(!has_immediates) {
980 ir_fprintf(stderr, "Optimisation warning: found lea which is "
984 } else if(scale == 0 && !has_immediates) {
989 /* can't create an add */
992 /* can't create an add */
997 if(ia32_cg_config.use_incdec) {
998 if(is_am_one(node)) {
999 dbgi = get_irn_dbg_info(node);
1000 block = get_nodes_block(node);
1001 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
1002 arch_set_irn_register(arch_env, res, out_reg);
1005 if(is_am_minus_one(node)) {
1006 dbgi = get_irn_dbg_info(node);
1007 block = get_nodes_block(node);
1008 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
1009 arch_set_irn_register(arch_env, res, out_reg);
1013 op2 = create_immediate_from_am(cg, node);
1016 dbgi = get_irn_dbg_info(node);
1017 block = get_nodes_block(node);
1018 noreg = ia32_new_NoReg_gp(cg);
1019 nomem = new_NoMem();
1020 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1021 arch_set_irn_register(arch_env, res, out_reg);
1022 set_ia32_commutative(res);
1026 dbgi = get_irn_dbg_info(node);
1027 block = get_nodes_block(node);
1028 noreg = ia32_new_NoReg_gp(cg);
1029 nomem = new_NoMem();
1030 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1031 arch_set_irn_register(arch_env, res, out_reg);
1035 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1037 /* add new ADD/SHL to schedule */
1038 DBG_OPT_LEA2ADD(node, res);
1040 /* exchange the Add and the LEA */
1041 sched_add_before(node, res);
1042 be_peephole_exchange(node, res);
1046 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1048 static void peephole_ia32_Imul_split(ir_node *imul) {
1049 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1050 const arch_register_t *reg;
1051 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
1055 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1056 /* no memory, imm form ignore */
1059 /* we need a free register */
1060 reg = get_free_gp_reg();
1064 /* fine, we can rebuild it */
1065 dbgi = get_irn_dbg_info(imul);
1066 block = get_nodes_block(imul);
1067 irg = current_ir_graph;
1068 base = get_irn_n(imul, n_ia32_IMul_base);
1069 index = get_irn_n(imul, n_ia32_IMul_index);
1070 mem = get_irn_n(imul, n_ia32_IMul_mem);
1071 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1073 /* copy all attributes */
1074 set_irn_pinned(load, get_irn_pinned(imul));
1075 set_ia32_op_type(load, ia32_AddrModeS);
1076 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1078 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1079 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1080 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1081 if (is_ia32_am_sc_sign(imul))
1082 set_ia32_am_sc_sign(load);
1083 if (is_ia32_use_frame(imul))
1084 set_ia32_use_frame(load);
1085 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1087 sched_add_before(imul, load);
1089 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1090 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1092 arch_set_irn_register(arch_env, res, reg);
1093 be_peephole_new_node(res);
1095 set_irn_n(imul, n_ia32_IMul_mem, mem);
1096 noreg = get_irn_n(imul, n_ia32_IMul_left);
1097 set_irn_n(imul, n_ia32_IMul_left, res);
1098 set_ia32_op_type(imul, ia32_Normal);
1102 * Replace xorps r,r and xorpd r,r by pxor r,r
1104 static void peephole_ia32_xZero(ir_node *xor) {
1105 set_irn_op(xor, op_ia32_xPzero);
1109 * Register a peephole optimisation function.
1111 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1112 assert(op->ops.generic == NULL);
1113 op->ops.generic = (op_func)func;
1116 /* Perform peephole-optimizations. */
1117 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1120 arch_env = cg->arch_env;
1122 /* register peephole optimisations */
1123 clear_irp_opcodes_generic_func();
1124 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1125 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1126 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1127 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1128 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1129 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1130 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1131 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1132 if (! ia32_cg_config.use_imul_mem_imm32)
1133 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1134 if (ia32_cg_config.use_pxor)
1135 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1137 be_peephole_opt(cg->birg);
1141 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1142 * all it's Projs are removed as well.
1143 * @param irn The irn to be removed from schedule
1145 static INLINE void try_kill(ir_node *node)
1147 if(get_irn_mode(node) == mode_T) {
1148 const ir_edge_t *edge, *next;
1149 foreach_out_edge_safe(node, edge, next) {
1150 ir_node *proj = get_edge_src_irn(edge);
1155 if(get_irn_n_edges(node) != 0)
1158 if (sched_is_scheduled(node)) {
1165 static void optimize_conv_store(ir_node *node)
1170 ir_mode *store_mode;
1172 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1175 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1176 pred_proj = get_irn_n(node, n_ia32_Store_val);
1177 if(is_Proj(pred_proj)) {
1178 pred = get_Proj_pred(pred_proj);
1182 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1184 if(get_ia32_op_type(pred) != ia32_Normal)
1187 /* the store only stores the lower bits, so we only need the conv
1188 * it it shrinks the mode */
1189 conv_mode = get_ia32_ls_mode(pred);
1190 store_mode = get_ia32_ls_mode(node);
1191 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1194 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1195 if(get_irn_n_edges(pred_proj) == 0) {
1196 kill_node(pred_proj);
1197 if(pred != pred_proj)
1202 static void optimize_load_conv(ir_node *node)
1204 ir_node *pred, *predpred;
1208 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1211 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1212 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1216 predpred = get_Proj_pred(pred);
1217 if(!is_ia32_Load(predpred))
1220 /* the load is sign extending the upper bits, so we only need the conv
1221 * if it shrinks the mode */
1222 load_mode = get_ia32_ls_mode(predpred);
1223 conv_mode = get_ia32_ls_mode(node);
1224 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1227 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1228 /* change the load if it has only 1 user */
1229 if(get_irn_n_edges(pred) == 1) {
1231 if(get_mode_sign(conv_mode)) {
1232 newmode = find_signed_mode(load_mode);
1234 newmode = find_unsigned_mode(load_mode);
1236 assert(newmode != NULL);
1237 set_ia32_ls_mode(predpred, newmode);
1239 /* otherwise we have to keep the conv */
1245 exchange(node, pred);
1248 static void optimize_conv_conv(ir_node *node)
1250 ir_node *pred_proj, *pred, *result_conv;
1251 ir_mode *pred_mode, *conv_mode;
1255 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1258 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1259 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1260 if(is_Proj(pred_proj))
1261 pred = get_Proj_pred(pred_proj);
1265 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1268 /* we know that after a conv, the upper bits are sign extended
1269 * so we only need the 2nd conv if it shrinks the mode */
1270 conv_mode = get_ia32_ls_mode(node);
1271 conv_mode_bits = get_mode_size_bits(conv_mode);
1272 pred_mode = get_ia32_ls_mode(pred);
1273 pred_mode_bits = get_mode_size_bits(pred_mode);
1275 if(conv_mode_bits == pred_mode_bits
1276 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1277 result_conv = pred_proj;
1278 } else if(conv_mode_bits <= pred_mode_bits) {
1279 /* if 2nd conv is smaller then first conv, then we can always take the
1281 if(get_irn_n_edges(pred_proj) == 1) {
1282 result_conv = pred_proj;
1283 set_ia32_ls_mode(pred, conv_mode);
1285 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1286 if (get_mode_size_bits(conv_mode) == 8) {
1287 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1288 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1291 /* we don't want to end up with 2 loads, so we better do nothing */
1292 if(get_irn_mode(pred) == mode_T) {
1296 result_conv = exact_copy(pred);
1297 set_ia32_ls_mode(result_conv, conv_mode);
1299 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1300 if (get_mode_size_bits(conv_mode) == 8) {
1301 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1302 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1306 /* if both convs have the same sign, then we can take the smaller one */
1307 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1308 result_conv = pred_proj;
1310 /* no optimisation possible if smaller conv is sign-extend */
1311 if(mode_is_signed(pred_mode)) {
1314 /* we can take the smaller conv if it is unsigned */
1315 result_conv = pred_proj;
1320 exchange(node, result_conv);
1322 if(get_irn_n_edges(pred_proj) == 0) {
1323 kill_node(pred_proj);
1324 if(pred != pred_proj)
1327 optimize_conv_conv(result_conv);
1330 static void optimize_node(ir_node *node, void *env)
1334 optimize_load_conv(node);
1335 optimize_conv_store(node);
1336 optimize_conv_conv(node);
1340 * Performs conv and address mode optimization.
1342 void ia32_optimize_graph(ia32_code_gen_t *cg)
1344 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1347 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1350 void ia32_init_optimize(void)
1352 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");