2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
31 #include "firm_types.h"
45 #include "bepeephole.h"
47 #include "ia32_new_nodes.h"
48 #include "ia32_optimize.h"
49 #include "bearch_ia32_t.h"
50 #include "gen_ia32_regalloc_if.h"
51 #include "ia32_common_transform.h"
52 #include "ia32_transform.h"
53 #include "ia32_dbg_stat.h"
54 #include "ia32_architecture.h"
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 static void copy_mark(const ir_node *old, ir_node *newn)
60 if (is_ia32_is_reload(old))
61 set_ia32_is_reload(newn);
62 if (is_ia32_is_spill(old))
63 set_ia32_is_spill(newn);
64 if (is_ia32_is_remat(old))
65 set_ia32_is_remat(newn);
68 typedef enum produces_flag_t {
71 produces_zero_in_carry
75 * Return which usable flag the given node produces about the result.
76 * That is zero (ZF) and sign(SF).
77 * We do not check for carry (CF) or overflow (OF).
79 * @param node the node to check
80 * @param pn the projection number of the used result
82 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
85 const ia32_immediate_attr_t *imm_attr;
87 if (!is_ia32_irn(node))
88 return produces_no_flag;
90 switch (get_ia32_irn_opcode(node)) {
105 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
106 count = get_irn_n(node, n_ia32_ShlD_count);
107 goto check_shift_amount;
112 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
113 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
114 count = get_irn_n(node, n_ia32_Shl_count);
116 /* when shift count is zero the flags are not affected, so we can only
117 * do this for constants != 0 */
118 if (!is_ia32_Immediate(count))
119 return produces_no_flag;
121 imm_attr = get_ia32_immediate_attr_const(count);
122 if (imm_attr->symconst != NULL)
123 return produces_no_flag;
124 if ((imm_attr->offset & 0x1f) == 0)
125 return produces_no_flag;
129 return pn == pn_ia32_Mul_res_high ?
130 produces_zero_in_carry : produces_no_flag;
133 return produces_no_flag;
136 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
140 * Replace Cmp(x, 0) by a Test(x, x)
142 static void peephole_ia32_Cmp(ir_node *const node)
146 ia32_immediate_attr_t const *imm;
152 ia32_attr_t const *attr;
155 arch_register_t const *reg;
156 ir_edge_t const *edge;
157 ir_edge_t const *tmp;
159 if (get_ia32_op_type(node) != ia32_Normal)
162 right = get_irn_n(node, n_ia32_Cmp_right);
163 if (!is_ia32_Immediate(right))
166 imm = get_ia32_immediate_attr_const(right);
167 if (imm->symconst != NULL || imm->offset != 0)
170 dbgi = get_irn_dbg_info(node);
171 irg = get_irn_irg(node);
172 block = get_nodes_block(node);
173 noreg = ia32_new_NoReg_gp(irg);
174 nomem = get_irg_no_mem(current_ir_graph);
175 op = get_irn_n(node, n_ia32_Cmp_left);
176 attr = get_ia32_attr(node);
177 ins_permuted = attr->data.ins_permuted;
179 if (is_ia32_Cmp(node)) {
180 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
181 op, op, ins_permuted);
183 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
184 op, op, ins_permuted);
186 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
188 reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
189 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
191 foreach_out_edge_safe(node, edge, tmp) {
192 ir_node *const user = get_edge_src_irn(edge);
195 exchange(user, test);
198 sched_add_before(node, test);
199 copy_mark(node, test);
200 be_peephole_exchange(node, test);
204 * Peephole optimization for Test instructions.
205 * - Remove the Test, if an appropriate flag was produced which is still live
206 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
208 static void peephole_ia32_Test(ir_node *node)
210 ir_node *left = get_irn_n(node, n_ia32_Test_left);
211 ir_node *right = get_irn_n(node, n_ia32_Test_right);
213 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
214 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
216 if (left == right) { /* we need a test for 0 */
217 ir_node *block = get_nodes_block(node);
218 int pn = pn_ia32_res;
224 const ir_edge_t *edge;
225 produces_flag_t produced;
227 if (get_nodes_block(left) != block)
231 pn = get_Proj_proj(op);
232 op = get_Proj_pred(op);
235 /* walk schedule up and abort when we find left or some other node
236 * destroys the flags */
239 schedpoint = sched_prev(schedpoint);
240 if (schedpoint == op)
242 if (arch_irn_is(schedpoint, modify_flags))
244 if (schedpoint == block)
245 panic("couldn't find left");
248 produced = check_produces_zero_sign(op, pn);
249 if (produced == produces_no_flag)
252 /* make sure users only look at the sign/zero flag */
253 foreach_out_edge(node, edge) {
254 ir_node *user = get_edge_src_irn(edge);
255 ia32_condition_code_t cc = get_ia32_condcode(user);
257 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
259 if (produced == produces_zero_sign
260 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
266 op_mode = get_ia32_ls_mode(op);
268 op_mode = get_irn_mode(op);
270 /* Make sure we operate on the same bit size */
271 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
274 if (produced == produces_zero_in_carry) {
275 /* patch users to look at the carry instead of the zero flag */
276 foreach_out_edge(node, edge) {
277 ir_node *user = get_edge_src_irn(edge);
278 ia32_condition_code_t cc = get_ia32_condcode(user);
281 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
282 case ia32_cc_not_equal: cc = ia32_cc_below; break;
283 default: panic("unexpected pn");
285 set_ia32_condcode(user, cc);
289 if (get_irn_mode(op) != mode_T) {
290 set_irn_mode(op, mode_T);
292 /* If there are other users, reroute them to result proj */
293 if (get_irn_n_edges(op) != 2) {
294 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
296 edges_reroute(op, res);
297 /* Reattach the result proj to left */
298 set_Proj_pred(res, op);
301 if (get_irn_n_edges(left) == 2)
305 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
306 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
307 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
309 assert(get_irn_mode(node) != mode_T);
311 be_peephole_exchange(node, flags_proj);
312 } else if (is_ia32_Immediate(right)) {
313 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
316 /* A test with a symconst is rather strange, but better safe than sorry */
317 if (imm->symconst != NULL)
320 offset = imm->offset;
321 if (get_ia32_op_type(node) == ia32_AddrModeS) {
322 ia32_attr_t *const attr = get_ia32_attr(node);
324 if ((offset & 0xFFFFFF00) == 0) {
325 /* attr->am_offs += 0; */
326 } else if ((offset & 0xFFFF00FF) == 0) {
327 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8);
328 set_irn_n(node, n_ia32_Test_right, imm_node);
330 } else if ((offset & 0xFF00FFFF) == 0) {
331 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16);
332 set_irn_n(node, n_ia32_Test_right, imm_node);
334 } else if ((offset & 0x00FFFFFF) == 0) {
335 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24);
336 set_irn_n(node, n_ia32_Test_right, imm_node);
341 } else if (offset < 256) {
342 arch_register_t const* const reg = arch_get_irn_register(left);
344 if (reg != &ia32_registers[REG_EAX] &&
345 reg != &ia32_registers[REG_EBX] &&
346 reg != &ia32_registers[REG_ECX] &&
347 reg != &ia32_registers[REG_EDX]) {
354 /* Technically we should build a Test8Bit because of the register
355 * constraints, but nobody changes registers at this point anymore. */
356 set_ia32_ls_mode(node, mode_Bu);
361 * AMD Athlon works faster when RET is not destination of
362 * conditional jump or directly preceded by other jump instruction.
363 * Can be avoided by placing a Rep prefix before the return.
365 static void peephole_ia32_Return(ir_node *node)
369 if (!ia32_cg_config.use_pad_return)
372 /* check if this return is the first on the block */
373 sched_foreach_reverse_from(node, irn) {
374 switch (get_irn_opcode(irn)) {
376 /* the return node itself, ignore */
380 /* ignore no code generated */
383 /* arg, IncSP 0 nodes might occur, ignore these */
384 if (be_get_IncSP_offset(irn) == 0)
394 /* ensure, that the 3 byte return is generated */
395 be_Return_set_emit_pop(node, 1);
398 /* only optimize up to 48 stores behind IncSPs */
399 #define MAXPUSH_OPTIMIZE 48
402 * Tries to create Push's from IncSP, Store combinations.
403 * The Stores are replaced by Push's, the IncSP is modified
404 * (possibly into IncSP 0, but not removed).
406 static void peephole_IncSP_Store_to_push(ir_node *irn)
412 ir_node *stores[MAXPUSH_OPTIMIZE];
417 ir_node *first_push = NULL;
418 ir_edge_t const *edge;
419 ir_edge_t const *next;
421 memset(stores, 0, sizeof(stores));
423 assert(be_is_IncSP(irn));
425 inc_ofs = be_get_IncSP_offset(irn);
430 * We first walk the schedule after the IncSP node as long as we find
431 * suitable Stores that could be transformed to a Push.
432 * We save them into the stores array which is sorted by the frame offset/4
433 * attached to the node
436 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
441 /* it has to be a Store */
442 if (!is_ia32_Store(node))
445 /* it has to use our sp value */
446 if (get_irn_n(node, n_ia32_base) != irn)
448 /* Store has to be attached to NoMem */
449 mem = get_irn_n(node, n_ia32_mem);
453 /* unfortunately we can't support the full AMs possible for push at the
454 * moment. TODO: fix this */
455 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
458 offset = get_ia32_am_offs_int(node);
459 /* we should NEVER access uninitialized stack BELOW the current SP */
462 /* storing at half-slots is bad */
463 if ((offset & 3) != 0)
466 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
468 storeslot = offset >> 2;
470 /* storing into the same slot twice is bad (and shouldn't happen...) */
471 if (stores[storeslot] != NULL)
474 stores[storeslot] = node;
475 if (storeslot > maxslot)
481 for (i = -1; i < maxslot; ++i) {
482 if (stores[i + 1] == NULL)
486 /* walk through the Stores and create Pushs for them */
487 block = get_nodes_block(irn);
488 spmode = get_irn_mode(irn);
489 irg = get_irn_irg(irn);
490 for (; i >= 0; --i) {
491 const arch_register_t *spreg;
493 ir_node *val, *mem, *mem_proj;
494 ir_node *store = stores[i];
495 ir_node *noreg = ia32_new_NoReg_gp(irg);
497 val = get_irn_n(store, n_ia32_unary_op);
498 mem = get_irn_n(store, n_ia32_mem);
499 spreg = arch_get_irn_register(curr_sp);
501 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
503 copy_mark(store, push);
505 if (first_push == NULL)
508 sched_add_after(skip_Proj(curr_sp), push);
510 /* create stackpointer Proj */
511 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
512 arch_set_irn_register(curr_sp, spreg);
514 /* create memory Proj */
515 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
517 /* rewire Store Projs */
518 foreach_out_edge_safe(store, edge, next) {
519 ir_node *proj = get_edge_src_irn(edge);
522 switch (get_Proj_proj(proj)) {
523 case pn_ia32_Store_M:
524 exchange(proj, mem_proj);
527 panic("unexpected Proj on Store->IncSp");
531 /* use the memproj now */
532 be_peephole_exchange(store, push);
537 foreach_out_edge_safe(irn, edge, next) {
538 ir_node *const src = get_edge_src_irn(edge);
539 int const pos = get_edge_src_pos(edge);
541 if (src == first_push)
544 set_irn_n(src, pos, curr_sp);
547 be_set_IncSP_offset(irn, inc_ofs);
552 * Creates a Push instruction before the given schedule point.
554 * @param dbgi debug info
555 * @param block the block
556 * @param stack the previous stack value
557 * @param schedpoint the new node is added before this node
558 * @param reg the register to pop
560 * @return the new stack value
562 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
563 ir_node *stack, ir_node *schedpoint)
565 const arch_register_t *esp = &ia32_registers[REG_ESP];
567 ir_node *val = ia32_new_NoReg_gp(cg);
568 ir_node *noreg = ia32_new_NoReg_gp(cg);
569 ir_graph *irg = get_irn_irg(block);
570 ir_node *nomem = get_irg_no_mem(irg);
571 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
572 sched_add_before(schedpoint, push);
574 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
575 arch_set_irn_register(stack, esp);
580 static void peephole_store_incsp(ir_node *store)
591 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
592 if (!be_is_IncSP(am_base)
593 || get_nodes_block(am_base) != get_nodes_block(store))
595 mem = get_irn_n(store, n_ia32_Store_mem);
596 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
600 int incsp_offset = be_get_IncSP_offset(am_base);
601 if (incsp_offset <= 0)
604 /* we have to be at offset 0 */
605 int my_offset = get_ia32_am_offs_int(store);
606 if (my_offset != 0) {
607 /* TODO here: find out whether there is a store with offset 0 before
608 * us and whether we can move it down to our place */
611 ir_mode *ls_mode = get_ia32_ls_mode(store);
612 int my_store_size = get_mode_size_bytes(ls_mode);
614 if (my_offset + my_store_size > incsp_offset)
617 /* correctness checking:
618 - noone else must write to that stackslot
619 (because after translation incsp won't allocate it anymore)
621 sched_foreach_reverse_from(store, node) {
627 /* make sure noone else can use the space on the stack */
628 arity = get_irn_arity(node);
629 for (i = 0; i < arity; ++i) {
630 ir_node *pred = get_irn_n(node, i);
634 if (i == n_ia32_base &&
635 (get_ia32_op_type(node) == ia32_AddrModeS
636 || get_ia32_op_type(node) == ia32_AddrModeD)) {
637 int node_offset = get_ia32_am_offs_int(node);
638 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
639 int node_size = get_mode_size_bytes(node_ls_mode);
640 /* overlapping with our position? abort */
641 if (node_offset < my_offset + my_store_size
642 && node_offset + node_size >= my_offset)
644 /* otherwise it's fine */
648 /* strange use of esp: abort */
653 /* all ok, change to push */
654 dbgi = get_irn_dbg_info(store);
655 block = get_nodes_block(store);
656 noreg = ia32_new_NoReg_gp(cg);
657 val = get_irn_n(store, n_ia32_Store_val);
659 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
661 create_push(dbgi, current_ir_graph, block, am_base, store);
666 * Return true if a mode can be stored in the GP register set
668 static inline int mode_needs_gp_reg(ir_mode *mode)
670 if (mode == ia32_mode_fpcw)
672 if (get_mode_size_bits(mode) > 32)
674 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
678 * Tries to create Pops from Load, IncSP combinations.
679 * The Loads are replaced by Pops, the IncSP is modified
680 * (possibly into IncSP 0, but not removed).
682 static void peephole_Load_IncSP_to_pop(ir_node *irn)
684 const arch_register_t *esp = &ia32_registers[REG_ESP];
685 int i, maxslot, inc_ofs, ofs;
686 ir_node *node, *pred_sp, *block;
687 ir_node *loads[MAXPUSH_OPTIMIZE];
688 unsigned regmask = 0;
689 unsigned copymask = ~0;
691 memset(loads, 0, sizeof(loads));
692 assert(be_is_IncSP(irn));
694 inc_ofs = -be_get_IncSP_offset(irn);
699 * We first walk the schedule before the IncSP node as long as we find
700 * suitable Loads that could be transformed to a Pop.
701 * We save them into the stores array which is sorted by the frame offset/4
702 * attached to the node
705 pred_sp = be_get_IncSP_pred(irn);
706 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
709 const arch_register_t *sreg, *dreg;
711 /* it has to be a Load */
712 if (!is_ia32_Load(node)) {
713 if (be_is_Copy(node)) {
714 if (!mode_needs_gp_reg(get_irn_mode(node))) {
715 /* not a GP copy, ignore */
718 dreg = arch_get_irn_register(node);
719 sreg = arch_get_irn_register(be_get_Copy_op(node));
720 if (regmask & copymask & (1 << sreg->index)) {
723 if (regmask & copymask & (1 << dreg->index)) {
726 /* we CAN skip Copies if neither the destination nor the source
727 * is not in our regmask, ie none of our future Pop will overwrite it */
728 regmask |= (1 << dreg->index) | (1 << sreg->index);
729 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
735 /* we can handle only GP loads */
736 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
739 /* it has to use our predecessor sp value */
740 if (get_irn_n(node, n_ia32_base) != pred_sp) {
741 /* it would be ok if this load does not use a Pop result,
742 * but we do not check this */
746 /* should have NO index */
747 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
750 offset = get_ia32_am_offs_int(node);
751 /* we should NEVER access uninitialized stack BELOW the current SP */
754 /* storing at half-slots is bad */
755 if ((offset & 3) != 0)
758 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
760 /* ignore those outside the possible windows */
761 if (offset > inc_ofs - 4)
763 loadslot = offset >> 2;
765 /* loading from the same slot twice is bad (and shouldn't happen...) */
766 if (loads[loadslot] != NULL)
769 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
770 if (regmask & (1 << dreg->index)) {
771 /* this register is already used */
774 regmask |= 1 << dreg->index;
776 loads[loadslot] = node;
777 if (loadslot > maxslot)
784 /* find the first slot */
785 for (i = maxslot; i >= 0; --i) {
786 ir_node *load = loads[i];
792 ofs = inc_ofs - (maxslot + 1) * 4;
795 /* create a new IncSP if needed */
796 block = get_nodes_block(irn);
798 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
799 sched_add_before(irn, pred_sp);
802 /* walk through the Loads and create Pops for them */
803 for (++i; i <= maxslot; ++i) {
804 ir_node *load = loads[i];
806 const ir_edge_t *edge, *tmp;
807 const arch_register_t *reg;
809 mem = get_irn_n(load, n_ia32_mem);
810 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
812 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
813 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
815 copy_mark(load, pop);
817 /* create stackpointer Proj */
818 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
819 arch_set_irn_register(pred_sp, esp);
821 sched_add_before(irn, pop);
824 foreach_out_edge_safe(load, edge, tmp) {
825 ir_node *proj = get_edge_src_irn(edge);
827 set_Proj_pred(proj, pop);
830 /* we can remove the Load now */
835 be_set_IncSP_offset(irn, -ofs);
836 be_set_IncSP_pred(irn, pred_sp);
841 * Find a free GP register if possible, else return NULL.
843 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
845 be_irg_t *birg = be_birg_from_irg(irg);
848 for (i = 0; i < N_ia32_gp_REGS; ++i) {
849 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
850 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
853 if (be_peephole_get_value(reg->global_index) == NULL)
861 * Creates a Pop instruction before the given schedule point.
863 * @param dbgi debug info
864 * @param block the block
865 * @param stack the previous stack value
866 * @param schedpoint the new node is added before this node
867 * @param reg the register to pop
869 * @return the new stack value
871 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
872 ir_node *stack, ir_node *schedpoint,
873 const arch_register_t *reg)
875 const arch_register_t *esp = &ia32_registers[REG_ESP];
876 ir_graph *irg = get_irn_irg(block);
882 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
884 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
885 arch_set_irn_register(stack, esp);
886 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
887 arch_set_irn_register(val, reg);
889 sched_add_before(schedpoint, pop);
892 keep = be_new_Keep(block, 1, in);
893 sched_add_before(schedpoint, keep);
899 * Optimize an IncSp by replacing it with Push/Pop.
901 static void peephole_be_IncSP(ir_node *node)
903 const arch_register_t *esp = &ia32_registers[REG_ESP];
904 const arch_register_t *reg;
910 /* first optimize incsp->incsp combinations */
911 node = be_peephole_IncSP_IncSP(node);
913 /* transform IncSP->Store combinations to Push where possible */
914 peephole_IncSP_Store_to_push(node);
916 /* transform Load->IncSP combinations to Pop where possible */
917 peephole_Load_IncSP_to_pop(node);
919 if (arch_get_irn_register(node) != esp)
922 /* replace IncSP -4 by Pop freereg when possible */
923 offset = be_get_IncSP_offset(node);
924 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
925 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
926 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
927 (offset != +8 || ia32_cg_config.use_sub_esp_8))
931 /* we need a free register for pop */
932 reg = get_free_gp_reg(get_irn_irg(node));
936 dbgi = get_irn_dbg_info(node);
937 block = get_nodes_block(node);
938 stack = be_get_IncSP_pred(node);
940 stack = create_pop(dbgi, block, stack, node, reg);
943 stack = create_pop(dbgi, block, stack, node, reg);
946 dbgi = get_irn_dbg_info(node);
947 block = get_nodes_block(node);
948 stack = be_get_IncSP_pred(node);
949 stack = new_bd_ia32_PushEax(dbgi, block, stack);
950 arch_set_irn_register(stack, esp);
951 sched_add_before(node, stack);
954 stack = new_bd_ia32_PushEax(dbgi, block, stack);
955 arch_set_irn_register(stack, esp);
956 sched_add_before(node, stack);
960 be_peephole_exchange(node, stack);
964 * Peephole optimisation for ia32_Const's
966 static void peephole_ia32_Const(ir_node *node)
968 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
969 const arch_register_t *reg;
974 /* try to transform a mov 0, reg to xor reg reg */
975 if (attr->offset != 0 || attr->symconst != NULL)
977 if (ia32_cg_config.use_mov_0)
979 /* xor destroys the flags, so no-one must be using them */
980 if (be_peephole_get_value(REG_EFLAGS) != NULL)
983 reg = arch_get_irn_register(node);
984 assert(be_peephole_get_reg_value(reg) == NULL);
986 /* create xor(produceval, produceval) */
987 block = get_nodes_block(node);
988 dbgi = get_irn_dbg_info(node);
989 xorn = new_bd_ia32_Xor0(dbgi, block);
990 arch_set_irn_register(xorn, reg);
992 sched_add_before(node, xorn);
994 copy_mark(node, xorn);
995 be_peephole_exchange(node, xorn);
998 static inline int is_noreg(const ir_node *node)
1000 return is_ia32_NoReg_GP(node);
1003 ir_node *ia32_immediate_from_long(long val)
1005 ir_graph *irg = current_ir_graph;
1006 ir_node *start_block = get_irg_start_block(irg);
1008 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
1009 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
1014 static ir_node *create_immediate_from_am(const ir_node *node)
1016 ir_node *block = get_nodes_block(node);
1017 int offset = get_ia32_am_offs_int(node);
1018 int sc_sign = is_ia32_am_sc_sign(node);
1019 const ia32_attr_t *attr = get_ia32_attr_const(node);
1020 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1021 ir_entity *entity = get_ia32_am_sc(node);
1024 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1026 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1030 static int is_am_one(const ir_node *node)
1032 int offset = get_ia32_am_offs_int(node);
1033 ir_entity *entity = get_ia32_am_sc(node);
1035 return offset == 1 && entity == NULL;
1038 static int is_am_minus_one(const ir_node *node)
1040 int offset = get_ia32_am_offs_int(node);
1041 ir_entity *entity = get_ia32_am_sc(node);
1043 return offset == -1 && entity == NULL;
1047 * Transforms a LEA into an Add or SHL if possible.
1049 static void peephole_ia32_Lea(ir_node *node)
1054 const arch_register_t *base_reg;
1055 const arch_register_t *index_reg;
1056 const arch_register_t *out_reg;
1067 assert(is_ia32_Lea(node));
1069 /* we can only do this if it is allowed to clobber the flags */
1070 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1073 base = get_irn_n(node, n_ia32_Lea_base);
1074 index = get_irn_n(node, n_ia32_Lea_index);
1076 if (is_noreg(base)) {
1080 base_reg = arch_get_irn_register(base);
1082 if (is_noreg(index)) {
1086 index_reg = arch_get_irn_register(index);
1089 if (base == NULL && index == NULL) {
1090 /* we shouldn't construct these in the first place... */
1091 #ifdef DEBUG_libfirm
1092 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1097 out_reg = arch_get_irn_register(node);
1098 scale = get_ia32_am_scale(node);
1099 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1100 /* check if we have immediates values (frame entities should already be
1101 * expressed in the offsets) */
1102 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1108 /* we can transform leas where the out register is the same as either the
1109 * base or index register back to an Add or Shl */
1110 if (out_reg == base_reg) {
1111 if (index == NULL) {
1112 #ifdef DEBUG_libfirm
1113 if (!has_immediates) {
1114 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1119 goto make_add_immediate;
1121 if (scale == 0 && !has_immediates) {
1126 /* can't create an add */
1128 } else if (out_reg == index_reg) {
1130 if (has_immediates && scale == 0) {
1132 goto make_add_immediate;
1133 } else if (!has_immediates && scale > 0) {
1135 op2 = ia32_immediate_from_long(scale);
1137 } else if (!has_immediates) {
1138 #ifdef DEBUG_libfirm
1139 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1143 } else if (scale == 0 && !has_immediates) {
1148 /* can't create an add */
1151 /* can't create an add */
1156 if (ia32_cg_config.use_incdec) {
1157 if (is_am_one(node)) {
1158 dbgi = get_irn_dbg_info(node);
1159 block = get_nodes_block(node);
1160 res = new_bd_ia32_Inc(dbgi, block, op1);
1161 arch_set_irn_register(res, out_reg);
1164 if (is_am_minus_one(node)) {
1165 dbgi = get_irn_dbg_info(node);
1166 block = get_nodes_block(node);
1167 res = new_bd_ia32_Dec(dbgi, block, op1);
1168 arch_set_irn_register(res, out_reg);
1172 op2 = create_immediate_from_am(node);
1175 dbgi = get_irn_dbg_info(node);
1176 block = get_nodes_block(node);
1177 irg = get_irn_irg(node);
1178 noreg = ia32_new_NoReg_gp(irg);
1179 nomem = get_irg_no_mem(irg);
1180 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1181 arch_set_irn_register(res, out_reg);
1182 set_ia32_commutative(res);
1186 dbgi = get_irn_dbg_info(node);
1187 block = get_nodes_block(node);
1188 irg = get_irn_irg(node);
1189 noreg = ia32_new_NoReg_gp(irg);
1190 nomem = get_irg_no_mem(irg);
1191 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1192 arch_set_irn_register(res, out_reg);
1196 SET_IA32_ORIG_NODE(res, node);
1198 /* add new ADD/SHL to schedule */
1199 DBG_OPT_LEA2ADD(node, res);
1201 /* exchange the Add and the LEA */
1202 sched_add_before(node, res);
1203 copy_mark(node, res);
1204 be_peephole_exchange(node, res);
1208 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1210 static void peephole_ia32_Imul_split(ir_node *imul)
1212 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1213 const arch_register_t *reg;
1216 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1217 /* no memory, imm form ignore */
1220 /* we need a free register */
1221 reg = get_free_gp_reg(get_irn_irg(imul));
1225 /* fine, we can rebuild it */
1226 res = ia32_turn_back_am(imul);
1227 arch_set_irn_register(res, reg);
1231 * Replace xorps r,r and xorpd r,r by pxor r,r
1233 static void peephole_ia32_xZero(ir_node *xorn)
1235 set_irn_op(xorn, op_ia32_xPzero);
1239 * Replace 16bit sign extension from ax to eax by shorter cwtl
1241 static void peephole_ia32_Conv_I2I(ir_node *node)
1243 const arch_register_t *eax = &ia32_registers[REG_EAX];
1244 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1245 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1250 if (get_mode_size_bits(smaller_mode) != 16 ||
1251 !mode_is_signed(smaller_mode) ||
1252 eax != arch_get_irn_register(val) ||
1253 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1256 dbgi = get_irn_dbg_info(node);
1257 block = get_nodes_block(node);
1258 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1259 arch_set_irn_register(cwtl, eax);
1260 sched_add_before(node, cwtl);
1261 be_peephole_exchange(node, cwtl);
1265 * Register a peephole optimisation function.
1267 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1269 assert(op->ops.generic == NULL);
1270 op->ops.generic = (op_func)func;
1273 /* Perform peephole-optimizations. */
1274 void ia32_peephole_optimization(ir_graph *irg)
1276 /* we currently do it in 2 passes because:
1277 * Lea -> Add could be usefull as flag producer for Test later
1281 ir_clear_opcodes_generic_func();
1282 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1283 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1284 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1285 if (ia32_cg_config.use_short_sex_eax)
1286 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1287 if (ia32_cg_config.use_pxor)
1288 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1289 if (! ia32_cg_config.use_imul_mem_imm32)
1290 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1291 be_peephole_opt(irg);
1294 ir_clear_opcodes_generic_func();
1295 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1296 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1297 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1298 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1299 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1300 be_peephole_opt(irg);
1304 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1305 * all its Projs are removed as well.
1306 * @param irn The irn to be removed from schedule
1308 static inline void try_kill(ir_node *node)
1310 if (get_irn_mode(node) == mode_T) {
1311 const ir_edge_t *edge, *next;
1312 foreach_out_edge_safe(node, edge, next) {
1313 ir_node *proj = get_edge_src_irn(edge);
1318 if (get_irn_n_edges(node) != 0)
1321 if (sched_is_scheduled(node)) {
1328 static void optimize_conv_store(ir_node *node)
1333 ir_mode *store_mode;
1335 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1338 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1339 pred_proj = get_irn_n(node, n_ia32_Store_val);
1340 if (is_Proj(pred_proj)) {
1341 pred = get_Proj_pred(pred_proj);
1345 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1347 if (get_ia32_op_type(pred) != ia32_Normal)
1350 /* the store only stores the lower bits, so we only need the conv
1351 * it it shrinks the mode */
1352 conv_mode = get_ia32_ls_mode(pred);
1353 store_mode = get_ia32_ls_mode(node);
1354 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1357 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1358 if (get_irn_n_edges(pred_proj) == 0) {
1359 kill_node(pred_proj);
1360 if (pred != pred_proj)
1365 static void optimize_load_conv(ir_node *node)
1367 ir_node *pred, *predpred;
1371 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1374 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1375 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1379 predpred = get_Proj_pred(pred);
1380 if (!is_ia32_Load(predpred))
1383 /* the load is sign extending the upper bits, so we only need the conv
1384 * if it shrinks the mode */
1385 load_mode = get_ia32_ls_mode(predpred);
1386 conv_mode = get_ia32_ls_mode(node);
1387 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1390 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1391 /* change the load if it has only 1 user */
1392 if (get_irn_n_edges(pred) == 1) {
1394 if (get_mode_sign(conv_mode)) {
1395 newmode = find_signed_mode(load_mode);
1397 newmode = find_unsigned_mode(load_mode);
1399 assert(newmode != NULL);
1400 set_ia32_ls_mode(predpred, newmode);
1402 /* otherwise we have to keep the conv */
1408 exchange(node, pred);
1411 static void optimize_conv_conv(ir_node *node)
1413 ir_node *pred_proj, *pred, *result_conv;
1414 ir_mode *pred_mode, *conv_mode;
1418 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1421 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1422 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1423 if (is_Proj(pred_proj))
1424 pred = get_Proj_pred(pred_proj);
1428 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1431 /* we know that after a conv, the upper bits are sign extended
1432 * so we only need the 2nd conv if it shrinks the mode */
1433 conv_mode = get_ia32_ls_mode(node);
1434 conv_mode_bits = get_mode_size_bits(conv_mode);
1435 pred_mode = get_ia32_ls_mode(pred);
1436 pred_mode_bits = get_mode_size_bits(pred_mode);
1438 if (conv_mode_bits == pred_mode_bits
1439 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1440 result_conv = pred_proj;
1441 } else if (conv_mode_bits <= pred_mode_bits) {
1442 /* if 2nd conv is smaller then first conv, then we can always take the
1444 if (get_irn_n_edges(pred_proj) == 1) {
1445 result_conv = pred_proj;
1446 set_ia32_ls_mode(pred, conv_mode);
1448 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1449 if (get_mode_size_bits(conv_mode) == 8) {
1450 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1451 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1452 arch_set_irn_register_reqs_in(pred, reqs);
1455 /* we don't want to end up with 2 loads, so we better do nothing */
1456 if (get_irn_mode(pred) == mode_T) {
1460 result_conv = exact_copy(pred);
1461 set_ia32_ls_mode(result_conv, conv_mode);
1463 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1464 if (get_mode_size_bits(conv_mode) == 8) {
1465 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1466 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1467 arch_set_irn_register_reqs_in(result_conv, reqs);
1471 /* if both convs have the same sign, then we can take the smaller one */
1472 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1473 result_conv = pred_proj;
1475 /* no optimisation possible if smaller conv is sign-extend */
1476 if (mode_is_signed(pred_mode)) {
1479 /* we can take the smaller conv if it is unsigned */
1480 result_conv = pred_proj;
1484 /* Some user (like Phis) won't be happy if we change the mode. */
1485 set_irn_mode(result_conv, get_irn_mode(node));
1488 exchange(node, result_conv);
1490 if (get_irn_n_edges(pred_proj) == 0) {
1491 kill_node(pred_proj);
1492 if (pred != pred_proj)
1495 optimize_conv_conv(result_conv);
1498 static void optimize_node(ir_node *node, void *env)
1502 optimize_load_conv(node);
1503 optimize_conv_store(node);
1504 optimize_conv_conv(node);
1508 * Performs conv and address mode optimization.
1510 void ia32_optimize_graph(ir_graph *irg)
1512 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1515 void ia32_init_optimize(void)
1517 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");