2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
65 * Returns non-zero if the given node produces
68 * @param node the node to check
69 * @param pn if >= 0, the projection number of the used result
71 static int produces_zero_flag(ir_node *node, int pn)
74 const ia32_immediate_attr_t *imm_attr;
76 if (!is_ia32_irn(node))
80 if (pn != pn_ia32_res)
84 switch (get_ia32_irn_opcode(node)) {
102 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
103 assert(n_ia32_Shl_count == n_ia32_Shr_count
104 && n_ia32_Shl_count == n_ia32_Sar_count);
105 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
106 count = get_irn_n(node, n_ia32_ShlD_count);
108 count = get_irn_n(node, n_ia32_Shl_count);
110 /* when shift count is zero the flags are not affected, so we can only
111 * do this for constants != 0 */
112 if (!is_ia32_Immediate(count))
115 imm_attr = get_ia32_immediate_attr_const(count);
116 if (imm_attr->symconst != NULL)
118 if ((imm_attr->offset & 0x1f) == 0)
129 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
131 * @param node the node to change
133 * @return the new mode_T node (if the mode was changed) or node itself
135 static ir_node *turn_into_mode_t(ir_node *node)
140 const arch_register_t *reg;
142 if(get_irn_mode(node) == mode_T)
145 assert(get_irn_mode(node) == mode_Iu);
147 new_node = exact_copy(node);
148 set_irn_mode(new_node, mode_T);
150 block = get_nodes_block(new_node);
151 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
154 reg = arch_get_irn_register(arch_env, node);
155 arch_set_irn_register(arch_env, res_proj, reg);
157 sched_add_before(node, new_node);
158 be_peephole_exchange(node, res_proj);
163 * Peephole optimization for Test instructions.
164 * We can remove the Test, if a zero flags was produced which is still
167 static void peephole_ia32_Test(ir_node *node)
169 ir_node *left = get_irn_n(node, n_ia32_Test_left);
170 ir_node *right = get_irn_n(node, n_ia32_Test_right);
176 const ir_edge_t *edge;
178 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
179 && n_ia32_Test_right == n_ia32_Test8Bit_right);
181 /* we need a test for 0 */
185 block = get_nodes_block(node);
186 if(get_nodes_block(left) != block)
190 pn = get_Proj_proj(left);
191 left = get_Proj_pred(left);
194 /* happens rarely, but if it does code will panic' */
195 if (is_ia32_Unknown_GP(left))
198 /* walk schedule up and abort when we find left or some other node destroys
200 schedpoint = sched_prev(node);
201 while(schedpoint != left) {
202 schedpoint = sched_prev(schedpoint);
203 if(arch_irn_is(arch_env, schedpoint, modify_flags))
205 if(schedpoint == block)
206 panic("couldn't find left");
209 /* make sure only Lg/Eq tests are used */
210 foreach_out_edge(node, edge) {
211 ir_node *user = get_edge_src_irn(edge);
212 int pnc = get_ia32_condcode(user);
214 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
219 if(!produces_zero_flag(left, pn))
222 left = turn_into_mode_t(left);
224 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
225 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
227 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
229 assert(get_irn_mode(node) != mode_T);
231 be_peephole_exchange(node, flags_proj);
235 * AMD Athlon works faster when RET is not destination of
236 * conditional jump or directly preceded by other jump instruction.
237 * Can be avoided by placing a Rep prefix before the return.
239 static void peephole_ia32_Return(ir_node *node) {
240 ir_node *block, *irn;
242 if (!ia32_cg_config.use_pad_return)
245 block = get_nodes_block(node);
247 /* check if this return is the first on the block */
248 sched_foreach_reverse_from(node, irn) {
249 switch (get_irn_opcode(irn)) {
251 /* the return node itself, ignore */
254 /* ignore the barrier, no code generated */
257 /* arg, IncSP 0 nodes might occur, ignore these */
258 if (be_get_IncSP_offset(irn) == 0)
268 /* ensure, that the 3 byte return is generated
269 * actually the emitter tests again if the block beginning has a label and
270 * isn't just a fallthrough */
271 be_Return_set_emit_pop(node, 1);
274 /* only optimize up to 48 stores behind IncSPs */
275 #define MAXPUSH_OPTIMIZE 48
278 * Tries to create Push's from IncSP, Store combinations.
279 * The Stores are replaced by Push's, the IncSP is modified
280 * (possibly into IncSP 0, but not removed).
282 static void peephole_IncSP_Store_to_push(ir_node *irn)
284 int i, maxslot, inc_ofs;
286 ir_node *stores[MAXPUSH_OPTIMIZE];
292 memset(stores, 0, sizeof(stores));
294 assert(be_is_IncSP(irn));
296 inc_ofs = be_get_IncSP_offset(irn);
301 * We first walk the schedule after the IncSP node as long as we find
302 * suitable Stores that could be transformed to a Push.
303 * We save them into the stores array which is sorted by the frame offset/4
304 * attached to the node
307 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
312 /* it has to be a Store */
313 if (!is_ia32_Store(node))
316 /* it has to use our sp value */
317 if (get_irn_n(node, n_ia32_base) != irn)
319 /* Store has to be attached to NoMem */
320 mem = get_irn_n(node, n_ia32_mem);
324 /* unfortunately we can't support the full AMs possible for push at the
325 * moment. TODO: fix this */
326 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
329 offset = get_ia32_am_offs_int(node);
330 /* we should NEVER access uninitialized stack BELOW the current SP */
333 offset = inc_ofs - 4 - offset;
335 /* storing at half-slots is bad */
336 if ((offset & 3) != 0)
339 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
341 storeslot = offset >> 2;
343 /* storing into the same slot twice is bad (and shouldn't happen...) */
344 if (stores[storeslot] != NULL)
347 stores[storeslot] = node;
348 if (storeslot > maxslot)
352 curr_sp = be_get_IncSP_pred(irn);
354 /* walk through the Stores and create Pushs for them */
355 block = get_nodes_block(irn);
356 spmode = get_irn_mode(irn);
358 for (i = 0; i <= maxslot; ++i) {
359 const arch_register_t *spreg;
361 ir_node *val, *mem, *mem_proj;
362 ir_node *store = stores[i];
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
368 val = get_irn_n(store, n_ia32_unary_op);
369 mem = get_irn_n(store, n_ia32_mem);
370 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
372 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
374 sched_add_before(irn, push);
376 /* create stackpointer Proj */
377 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
378 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
380 /* create memory Proj */
381 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
383 /* use the memproj now */
384 exchange(store, mem_proj);
386 /* we can remove the Store now */
392 be_set_IncSP_offset(irn, inc_ofs);
393 be_set_IncSP_pred(irn, curr_sp);
397 * Return true if a mode can be stored in the GP register set
399 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
400 if (mode == mode_fpcw)
402 if (get_mode_size_bits(mode) > 32)
404 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
408 * Tries to create Pops from Load, IncSP combinations.
409 * The Loads are replaced by Pops, the IncSP is modified
410 * (possibly into IncSP 0, but not removed).
412 static void peephole_Load_IncSP_to_pop(ir_node *irn)
414 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
415 int i, maxslot, inc_ofs, ofs;
416 ir_node *node, *pred_sp, *block;
417 ir_node *loads[MAXPUSH_OPTIMIZE];
419 unsigned regmask = 0;
420 unsigned copymask = ~0;
422 memset(loads, 0, sizeof(loads));
423 assert(be_is_IncSP(irn));
425 inc_ofs = -be_get_IncSP_offset(irn);
430 * We first walk the schedule before the IncSP node as long as we find
431 * suitable Loads that could be transformed to a Pop.
432 * We save them into the stores array which is sorted by the frame offset/4
433 * attached to the node
436 pred_sp = be_get_IncSP_pred(irn);
437 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
441 const arch_register_t *sreg, *dreg;
443 /* it has to be a Load */
444 if (!is_ia32_Load(node)) {
445 if (be_is_Copy(node)) {
446 if (!mode_needs_gp_reg(get_irn_mode(node))) {
447 /* not a GP copy, ignore */
450 dreg = arch_get_irn_register(arch_env, node);
451 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
452 if (regmask & copymask & (1 << sreg->index)) {
455 if (regmask & copymask & (1 << dreg->index)) {
458 /* we CAN skip Copies if neither the destination nor the source
459 * is not in our regmask, ie none of our future Pop will overwrite it */
460 regmask |= (1 << dreg->index) | (1 << sreg->index);
461 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
467 /* we can handle only GP loads */
468 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
471 /* it has to use our predecessor sp value */
472 if (get_irn_n(node, n_ia32_base) != pred_sp) {
473 /* it would be ok if this load does not use a Pop result,
474 * but we do not check this */
477 /* Load has to be attached to Spill-Mem */
478 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
479 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
482 /* should have NO index */
483 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
486 offset = get_ia32_am_offs_int(node);
487 /* we should NEVER access uninitialized stack BELOW the current SP */
490 /* storing at half-slots is bad */
491 if ((offset & 3) != 0)
494 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
496 /* ignore those outside the possible windows */
497 if (offset > inc_ofs - 4)
499 loadslot = offset >> 2;
501 /* loading from the same slot twice is bad (and shouldn't happen...) */
502 if (loads[loadslot] != NULL)
505 dreg = arch_get_irn_register(arch_env, node);
506 if (regmask & (1 << dreg->index)) {
507 /* this register is already used */
510 regmask |= 1 << dreg->index;
512 loads[loadslot] = node;
513 if (loadslot > maxslot)
520 /* find the first slot */
521 for (i = maxslot; i >= 0; --i) {
522 ir_node *load = loads[i];
528 ofs = inc_ofs - (maxslot + 1) * 4;
531 /* create a new IncSP if needed */
532 block = get_nodes_block(irn);
535 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
536 sched_add_before(irn, pred_sp);
539 /* walk through the Loads and create Pops for them */
540 for (++i; i <= maxslot; ++i) {
541 ir_node *load = loads[i];
543 const ir_edge_t *edge, *tmp;
544 const arch_register_t *reg;
546 mem = get_irn_n(load, n_ia32_mem);
547 reg = arch_get_irn_register(arch_env, load);
549 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
550 arch_set_irn_register(arch_env, pop, reg);
552 /* create stackpointer Proj */
553 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
554 arch_set_irn_register(arch_env, pred_sp, esp);
556 sched_add_before(irn, pop);
559 foreach_out_edge_safe(load, edge, tmp) {
560 ir_node *proj = get_edge_src_irn(edge);
562 set_Proj_pred(proj, pop);
566 /* we can remove the Load now */
570 be_set_IncSP_offset(irn, -ofs);
571 be_set_IncSP_pred(irn, pred_sp);
577 * Find a free GP register if possible, else return NULL.
579 static const arch_register_t *get_free_gp_reg(void)
583 for(i = 0; i < N_ia32_gp_REGS; ++i) {
584 const arch_register_t *reg = &ia32_gp_regs[i];
585 if(arch_register_type_is(reg, ignore))
588 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
589 return &ia32_gp_regs[i];
596 * Creates a Pop instruction before the given schedule point.
598 * @param dbgi debug info
599 * @param irg the graph
600 * @param block the block
601 * @param stack the previous stack value
602 * @param schedpoint the new node is added before this node
603 * @param reg the register to pop
605 * @return the new stack value
607 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
608 ir_node *stack, ir_node *schedpoint,
609 const arch_register_t *reg)
611 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
617 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
619 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
620 arch_set_irn_register(arch_env, stack, esp);
621 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
622 arch_set_irn_register(arch_env, val, reg);
624 sched_add_before(schedpoint, pop);
627 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
628 sched_add_before(schedpoint, keep);
634 * Creates a Push instruction before the given schedule point.
636 * @param dbgi debug info
637 * @param irg the graph
638 * @param block the block
639 * @param stack the previous stack value
640 * @param schedpoint the new node is added before this node
641 * @param reg the register to pop
643 * @return the new stack value
645 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
646 ir_node *stack, ir_node *schedpoint,
647 const arch_register_t *reg)
649 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
650 ir_node *noreg, *nomem, *push, *val;
652 val = new_rd_ia32_ProduceVal(NULL, irg, block);
653 arch_set_irn_register(arch_env, val, reg);
654 sched_add_before(schedpoint, val);
656 noreg = ia32_new_NoReg_gp(cg);
657 nomem = get_irg_no_mem(irg);
658 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
659 sched_add_before(schedpoint, push);
661 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
662 arch_set_irn_register(arch_env, stack, esp);
668 * Optimize an IncSp by replacing it with Push/Pop.
670 static void peephole_be_IncSP(ir_node *node)
672 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
673 const arch_register_t *reg;
674 ir_graph *irg = current_ir_graph;
680 /* first optimize incsp->incsp combinations */
681 node = be_peephole_IncSP_IncSP(node);
683 /* transform IncSP->Store combinations to Push where possible */
684 peephole_IncSP_Store_to_push(node);
686 /* transform Load->IncSP combinations to Pop where possible */
687 peephole_Load_IncSP_to_pop(node);
689 if (arch_get_irn_register(arch_env, node) != esp)
692 /* replace IncSP -4 by Pop freereg when possible */
693 offset = be_get_IncSP_offset(node);
694 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
695 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
696 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
697 (offset != +8 || ia32_cg_config.use_sub_esp_8))
701 /* we need a free register for pop */
702 reg = get_free_gp_reg();
706 dbgi = get_irn_dbg_info(node);
707 block = get_nodes_block(node);
708 stack = be_get_IncSP_pred(node);
710 stack = create_pop(dbgi, irg, block, stack, node, reg);
713 stack = create_pop(dbgi, irg, block, stack, node, reg);
716 dbgi = get_irn_dbg_info(node);
717 block = get_nodes_block(node);
718 stack = be_get_IncSP_pred(node);
719 reg = &ia32_gp_regs[REG_EAX];
721 stack = create_push(dbgi, irg, block, stack, node, reg);
724 stack = create_push(dbgi, irg, block, stack, node, reg);
728 be_peephole_exchange(node, stack);
732 * Peephole optimisation for ia32_Const's
734 static void peephole_ia32_Const(ir_node *node)
736 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
737 const arch_register_t *reg;
738 ir_graph *irg = current_ir_graph;
745 /* try to transform a mov 0, reg to xor reg reg */
746 if (attr->offset != 0 || attr->symconst != NULL)
748 if (ia32_cg_config.use_mov_0)
750 /* xor destroys the flags, so no-one must be using them */
751 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
754 reg = arch_get_irn_register(arch_env, node);
755 assert(be_peephole_get_reg_value(reg) == NULL);
757 /* create xor(produceval, produceval) */
758 block = get_nodes_block(node);
759 dbgi = get_irn_dbg_info(node);
760 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
761 arch_set_irn_register(arch_env, produceval, reg);
763 noreg = ia32_new_NoReg_gp(cg);
764 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
765 produceval, produceval);
766 arch_set_irn_register(arch_env, xor, reg);
768 sched_add_before(node, produceval);
769 sched_add_before(node, xor);
771 be_peephole_exchange(node, xor);
774 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
776 return node == cg->noreg_gp;
779 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
781 ir_graph *irg = current_ir_graph;
782 ir_node *start_block = get_irg_start_block(irg);
783 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
785 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
790 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
793 ir_graph *irg = get_irn_irg(node);
794 ir_node *block = get_nodes_block(node);
795 int offset = get_ia32_am_offs_int(node);
796 int sc_sign = is_ia32_am_sc_sign(node);
797 ir_entity *entity = get_ia32_am_sc(node);
800 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
801 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
805 static int is_am_one(const ir_node *node)
807 int offset = get_ia32_am_offs_int(node);
808 ir_entity *entity = get_ia32_am_sc(node);
810 return offset == 1 && entity == NULL;
813 static int is_am_minus_one(const ir_node *node)
815 int offset = get_ia32_am_offs_int(node);
816 ir_entity *entity = get_ia32_am_sc(node);
818 return offset == -1 && entity == NULL;
822 * Transforms a LEA into an Add or SHL if possible.
824 static void peephole_ia32_Lea(ir_node *node)
826 const arch_env_t *arch_env = cg->arch_env;
827 ir_graph *irg = current_ir_graph;
830 const arch_register_t *base_reg;
831 const arch_register_t *index_reg;
832 const arch_register_t *out_reg;
843 assert(is_ia32_Lea(node));
845 /* we can only do this if are allowed to globber the flags */
846 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
849 base = get_irn_n(node, n_ia32_Lea_base);
850 index = get_irn_n(node, n_ia32_Lea_index);
852 if(is_noreg(cg, base)) {
856 base_reg = arch_get_irn_register(arch_env, base);
858 if(is_noreg(cg, index)) {
862 index_reg = arch_get_irn_register(arch_env, index);
865 if(base == NULL && index == NULL) {
866 /* we shouldn't construct these in the first place... */
868 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
873 out_reg = arch_get_irn_register(arch_env, node);
874 scale = get_ia32_am_scale(node);
875 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
876 /* check if we have immediates values (frame entities should already be
877 * expressed in the offsets) */
878 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
884 /* we can transform leas where the out register is the same as either the
885 * base or index register back to an Add or Shl */
886 if(out_reg == base_reg) {
889 if(!has_immediates) {
890 ir_fprintf(stderr, "Optimisation warning: found lea which is "
895 goto make_add_immediate;
897 if(scale == 0 && !has_immediates) {
902 /* can't create an add */
904 } else if(out_reg == index_reg) {
906 if(has_immediates && scale == 0) {
908 goto make_add_immediate;
909 } else if(!has_immediates && scale > 0) {
911 op2 = create_immediate_from_int(cg, scale);
913 } else if(!has_immediates) {
915 ir_fprintf(stderr, "Optimisation warning: found lea which is "
919 } else if(scale == 0 && !has_immediates) {
924 /* can't create an add */
927 /* can't create an add */
932 if(ia32_cg_config.use_incdec) {
933 if(is_am_one(node)) {
934 dbgi = get_irn_dbg_info(node);
935 block = get_nodes_block(node);
936 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
937 arch_set_irn_register(arch_env, res, out_reg);
940 if(is_am_minus_one(node)) {
941 dbgi = get_irn_dbg_info(node);
942 block = get_nodes_block(node);
943 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
944 arch_set_irn_register(arch_env, res, out_reg);
948 op2 = create_immediate_from_am(cg, node);
951 dbgi = get_irn_dbg_info(node);
952 block = get_nodes_block(node);
953 noreg = ia32_new_NoReg_gp(cg);
955 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
956 arch_set_irn_register(arch_env, res, out_reg);
957 set_ia32_commutative(res);
961 dbgi = get_irn_dbg_info(node);
962 block = get_nodes_block(node);
963 noreg = ia32_new_NoReg_gp(cg);
965 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
966 arch_set_irn_register(arch_env, res, out_reg);
970 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
972 /* add new ADD/SHL to schedule */
973 DBG_OPT_LEA2ADD(node, res);
975 /* exchange the Add and the LEA */
976 sched_add_before(node, res);
977 be_peephole_exchange(node, res);
981 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
983 static void peephole_ia32_Imul_split(ir_node *imul) {
984 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
985 const arch_register_t *reg;
986 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
990 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
991 /* no memory, imm form ignore */
994 /* we need a free register */
995 reg = get_free_gp_reg();
999 /* fine, we can rebuild it */
1000 dbgi = get_irn_dbg_info(imul);
1001 block = get_nodes_block(imul);
1002 irg = current_ir_graph;
1003 base = get_irn_n(imul, n_ia32_IMul_base);
1004 index = get_irn_n(imul, n_ia32_IMul_index);
1005 mem = get_irn_n(imul, n_ia32_IMul_mem);
1006 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1008 /* copy all attributes */
1009 set_irn_pinned(load, get_irn_pinned(imul));
1010 set_ia32_op_type(load, ia32_AddrModeS);
1011 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1013 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1014 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1015 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1016 if (is_ia32_am_sc_sign(imul))
1017 set_ia32_am_sc_sign(load);
1018 if (is_ia32_use_frame(imul))
1019 set_ia32_use_frame(load);
1020 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1022 sched_add_before(imul, load);
1024 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1025 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1027 arch_set_irn_register(arch_env, res, reg);
1028 be_peephole_new_node(res);
1030 set_irn_n(imul, n_ia32_IMul_mem, mem);
1031 noreg = get_irn_n(imul, n_ia32_IMul_left);
1032 set_irn_n(imul, n_ia32_IMul_left, res);
1033 set_ia32_op_type(imul, ia32_Normal);
1037 * Replace xorps r,r and xorpd r,r by pxor r,r
1039 static void peephole_ia32_xZero(ir_node *xor) {
1040 set_irn_op(xor, op_ia32_xPzero);
1044 * Register a peephole optimisation function.
1046 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1047 assert(op->ops.generic == NULL);
1048 op->ops.generic = (op_func)func;
1051 /* Perform peephole-optimizations. */
1052 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1055 arch_env = cg->arch_env;
1057 /* register peephole optimisations */
1058 clear_irp_opcodes_generic_func();
1059 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1060 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1061 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1062 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1063 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1064 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1065 if (! ia32_cg_config.use_imul_mem_imm32)
1066 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1067 if (ia32_cg_config.use_pxor)
1068 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1070 be_peephole_opt(cg->birg);
1074 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1075 * all it's Projs are removed as well.
1076 * @param irn The irn to be removed from schedule
1078 static INLINE void try_kill(ir_node *node)
1080 if(get_irn_mode(node) == mode_T) {
1081 const ir_edge_t *edge, *next;
1082 foreach_out_edge_safe(node, edge, next) {
1083 ir_node *proj = get_edge_src_irn(edge);
1088 if(get_irn_n_edges(node) != 0)
1091 if (sched_is_scheduled(node)) {
1098 static void optimize_conv_store(ir_node *node)
1103 ir_mode *store_mode;
1105 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1108 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1109 pred_proj = get_irn_n(node, n_ia32_Store_val);
1110 if(is_Proj(pred_proj)) {
1111 pred = get_Proj_pred(pred_proj);
1115 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1117 if(get_ia32_op_type(pred) != ia32_Normal)
1120 /* the store only stores the lower bits, so we only need the conv
1121 * it it shrinks the mode */
1122 conv_mode = get_ia32_ls_mode(pred);
1123 store_mode = get_ia32_ls_mode(node);
1124 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1127 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1128 if(get_irn_n_edges(pred_proj) == 0) {
1129 be_kill_node(pred_proj);
1130 if(pred != pred_proj)
1135 static void optimize_load_conv(ir_node *node)
1137 ir_node *pred, *predpred;
1141 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1144 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1145 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1149 predpred = get_Proj_pred(pred);
1150 if(!is_ia32_Load(predpred))
1153 /* the load is sign extending the upper bits, so we only need the conv
1154 * if it shrinks the mode */
1155 load_mode = get_ia32_ls_mode(predpred);
1156 conv_mode = get_ia32_ls_mode(node);
1157 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1160 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1161 /* change the load if it has only 1 user */
1162 if(get_irn_n_edges(pred) == 1) {
1164 if(get_mode_sign(conv_mode)) {
1165 newmode = find_signed_mode(load_mode);
1167 newmode = find_unsigned_mode(load_mode);
1169 assert(newmode != NULL);
1170 set_ia32_ls_mode(predpred, newmode);
1172 /* otherwise we have to keep the conv */
1178 exchange(node, pred);
1181 static void optimize_conv_conv(ir_node *node)
1183 ir_node *pred_proj, *pred, *result_conv;
1184 ir_mode *pred_mode, *conv_mode;
1188 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1191 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1192 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1193 if(is_Proj(pred_proj))
1194 pred = get_Proj_pred(pred_proj);
1198 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1201 /* we know that after a conv, the upper bits are sign extended
1202 * so we only need the 2nd conv if it shrinks the mode */
1203 conv_mode = get_ia32_ls_mode(node);
1204 conv_mode_bits = get_mode_size_bits(conv_mode);
1205 pred_mode = get_ia32_ls_mode(pred);
1206 pred_mode_bits = get_mode_size_bits(pred_mode);
1208 if(conv_mode_bits == pred_mode_bits
1209 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1210 result_conv = pred_proj;
1211 } else if(conv_mode_bits <= pred_mode_bits) {
1212 /* if 2nd conv is smaller then first conv, then we can always take the
1214 if(get_irn_n_edges(pred_proj) == 1) {
1215 result_conv = pred_proj;
1216 set_ia32_ls_mode(pred, conv_mode);
1218 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1219 if (get_mode_size_bits(conv_mode) == 8) {
1220 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1221 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1224 /* we don't want to end up with 2 loads, so we better do nothing */
1225 if(get_irn_mode(pred) == mode_T) {
1229 result_conv = exact_copy(pred);
1230 set_ia32_ls_mode(result_conv, conv_mode);
1232 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1233 if (get_mode_size_bits(conv_mode) == 8) {
1234 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1235 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1239 /* if both convs have the same sign, then we can take the smaller one */
1240 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1241 result_conv = pred_proj;
1243 /* no optimisation possible if smaller conv is sign-extend */
1244 if(mode_is_signed(pred_mode)) {
1247 /* we can take the smaller conv if it is unsigned */
1248 result_conv = pred_proj;
1253 exchange(node, result_conv);
1255 if(get_irn_n_edges(pred_proj) == 0) {
1256 be_kill_node(pred_proj);
1257 if(pred != pred_proj)
1260 optimize_conv_conv(result_conv);
1263 static void optimize_node(ir_node *node, void *env)
1267 optimize_load_conv(node);
1268 optimize_conv_store(node);
1269 optimize_conv_conv(node);
1273 * Performs conv and address mode optimization.
1275 void ia32_optimize_graph(ia32_code_gen_t *cg)
1277 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1280 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1283 void ia32_init_optimize(void)
1285 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");