3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universität Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
28 #include "../benode_t.h"
29 #include "../besched_t.h"
31 #include "ia32_new_nodes.h"
32 #include "bearch_ia32_t.h"
33 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "ia32_transform.h"
35 #include "ia32_dbg_stat.h"
36 #include "ia32_util.h"
38 typedef struct _ia32_place_env_t {
44 IA32_AM_CAND_NONE = 0,
45 IA32_AM_CAND_LEFT = 1,
46 IA32_AM_CAND_RIGHT = 2,
51 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
53 typedef int is_op_func_t(const ir_node *n);
54 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
57 * checks if a node represents the NOREG value
59 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
60 be_abi_irg_t *babi = cg->birg->abi;
61 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
62 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
64 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
65 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
70 /*************************************************
73 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
74 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
75 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
76 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
78 *************************************************/
81 * creates a unique ident by adding a number to a tag
83 * @param tag the tag string, must contain a %d if a number
86 static ident *unique_id(const char *tag)
88 static unsigned id = 0;
91 snprintf(str, sizeof(str), tag, ++id);
92 return new_id_from_str(str);
96 * Transforms a SymConst.
98 * @param mod the debug module
99 * @param block the block the new node should belong to
100 * @param node the ir SymConst node
101 * @param mode mode of the SymConst
102 * @return the created ia32 Const node
104 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
105 dbg_info *dbg = env->dbg;
106 ir_mode *mode = env->mode;
107 ir_graph *irg = env->irg;
108 ir_node *block = env->block;
111 if (mode_is_float(mode)) {
113 if (USE_SSE2(env->cg))
114 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
116 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
119 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
121 set_ia32_Const_attr(cnst, env->irn);
127 * Get a primitive type for a mode.
129 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
131 pmap_entry *e = pmap_find(types, mode);
136 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
137 res = new_type_primitive(new_id_from_str(buf), mode);
138 pmap_insert(types, mode, res);
146 * Get an entity that is initialized with a tarval
148 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
150 tarval *tv = get_Const_tarval(cnst);
151 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
156 ir_mode *mode = get_irn_mode(cnst);
157 ir_type *tp = get_Const_type(cnst);
158 if (tp == firm_unknown_type)
159 tp = get_prim_type(cg->isa->types, mode);
161 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
163 set_entity_ld_ident(res, get_entity_ident(res));
164 set_entity_visibility(res, visibility_local);
165 set_entity_variability(res, variability_constant);
166 set_entity_allocation(res, allocation_static);
168 /* we create a new entity here: It's initialization must resist on the
170 rem = current_ir_graph;
171 current_ir_graph = get_const_code_irg();
172 set_atomic_ent_value(res, new_Const_type(tv, tp));
173 current_ir_graph = rem;
175 pmap_insert(cg->isa->tv_ent, tv, res);
183 * Transforms a Const.
185 * @param mod the debug module
186 * @param block the block the new node should belong to
187 * @param node the ir Const node
188 * @param mode mode of the Const
189 * @return the created ia32 Const node
191 static ir_node *gen_Const(ia32_transform_env_t *env) {
192 ir_node *cnst, *load;
194 ir_graph *irg = env->irg;
195 ir_node *block = env->block;
196 ir_node *node = env->irn;
197 dbg_info *dbg = env->dbg;
198 ir_mode *mode = env->mode;
200 if (mode_is_float(mode)) {
202 if (! USE_SSE2(env->cg)) {
203 cnst_classify_t clss = classify_Const(node);
205 if (clss == CNST_NULL)
206 return new_rd_ia32_vfldz(dbg, irg, block, mode);
207 else if (clss == CNST_ONE)
208 return new_rd_ia32_vfld1(dbg, irg, block, mode);
210 sym.entity_p = get_entity_for_tv(env->cg, node);
213 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
214 load = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode);
215 load = new_r_Proj(irg, block, load, mode, pn_Load_res);
218 cnst = gen_SymConst(env);
219 set_Load_ptr(get_Proj_pred(load), cnst);
223 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
224 set_ia32_Const_attr(cnst, node);
230 * Transforms (all) Const's into ia32_Const and places them in the
231 * block where they are used (or in the cfg-pred Block in case of Phi's).
232 * Additionally all reference nodes are changed into mode_Is nodes.
233 * NOTE: irn must be a firm constant!
235 static void ia32_transform_const(ir_node *irn, void *env) {
236 ia32_code_gen_t *cg = env;
237 ir_node *cnst = NULL;
238 ia32_transform_env_t tenv;
242 tenv.mode = get_irn_mode(irn);
243 tenv.dbg = get_irn_dbg_info(irn);
245 DEBUG_ONLY(tenv.mod = cg->mod;)
247 /* place const either in the smallest dominator of all its users or the original block */
248 if (cg->opt & IA32_OPT_PLACECNST)
249 tenv.block = node_users_smallest_common_dominator(irn, 1);
251 tenv.block = get_nodes_block(irn);
253 switch (get_irn_opcode(irn)) {
255 cnst = gen_Const(&tenv);
258 cnst = gen_SymConst(&tenv);
261 assert(0 && "Wrong usage of ia32_transform_const!");
264 assert(cnst && "Could not create ia32 Const");
266 /* set the new ia32 const */
271 * Transform all firm consts and assure, we visit each const only once.
273 static void ia32_place_consts_walker(ir_node *irn, void *env) {
274 ia32_place_env_t *penv = env;
275 opcode opc = get_irn_opcode(irn);
277 /* transform only firm consts which are not already visited */
278 if ((opc != iro_Const && opc != iro_SymConst) || bitset_is_set(penv->visited, get_irn_idx(irn)))
281 /* mark const visited */
282 bitset_set(penv->visited, get_irn_idx(irn));
284 ia32_transform_const(irn, penv->cg);
288 * Replace reference modes with mode_Iu and preserve store value modes.
290 static void ia32_set_modes(ir_node *irn, void *env) {
294 /* transform all reference nodes into mode_Iu nodes */
295 if (mode_is_reference(get_irn_mode(irn))) {
296 set_irn_mode(irn, mode_Iu);
301 * Walks over the graph, transforms all firm consts into ia32 consts
302 * and places them into the "best" block.
303 * @param cg The ia32 codegenerator object
305 static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
306 ia32_place_env_t penv;
309 penv.visited = bitset_irg_malloc(cg->irg);
310 irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, &penv);
311 bitset_free(penv.visited);
314 /* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
315 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
317 We need to transform the consts twice:
318 - the psi condition tree transformer needs existing constants to be ia32 constants
319 - the psi condition tree transformer inserts new firm constants which need to be transformed
321 ia32_transform_all_firm_consts(cg);
322 irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
323 ia32_transform_all_firm_consts(cg);
326 /********************************************************************************************************
327 * _____ _ _ ____ _ _ _ _ _
328 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
329 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
330 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
331 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
332 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
335 ********************************************************************************************************/
338 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
341 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
342 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
346 * Checks for potential CJmp/CJmpAM optimization candidates.
348 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
349 ir_node *cand = NULL;
350 ir_node *prev = sched_prev(irn);
352 if (is_Block(prev)) {
353 if (get_Block_n_cfgpreds(prev) == 1)
354 prev = get_Block_cfgpred(prev, 0);
359 /* The predecessor must be a ProjX. */
360 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
361 prev = get_Proj_pred(prev);
363 if (is_op_func(prev))
370 static int is_TestJmp_cand(const ir_node *irn) {
371 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
375 * Checks if two consecutive arguments of cand matches
376 * the two arguments of irn (TestJmp).
378 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
379 ir_node *in1 = get_irn_n(irn, 0);
380 ir_node *in2 = get_irn_n(irn, 1);
381 int i, n = get_irn_arity(cand);
384 for (i = 0; i < n - 1; i++) {
385 if (get_irn_n(cand, i) == in1 &&
386 get_irn_n(cand, i + 1) == in2)
394 return ia32_cnst_compare(cand, irn);
400 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
402 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
403 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
406 /* we found a possible candidate */
407 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
410 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
412 if (is_ia32_And(cand))
413 set_irn_op(irn, op_ia32_CJmpAM);
415 set_irn_op(irn, op_ia32_CJmp);
417 DB((cg->mod, LEVEL_1, "%+F\n", irn));
421 static int is_CondJmp_cand(const ir_node *irn) {
422 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
426 * Checks if the arguments of cand are the same of irn.
428 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
429 int i, n = get_irn_arity(cand);
432 for (i = 0; i < n; i++) {
433 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
440 return ia32_cnst_compare(cand, irn);
446 * Tries to replace a CondJmp by a CJmpAM
448 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
449 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
452 /* we found a possible candidate */
453 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
456 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
459 set_irn_op(irn, op_ia32_CJmpAM);
461 DB((cg->mod, LEVEL_1, "%+F\n", irn));
466 * Creates a Push from Store(IncSP(gp_reg_size))
468 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
469 ir_node *sp = get_irn_n(irn, 0);
470 ir_graph *irg = cg->irg;
471 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M, *mem;
472 const ir_edge_t *edge;
475 /* do not create push if store has already an offset assigned or base is not a IncSP */
476 if (get_ia32_am_offs(irn) || ! be_is_IncSP(sp))
479 /* do not create push if index is not NOREG */
480 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
481 &ia32_gp_regs[REG_GP_NOREG])
484 /* do not create push for floating point */
485 val = get_irn_n(irn, 2);
486 if (mode_is_float(get_irn_mode(val)))
489 /* do not create push if IncSp doesn't expand stack or expand size is different from register size */
490 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
491 be_get_IncSP_offset(sp) != (unsigned) get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
494 /* do not create push, if there is a path (inside the block) from the push value to IncSP */
495 h = heights_new(cg->irg);
496 if (get_nodes_block(val) == get_nodes_block(sp) &&
497 heights_reachable_in_block(h, val, sp))
504 /* ok, translate into Push */
505 edge = get_irn_out_edge_first(irn);
506 old_proj_M = get_edge_src_irn(edge);
507 bl = get_nodes_block(irn);
509 next = sched_next(irn);
515 if the IncSP points to NoMem -> just use the memory input from store
516 if IncSP points to somewhere else -> sync memory of IncSP and Store
518 mem = be_get_IncSP_mem(sp);
519 if (mem == get_irg_no_mem(irg))
520 mem = get_irn_n(irn, 3);
525 in[1] = get_irn_n(irn, 3);
526 mem = new_r_Sync(irg, bl, 2, in);
529 push = new_rd_ia32_Push(NULL, irg, bl, be_get_IncSP_pred(sp), val, mem);
530 proj_res = new_r_Proj(irg, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
531 proj_M = new_r_Proj(irg, bl, push, mode_M, pn_ia32_Push_M);
533 /* copy a possible constant from the store */
534 set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
535 set_ia32_immop_type(push, get_ia32_immop_type(irn));
537 /* the push must have SP out register */
538 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
540 exchange(old_proj_M, proj_M);
541 exchange(sp, proj_res);
542 sched_add_before(next, push);
543 sched_add_after(push, proj_res);
547 * Creates a Pop from IncSP(Load(sp))
549 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
550 ir_node *old_proj_M = be_get_IncSP_mem(irn);
551 ir_node *load = skip_Proj(old_proj_M);
552 ir_node *old_proj_res = NULL;
553 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
554 const ir_edge_t *edge;
555 const arch_register_t *reg, *sp;
557 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
560 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
561 &ia32_gp_regs[REG_GP_NOREG])
563 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
566 /* ok, translate into pop */
567 foreach_out_edge(load, edge) {
568 ir_node *succ = get_edge_src_irn(edge);
569 if (succ != old_proj_M) {
574 if (! old_proj_res) {
576 return; /* should not happen */
579 bl = get_nodes_block(load);
581 /* IncSP is typically scheduled after the load, so remove it first */
583 next = sched_next(old_proj_res);
584 sched_remove(old_proj_res);
587 reg = arch_get_irn_register(cg->arch_env, load);
588 sp = arch_get_irn_register(cg->arch_env, irn);
590 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
591 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
592 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
593 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
595 exchange(old_proj_M, proj_M);
596 exchange(old_proj_res, proj_res);
597 exchange(irn, proj_sp);
599 arch_set_irn_register(cg->arch_env, proj_res, reg);
600 arch_set_irn_register(cg->arch_env, proj_sp, sp);
602 sched_add_before(next, proj_sp);
603 sched_add_before(proj_sp, proj_res);
604 sched_add_before(proj_res,pop);
608 * Tries to optimize two following IncSP.
610 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
611 ir_node *prev = be_get_IncSP_pred(irn);
612 int real_uses = get_irn_n_edges(prev);
614 if (be_is_IncSP(prev) && real_uses == 1) {
615 /* first IncSP has only one IncSP user, kill the first one */
616 unsigned prev_offs = be_get_IncSP_offset(prev);
617 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
618 unsigned curr_offs = be_get_IncSP_offset(irn);
619 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
621 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
622 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
626 curr_dir = be_stack_dir_expand;
629 curr_dir = be_stack_dir_shrink;
630 be_set_IncSP_offset(prev, 0);
631 be_set_IncSP_offset(irn, (unsigned)new_ofs);
632 be_set_IncSP_direction(irn, curr_dir);
634 /* Omit the optimized IncSP */
635 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
640 * Performs Peephole Optimizations.
642 void ia32_peephole_optimization(ir_node *irn, void *env) {
643 ia32_code_gen_t *cg = env;
645 /* AMD CPUs want explicit compare before conditional jump */
646 if (! ARCH_AMD(cg->opt_arch)) {
647 if (is_ia32_TestJmp(irn))
648 ia32_optimize_TestJmp(irn, cg);
649 else if (is_ia32_CondJmp(irn))
650 ia32_optimize_CondJmp(irn, cg);
652 /* seems to be buggy when using Pushes */
653 else if (be_is_IncSP(irn))
654 ia32_optimize_IncSP(irn, cg);
655 else if (is_ia32_Store(irn))
656 ia32_create_Push(irn, cg);
661 /******************************************************************
663 * /\ | | | | | \/ | | |
664 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
665 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
666 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
667 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
669 ******************************************************************/
676 static int node_is_ia32_comm(const ir_node *irn) {
677 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
680 static int ia32_get_irn_n_edges(const ir_node *irn) {
681 const ir_edge_t *edge;
684 foreach_out_edge(irn, edge) {
692 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
694 * @param pred The node to be checked
695 * @param is_op_func The check-function
696 * @return 1 if conditions are fulfilled, 0 otherwise
698 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
699 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
707 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
708 * and if the predecessor is in block bl.
710 * @param bl The block
711 * @param pred The node to be checked
712 * @param is_op_func The check-function
713 * @return 1 if conditions are fulfilled, 0 otherwise
715 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
716 int (*is_op_func)(const ir_node *n))
719 pred = get_Proj_pred(pred);
720 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
729 * Checks if irn is a candidate for address calculation.
731 * - none of the operand must be a Load within the same block OR
732 * - all Loads must have more than one user OR
733 * - the irn has a frame entity (it's a former FrameAddr)
735 * @param block The block the Loads must/mustnot be in
736 * @param irn The irn to check
737 * return 1 if irn is a candidate, 0 otherwise
739 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
740 ir_node *in, *left, *right;
743 left = get_irn_n(irn, 2);
744 right = get_irn_n(irn, 3);
748 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
749 n = ia32_get_irn_n_edges(in);
750 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
755 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
756 n = ia32_get_irn_n_edges(in);
757 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
760 is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
766 * Checks if irn is a candidate for address mode.
769 * - at least one operand has to be a Load within the same block AND
770 * - the load must not have other users than the irn AND
771 * - the irn must not have a frame entity set
773 * @param cg The ia32 code generator
774 * @param h The height information of the irg
775 * @param block The block the Loads must/mustnot be in
776 * @param irn The irn to check
777 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
779 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
780 ir_node *in, *load, *other, *left, *right;
781 int n, is_cand = 0, cand;
783 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
784 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
787 left = get_irn_n(irn, 2);
788 right = get_irn_n(irn, 3);
792 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
793 n = ia32_get_irn_n_edges(in);
794 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
796 load = get_Proj_pred(in);
799 /* 8bit Loads are not supported, they cannot be used with every register */
800 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
803 /* If there is a data dependency of other irn from load: cannot use AM */
804 if (is_cand && get_nodes_block(other) == block) {
805 other = skip_Proj(other);
806 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
807 /* this could happen in loops */
808 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
812 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
816 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
817 n = ia32_get_irn_n_edges(in);
818 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
820 load = get_Proj_pred(in);
823 /* 8bit Loads are not supported, they cannot be used with every register */
824 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
827 /* If there is a data dependency of other irn from load: cannot use load */
828 if (is_cand && get_nodes_block(other) == block) {
829 other = skip_Proj(other);
830 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
831 /* this could happen in loops */
832 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
836 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
838 /* check some special cases */
839 if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
840 /* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
841 if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32)
842 cand = IA32_AM_CAND_NONE;
844 else if (is_ia32_Conv_I2I(irn)) {
845 /* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
846 if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn)))
847 cand = IA32_AM_CAND_NONE;
850 /* if the irn has a frame entity: we do not use address mode */
851 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
855 * Compares the base and index addr and the load/store entities
856 * and returns 1 if they are equal.
858 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
859 const ir_node *addr_b, const ir_node *addr_i)
861 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
862 entity *lent = get_ia32_frame_ent(load);
863 entity *sent = get_ia32_frame_ent(store);
864 ident *lid = get_ia32_am_sc(load);
865 ident *sid = get_ia32_am_sc(store);
866 char *loffs = get_ia32_am_offs(load);
867 char *soffs = get_ia32_am_offs(store);
869 /* are both entities set and equal? */
870 if (is_equal && (lent || sent))
871 is_equal = lent && sent && (lent == sent);
873 /* are address mode idents set and equal? */
874 if (is_equal && (lid || sid))
875 is_equal = lid && sid && (lid == sid);
877 /* are offsets set and equal */
878 if (is_equal && (loffs || soffs))
879 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
881 /* are the load and the store of the same mode? */
882 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
887 typedef enum _ia32_take_lea_attr {
888 IA32_LEA_ATTR_NONE = 0,
889 IA32_LEA_ATTR_BASE = (1 << 0),
890 IA32_LEA_ATTR_INDEX = (1 << 1),
891 IA32_LEA_ATTR_OFFS = (1 << 2),
892 IA32_LEA_ATTR_SCALE = (1 << 3),
893 IA32_LEA_ATTR_AMSC = (1 << 4),
894 IA32_LEA_ATTR_FENT = (1 << 5)
895 } ia32_take_lea_attr;
898 * Decides if we have to keep the LEA operand or if we can assimilate it.
900 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
901 int have_am_sc, ia32_code_gen_t *cg)
903 entity *irn_ent = get_ia32_frame_ent(irn);
904 entity *lea_ent = get_ia32_frame_ent(lea);
906 int is_noreg_base = be_is_NoReg(cg, base);
907 int is_noreg_index = be_is_NoReg(cg, index);
908 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
910 /* If the Add and the LEA both have a different frame entity set: keep */
911 if (irn_ent && lea_ent && (irn_ent != lea_ent))
912 return IA32_LEA_ATTR_NONE;
913 else if (! irn_ent && lea_ent)
914 ret_val |= IA32_LEA_ATTR_FENT;
916 /* If the Add and the LEA both have already an address mode symconst: keep */
917 if (have_am_sc && get_ia32_am_sc(lea))
918 return IA32_LEA_ATTR_NONE;
919 else if (get_ia32_am_sc(lea))
920 ret_val |= IA32_LEA_ATTR_AMSC;
922 /* Check the different base-index combinations */
924 if (! is_noreg_base && ! is_noreg_index) {
925 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
926 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
927 if (am_flav & ia32_O)
928 ret_val |= IA32_LEA_ATTR_OFFS;
930 ret_val |= IA32_LEA_ATTR_BASE;
933 return IA32_LEA_ATTR_NONE;
935 else if (! is_noreg_base && is_noreg_index) {
936 /* Base is set but index not */
938 /* Base points to LEA: assimilate everything */
939 if (am_flav & ia32_O)
940 ret_val |= IA32_LEA_ATTR_OFFS;
941 if (am_flav & ia32_S)
942 ret_val |= IA32_LEA_ATTR_SCALE;
943 if (am_flav & ia32_I)
944 ret_val |= IA32_LEA_ATTR_INDEX;
946 ret_val |= IA32_LEA_ATTR_BASE;
948 else if (am_flav & ia32_B ? 0 : 1) {
949 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
950 if (am_flav & ia32_O)
951 ret_val |= IA32_LEA_ATTR_OFFS;
952 if (am_flav & ia32_S)
953 ret_val |= IA32_LEA_ATTR_SCALE;
955 ret_val |= IA32_LEA_ATTR_INDEX;
958 return IA32_LEA_ATTR_NONE;
960 else if (is_noreg_base && ! is_noreg_index) {
961 /* Index is set but not base */
963 /* Index points to LEA: assimilate everything */
964 if (am_flav & ia32_O)
965 ret_val |= IA32_LEA_ATTR_OFFS;
966 if (am_flav & ia32_S)
967 ret_val |= IA32_LEA_ATTR_SCALE;
968 if (am_flav & ia32_B)
969 ret_val |= IA32_LEA_ATTR_BASE;
971 ret_val |= IA32_LEA_ATTR_INDEX;
973 else if (am_flav & ia32_I ? 0 : 1) {
974 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
975 if (am_flav & ia32_O)
976 ret_val |= IA32_LEA_ATTR_OFFS;
977 if (am_flav & ia32_S)
978 ret_val |= IA32_LEA_ATTR_SCALE;
980 ret_val |= IA32_LEA_ATTR_BASE;
983 return IA32_LEA_ATTR_NONE;
986 assert(0 && "There must have been set base or index");
993 * Adds res before irn into schedule if irn was scheduled.
994 * @param irn The schedule point
995 * @param res The node to be scheduled
997 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
998 if (sched_is_scheduled(irn))
999 sched_add_before(irn, res);
1003 * Removes irn from schedule if it was scheduled. If irn is a mode_T node
1004 * all it's Projs are removed as well.
1005 * @param irn The irn to be removed from schedule
1007 static INLINE void try_remove_from_sched(ir_node *irn) {
1008 if (sched_is_scheduled(irn)) {
1009 if (get_irn_mode(irn) == mode_T) {
1010 const ir_edge_t *edge;
1011 foreach_out_edge(irn, edge) {
1012 ir_node *proj = get_edge_src_irn(edge);
1013 if (sched_is_scheduled(proj))
1022 * Folds Add or Sub to LEA if possible
1024 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
1025 ir_graph *irg = get_irn_irg(irn);
1026 dbg_info *dbg = get_irn_dbg_info(irn);
1027 ir_node *block = get_nodes_block(irn);
1029 ir_node *shift = NULL;
1030 ir_node *lea_o = NULL;
1031 ir_node *lea = NULL;
1033 const char *offs_cnst = NULL;
1034 char *offs_lea = NULL;
1040 ident *am_sc = NULL;
1041 entity *lea_ent = NULL;
1042 ir_node *left, *right, *temp;
1043 ir_node *base, *index;
1044 ia32_am_flavour_t am_flav;
1045 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1047 if (is_ia32_Add(irn))
1050 left = get_irn_n(irn, 2);
1051 right = get_irn_n(irn, 3);
1053 /* "normalize" arguments in case of add with two operands */
1054 if (isadd && ! be_is_NoReg(cg, right)) {
1055 /* put LEA == ia32_am_O as right operand */
1056 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
1057 set_irn_n(irn, 2, right);
1058 set_irn_n(irn, 3, left);
1064 /* put LEA != ia32_am_O as left operand */
1065 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
1066 set_irn_n(irn, 2, right);
1067 set_irn_n(irn, 3, left);
1073 /* put SHL as left operand iff left is NOT a LEA */
1074 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
1075 set_irn_n(irn, 2, right);
1076 set_irn_n(irn, 3, left);
1089 /* check for operation with immediate */
1090 if (is_ia32_ImmConst(irn)) {
1091 DBG((mod, LEVEL_1, "\tfound op with imm const"));
1093 offs_cnst = get_ia32_cnst(irn);
1096 else if (is_ia32_ImmSymConst(irn)) {
1097 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
1101 am_sc = get_ia32_id_cnst(irn);
1102 am_sc_sign = is_ia32_am_sc_sign(irn);
1105 /* determine the operand which needs to be checked */
1106 temp = be_is_NoReg(cg, right) ? left : right;
1108 /* check if right operand is AMConst (LEA with ia32_am_O) */
1109 /* but we can only eat it up if there is no other symconst */
1110 /* because the linker won't accept two symconsts */
1111 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
1112 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
1114 offs_lea = get_ia32_am_offs(temp);
1115 am_sc = get_ia32_am_sc(temp);
1116 am_sc_sign = is_ia32_am_sc_sign(temp);
1123 else if (temp == right)
1128 /* default for add -> make right operand to index */
1132 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
1134 /* determine the operand which needs to be checked */
1136 if (is_ia32_Lea(left)) {
1140 /* check for SHL 1,2,3 */
1141 if (pred_is_specific_node(temp, is_ia32_Shl)) {
1142 temp = get_Proj_pred(temp);
1145 if (get_ia32_Immop_tarval(temp)) {
1146 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
1149 index = get_irn_n(temp, 2);
1151 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
1161 if (! be_is_NoReg(cg, index)) {
1162 /* if we have index, but left == right -> no base */
1163 if (left == right) {
1166 else if (! is_ia32_Lea(left) && (index != right)) {
1167 /* index != right -> we found a good Shl */
1168 /* left != LEA -> this Shl was the left operand */
1169 /* -> base is right operand */
1170 base = (right == lea_o) ? noreg : right;
1175 /* Try to assimilate a LEA as left operand */
1176 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1177 /* check if we can assimilate the LEA */
1178 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1180 if (take_attr == IA32_LEA_ATTR_NONE) {
1181 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1184 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1185 lea = left; /* for statistics */
1187 if (take_attr & IA32_LEA_ATTR_OFFS)
1188 offs = get_ia32_am_offs(left);
1190 if (take_attr & IA32_LEA_ATTR_AMSC) {
1191 am_sc = get_ia32_am_sc(left);
1193 am_sc_sign = is_ia32_am_sc_sign(left);
1196 if (take_attr & IA32_LEA_ATTR_SCALE)
1197 scale = get_ia32_am_scale(left);
1199 if (take_attr & IA32_LEA_ATTR_BASE)
1200 base = get_irn_n(left, 0);
1202 if (take_attr & IA32_LEA_ATTR_INDEX)
1203 index = get_irn_n(left, 1);
1205 if (take_attr & IA32_LEA_ATTR_FENT)
1206 lea_ent = get_ia32_frame_ent(left);
1210 /* ok, we can create a new LEA */
1212 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1214 /* add the old offset of a previous LEA */
1216 add_ia32_am_offs(res, offs);
1219 /* add the new offset */
1222 add_ia32_am_offs(res, offs_cnst);
1225 add_ia32_am_offs(res, offs_lea);
1229 /* either lea_O-cnst, -cnst or -lea_O */
1232 add_ia32_am_offs(res, offs_lea);
1235 sub_ia32_am_offs(res, offs_cnst);
1238 sub_ia32_am_offs(res, offs_lea);
1242 /* set the address mode symconst */
1244 set_ia32_am_sc(res, am_sc);
1246 set_ia32_am_sc_sign(res);
1249 /* copy the frame entity (could be set in case of Add */
1250 /* which was a FrameAddr) */
1252 set_ia32_frame_ent(res, lea_ent);
1254 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1256 if (get_ia32_frame_ent(res))
1257 set_ia32_use_frame(res);
1260 set_ia32_am_scale(res, scale);
1262 am_flav = ia32_am_N;
1263 /* determine new am flavour */
1264 if (offs || offs_cnst || offs_lea || have_am_sc) {
1267 if (! be_is_NoReg(cg, base)) {
1270 if (! be_is_NoReg(cg, index)) {
1276 set_ia32_am_flavour(res, am_flav);
1278 set_ia32_op_type(res, ia32_AddrModeS);
1280 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1282 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1284 /* we will exchange it, report here before the Proj is created */
1285 if (shift && lea && lea_o) {
1286 try_remove_from_sched(shift);
1287 try_remove_from_sched(lea);
1288 try_remove_from_sched(lea_o);
1289 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1291 else if (shift && lea) {
1292 try_remove_from_sched(shift);
1293 try_remove_from_sched(lea);
1294 DBG_OPT_LEA3(irn, lea, shift, res);
1296 else if (shift && lea_o) {
1297 try_remove_from_sched(shift);
1298 try_remove_from_sched(lea_o);
1299 DBG_OPT_LEA3(irn, lea_o, shift, res);
1301 else if (lea && lea_o) {
1302 try_remove_from_sched(lea);
1303 try_remove_from_sched(lea_o);
1304 DBG_OPT_LEA3(irn, lea_o, lea, res);
1307 try_remove_from_sched(shift);
1308 DBG_OPT_LEA2(irn, shift, res);
1311 try_remove_from_sched(lea);
1312 DBG_OPT_LEA2(irn, lea, res);
1315 try_remove_from_sched(lea_o);
1316 DBG_OPT_LEA2(irn, lea_o, res);
1319 DBG_OPT_LEA1(irn, res);
1321 /* get the result Proj of the Add/Sub */
1322 try_add_to_sched(irn, res);
1323 try_remove_from_sched(irn);
1324 irn = ia32_get_res_proj(irn);
1326 assert(irn && "Couldn't find result proj");
1328 /* exchange the old op with the new LEA */
1337 * Merges a Load/Store node with a LEA.
1338 * @param irn The Load/Store node
1339 * @param lea The LEA
1341 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1342 entity *irn_ent = get_ia32_frame_ent(irn);
1343 entity *lea_ent = get_ia32_frame_ent(lea);
1345 /* If the irn and the LEA both have a different frame entity set: do not merge */
1346 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1348 else if (! irn_ent && lea_ent) {
1349 set_ia32_frame_ent(irn, lea_ent);
1350 set_ia32_use_frame(irn);
1353 /* get the AM attributes from the LEA */
1354 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1355 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1356 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1358 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1359 if (is_ia32_am_sc_sign(lea))
1360 set_ia32_am_sc_sign(irn);
1362 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1364 /* set base and index */
1365 set_irn_n(irn, 0, get_irn_n(lea, 0));
1366 set_irn_n(irn, 1, get_irn_n(lea, 1));
1368 try_remove_from_sched(lea);
1370 /* clear remat flag */
1371 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1373 if (is_ia32_Ld(irn))
1374 DBG_OPT_LOAD_LEA(lea, irn);
1376 DBG_OPT_STORE_LEA(lea, irn);
1381 * Sets new_right index of irn to right and new_left index to left.
1382 * Also exchange left and right
1384 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1387 set_irn_n(irn, new_right, *right);
1388 set_irn_n(irn, new_left, *left);
1394 /* this is only needed for Compares, but currently ALL nodes
1395 * have this attribute :-) */
1396 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1400 * Performs address calculation optimization (create LEAs if possible)
1402 static void optimize_lea(ir_node *irn, void *env) {
1403 ia32_code_gen_t *cg = env;
1404 ir_node *block, *noreg_gp, *left, *right;
1406 if (! is_ia32_irn(irn))
1409 /* Following cases can occur: */
1410 /* - Sub (l, imm) -> LEA [base - offset] */
1411 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1412 /* - Add (l, imm) -> LEA [base + offset] */
1413 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1414 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1415 /* - Add (l, r) -> LEA [base + index * scale] */
1416 /* with scale > 1 iff l/r == shl (1,2,3) */
1418 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1419 left = get_irn_n(irn, 2);
1420 right = get_irn_n(irn, 3);
1421 block = get_nodes_block(irn);
1422 noreg_gp = ia32_new_NoReg_gp(cg);
1424 /* Do not try to create a LEA if one of the operands is a Load. */
1425 /* check is irn is a candidate for address calculation */
1426 if (is_addr_candidate(block, irn)) {
1429 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1430 res = fold_addr(cg, irn, noreg_gp);
1433 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1435 DB((cg->mod, LEVEL_1, "not transformed\n"));
1438 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1439 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1440 /* - Store -> LEA into Store } it might be better to keep the LEA */
1441 left = get_irn_n(irn, 0);
1443 if (is_ia32_Lea(left)) {
1444 const ir_edge_t *edge, *ne;
1447 /* merge all Loads/Stores connected to this LEA with the LEA */
1448 foreach_out_edge_safe(left, edge, ne) {
1449 src = get_edge_src_irn(edge);
1451 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1452 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1453 if (! is_ia32_got_lea(src))
1454 merge_loadstore_lea(src, left);
1455 set_ia32_got_lea(src);
1464 * Checks for address mode patterns and performs the
1465 * necessary transformations.
1466 * This function is called by a walker.
1468 static void optimize_am(ir_node *irn, void *env) {
1469 ia32_am_opt_env_t *am_opt_env = env;
1470 ia32_code_gen_t *cg = am_opt_env->cg;
1471 heights_t *h = am_opt_env->h;
1472 ir_node *block, *noreg_gp, *noreg_fp;
1473 ir_node *left, *right;
1474 ir_node *store, *load, *mem_proj;
1475 ir_node *succ, *addr_b, *addr_i;
1476 int check_am_src = 0;
1477 int need_exchange_on_fail = 0;
1478 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1480 if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1483 block = get_nodes_block(irn);
1484 noreg_gp = ia32_new_NoReg_gp(cg);
1485 noreg_fp = ia32_new_NoReg_fp(cg);
1487 DBG((mod, LEVEL_1, "checking for AM\n"));
1489 /* fold following patterns: */
1490 /* - op -> Load into AMop with am_Source */
1492 /* - op is am_Source capable AND */
1493 /* - the Load is only used by this op AND */
1494 /* - the Load is in the same block */
1495 /* - Store -> op -> Load into AMop with am_Dest */
1497 /* - op is am_Dest capable AND */
1498 /* - the Store uses the same address as the Load AND */
1499 /* - the Load is only used by this op AND */
1500 /* - the Load and Store are in the same block AND */
1501 /* - nobody else uses the result of the op */
1503 if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) {
1504 ia32_am_cand_t cand = is_am_candidate(cg, h, block, irn);
1505 ia32_am_cand_t orig_cand = cand;
1507 /* cand == 1: load is left; cand == 2: load is right; */
1509 if (cand == IA32_AM_CAND_NONE)
1512 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1514 left = get_irn_n(irn, 2);
1515 if (get_irn_arity(irn) == 4) {
1516 /* it's an "unary" operation */
1520 right = get_irn_n(irn, 3);
1523 /* normalize commutative ops */
1524 if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) {
1526 /* Assure that left operand is always a Load if there is one */
1527 /* because non-commutative ops can only use Dest AM if the left */
1528 /* operand is a load, so we only need to check left operand. */
1530 exchange_left_right(irn, &left, &right, 3, 2);
1531 need_exchange_on_fail = 1;
1533 /* now: load is right */
1534 cand = IA32_AM_CAND_LEFT;
1537 /* check for Store -> op -> Load */
1539 /* Store -> op -> Load optimization is only possible if supported by op */
1540 /* and if right operand is a Load */
1541 if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_LEFT))
1543 /* An address mode capable op always has a result Proj. */
1544 /* If this Proj is used by more than one other node, we don't need to */
1545 /* check further, otherwise we check for Store and remember the address, */
1546 /* the Store points to. */
1548 succ = ia32_get_res_proj(irn);
1549 assert(succ && "Couldn't find result proj");
1555 /* now check for users and Store */
1556 if (ia32_get_irn_n_edges(succ) == 1) {
1557 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1559 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1561 addr_b = get_irn_n(store, 0);
1562 addr_i = get_irn_n(store, 1);
1567 /* we found a Store as single user: Now check for Load */
1569 /* skip the Proj for easier access */
1570 load = is_Proj(right) ? (is_ia32_Load(get_Proj_pred(right)) ? get_Proj_pred(right) : NULL) : NULL;
1572 /* Extra check for commutative ops with two Loads */
1573 /* -> put the interesting Load left */
1574 if (load && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) {
1575 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1576 /* We exchange left and right, so it's easier to kill */
1577 /* the correct Load later and to handle unary operations. */
1578 exchange_left_right(irn, &left, &right, 3, 2);
1579 need_exchange_on_fail ^= 1;
1583 /* skip the Proj for easier access */
1584 load = get_Proj_pred(left);
1586 /* Compare Load and Store address */
1587 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1588 /* Left Load is from same address, so we can */
1589 /* disconnect the Load and Store here */
1591 /* set new base, index and attributes */
1592 set_irn_n(irn, 0, addr_b);
1593 set_irn_n(irn, 1, addr_i);
1594 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1595 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1596 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1597 set_ia32_op_type(irn, ia32_AddrModeD);
1598 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1599 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1601 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1602 if (is_ia32_am_sc_sign(load))
1603 set_ia32_am_sc_sign(irn);
1605 if (is_ia32_use_frame(load))
1606 set_ia32_use_frame(irn);
1608 /* connect to Load memory and disconnect Load */
1609 if (get_irn_arity(irn) == 5) {
1611 set_irn_n(irn, 4, get_irn_n(load, 2));
1612 set_irn_n(irn, 2, noreg_gp);
1616 set_irn_n(irn, 3, get_irn_n(load, 2));
1617 set_irn_n(irn, 2, noreg_gp);
1620 /* connect the memory Proj of the Store to the op */
1621 mem_proj = ia32_get_proj_for_mode(store, mode_M);
1622 set_Proj_pred(mem_proj, irn);
1623 set_Proj_proj(mem_proj, 1);
1625 /* clear remat flag */
1626 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1628 try_remove_from_sched(load);
1629 try_remove_from_sched(store);
1630 DBG_OPT_AM_D(load, store, irn);
1632 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1634 need_exchange_on_fail = 0;
1637 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1638 /* There was no store, check if we still can optimize for source address mode */
1641 } /* if (support AM Dest) */
1642 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1643 /* op doesn't support am AM Dest -> check for AM Source */
1647 /* was exchanged but optimize failed: exchange back */
1648 if (need_exchange_on_fail) {
1649 exchange_left_right(irn, &left, &right, 3, 2);
1653 need_exchange_on_fail = 0;
1655 /* normalize commutative ops */
1656 if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) {
1658 /* Assure that right operand is always a Load if there is one */
1659 /* because non-commutative ops can only use Source AM if the */
1660 /* right operand is a Load, so we only need to check the right */
1661 /* operand afterwards. */
1663 exchange_left_right(irn, &left, &right, 3, 2);
1664 need_exchange_on_fail = 1;
1666 /* now: load is left */
1667 cand = IA32_AM_CAND_RIGHT;
1670 /* optimize op -> Load iff Load is only used by this op */
1671 /* and right operand is a Load which only used by this irn */
1673 (cand & IA32_AM_CAND_RIGHT) &&
1674 (get_irn_arity(irn) == 5) &&
1675 (ia32_get_irn_n_edges(right) == 1))
1677 right = get_Proj_pred(right);
1679 addr_b = get_irn_n(right, 0);
1680 addr_i = get_irn_n(right, 1);
1682 /* set new base, index and attributes */
1683 set_irn_n(irn, 0, addr_b);
1684 set_irn_n(irn, 1, addr_i);
1685 add_ia32_am_offs(irn, get_ia32_am_offs(right));
1686 set_ia32_am_scale(irn, get_ia32_am_scale(right));
1687 set_ia32_am_flavour(irn, get_ia32_am_flavour(right));
1688 set_ia32_op_type(irn, ia32_AddrModeS);
1689 set_ia32_frame_ent(irn, get_ia32_frame_ent(right));
1690 set_ia32_ls_mode(irn, get_ia32_ls_mode(right));
1692 set_ia32_am_sc(irn, get_ia32_am_sc(right));
1693 if (is_ia32_am_sc_sign(right))
1694 set_ia32_am_sc_sign(irn);
1696 /* clear remat flag */
1697 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1699 if (is_ia32_use_frame(right))
1700 set_ia32_use_frame(irn);
1702 /* connect to Load memory */
1703 set_irn_n(irn, 4, get_irn_n(right, 2));
1705 /* this is only needed for Compares, but currently ALL nodes
1706 * have this attribute :-) */
1707 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1709 /* disconnect from Load */
1710 set_irn_n(irn, 3, noreg_gp);
1712 DBG_OPT_AM_S(right, irn);
1714 /* If Load has a memory Proj, connect it to the op */
1715 mem_proj = ia32_get_proj_for_mode(right, mode_M);
1717 set_Proj_pred(mem_proj, irn);
1718 set_Proj_proj(mem_proj, 1);
1721 try_remove_from_sched(right);
1723 DB((mod, LEVEL_1, "merged with %+F into source AM\n", right));
1726 /* was exchanged but optimize failed: exchange back */
1727 if (need_exchange_on_fail)
1728 exchange_left_right(irn, &left, &right, 3, 2);
1734 * Performs address mode optimization.
1736 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1737 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1738 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1739 edges_deactivate(cg->irg);
1740 edges_activate(cg->irg);
1743 /* no optimizations at all */
1747 /* beware: we cannot optimize LEA and AM in one run because */
1748 /* LEA optimization adds new nodes to the irg which */
1749 /* invalidates the phase data */
1751 if (cg->opt & IA32_OPT_LEA) {
1752 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1756 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1758 if (cg->opt & IA32_OPT_DOAM) {
1759 /* we need height information for am optimization */
1760 heights_t *h = heights_new(cg->irg);
1761 ia32_am_opt_env_t env;
1766 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);