2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
45 #include "../benode.h"
46 #include "../besched.h"
47 #include "../bepeephole.h"
49 #include "ia32_new_nodes.h"
50 #include "ia32_optimize.h"
51 #include "bearch_ia32_t.h"
52 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_common_transform.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static ia32_code_gen_t *cg;
63 static void copy_mark(const ir_node *old, ir_node *new)
65 if (is_ia32_is_reload(old))
66 set_ia32_is_reload(new);
67 if (is_ia32_is_spill(old))
68 set_ia32_is_spill(new);
69 if (is_ia32_is_remat(old))
70 set_ia32_is_remat(new);
73 typedef enum produces_flag_t {
80 * Return which usable flag the given node produces
82 * @param node the node to check
83 * @param pn the projection number of the used result
85 static produces_flag_t produces_test_flag(ir_node *node, int pn)
88 const ia32_immediate_attr_t *imm_attr;
90 if (!is_ia32_irn(node))
91 return produces_no_flag;
93 switch (get_ia32_irn_opcode(node)) {
108 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
109 count = get_irn_n(node, n_ia32_ShlD_count);
110 goto check_shift_amount;
115 assert(n_ia32_Shl_count == n_ia32_Shr_count
116 && n_ia32_Shl_count == n_ia32_Sar_count);
117 count = get_irn_n(node, n_ia32_Shl_count);
119 /* when shift count is zero the flags are not affected, so we can only
120 * do this for constants != 0 */
121 if (!is_ia32_Immediate(count))
122 return produces_no_flag;
124 imm_attr = get_ia32_immediate_attr_const(count);
125 if (imm_attr->symconst != NULL)
126 return produces_no_flag;
127 if ((imm_attr->offset & 0x1f) == 0)
128 return produces_no_flag;
132 return pn == pn_ia32_Mul_res_high ?
133 produces_flag_carry : produces_no_flag;
136 return produces_no_flag;
139 return pn == pn_ia32_res ?
140 produces_flag_zero : produces_no_flag;
144 * Replace Cmp(x, 0) by a Test(x, x)
146 static void peephole_ia32_Cmp(ir_node *const node)
149 ia32_immediate_attr_t const *imm;
155 ia32_attr_t const *attr;
159 arch_register_t const *reg;
160 ir_edge_t const *edge;
161 ir_edge_t const *tmp;
163 if (get_ia32_op_type(node) != ia32_Normal)
166 right = get_irn_n(node, n_ia32_Cmp_right);
167 if (!is_ia32_Immediate(right))
170 imm = get_ia32_immediate_attr_const(right);
171 if (imm->symconst != NULL || imm->offset != 0)
174 dbgi = get_irn_dbg_info(node);
175 block = get_nodes_block(node);
176 noreg = ia32_new_NoReg_gp(cg);
177 nomem = get_irg_no_mem(current_ir_graph);
178 op = get_irn_n(node, n_ia32_Cmp_left);
179 attr = get_irn_generic_attr(node);
180 ins_permuted = attr->data.ins_permuted;
181 cmp_unsigned = attr->data.cmp_unsigned;
183 if (is_ia32_Cmp(node)) {
184 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
185 op, op, ins_permuted, cmp_unsigned);
187 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
188 op, op, ins_permuted, cmp_unsigned);
190 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
192 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
193 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
195 foreach_out_edge_safe(node, edge, tmp) {
196 ir_node *const user = get_edge_src_irn(edge);
199 exchange(user, test);
202 sched_add_before(node, test);
203 copy_mark(node, test);
204 be_peephole_exchange(node, test);
208 * Peephole optimization for Test instructions.
209 * - Remove the Test, if an appropriate flag was produced which is still live
210 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
212 static void peephole_ia32_Test(ir_node *node)
214 ir_node *left = get_irn_n(node, n_ia32_Test_left);
215 ir_node *right = get_irn_n(node, n_ia32_Test_right);
217 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
218 && n_ia32_Test_right == n_ia32_Test8Bit_right);
220 if (left == right) { /* we need a test for 0 */
221 ir_node *block = get_nodes_block(node);
222 int pn = pn_ia32_res;
226 const ir_edge_t *edge;
228 if (get_nodes_block(left) != block)
232 pn = get_Proj_proj(left);
233 left = get_Proj_pred(left);
236 /* walk schedule up and abort when we find left or some other node
237 * destroys the flags */
240 schedpoint = sched_prev(schedpoint);
241 if (schedpoint == left)
243 if (arch_irn_is(schedpoint, modify_flags))
245 if (schedpoint == block)
246 panic("couldn't find left");
249 /* make sure only Lg/Eq tests are used */
250 foreach_out_edge(node, edge) {
251 ir_node *user = get_edge_src_irn(edge);
252 int pnc = get_ia32_condcode(user);
254 if (pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
259 switch (produces_test_flag(left, pn)) {
260 case produces_flag_zero:
263 case produces_flag_carry:
264 foreach_out_edge(node, edge) {
265 ir_node *user = get_edge_src_irn(edge);
266 int pnc = get_ia32_condcode(user);
269 case pn_Cmp_Eq: pnc = ia32_pn_Cmp_not_carry; break;
270 case pn_Cmp_Lg: pnc = ia32_pn_Cmp_carry; break;
271 default: panic("unexpected pn");
273 set_ia32_condcode(user, pnc);
281 if (get_irn_mode(left) != mode_T) {
282 set_irn_mode(left, mode_T);
284 /* If there are other users, reroute them to result proj */
285 if (get_irn_n_edges(left) != 2) {
286 ir_node *res = new_r_Proj(left, mode_Iu, pn_ia32_res);
288 edges_reroute(left, res, current_ir_graph);
289 /* Reattach the result proj to left */
290 set_Proj_pred(res, left);
294 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
295 flags_proj = new_r_Proj(left, flags_mode, pn_ia32_flags);
296 arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
298 assert(get_irn_mode(node) != mode_T);
300 be_peephole_exchange(node, flags_proj);
301 } else if (is_ia32_Immediate(right)) {
302 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
305 /* A test with a symconst is rather strange, but better safe than sorry */
306 if (imm->symconst != NULL)
309 offset = imm->offset;
310 if (get_ia32_op_type(node) == ia32_AddrModeS) {
311 ia32_attr_t *const attr = get_irn_generic_attr(node);
313 if ((offset & 0xFFFFFF00) == 0) {
314 /* attr->am_offs += 0; */
315 } else if ((offset & 0xFFFF00FF) == 0) {
316 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
317 set_irn_n(node, n_ia32_Test_right, imm);
319 } else if ((offset & 0xFF00FFFF) == 0) {
320 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
321 set_irn_n(node, n_ia32_Test_right, imm);
323 } else if ((offset & 0x00FFFFFF) == 0) {
324 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
325 set_irn_n(node, n_ia32_Test_right, imm);
330 } else if (offset < 256) {
331 arch_register_t const* const reg = arch_get_irn_register(left);
333 if (reg != &ia32_gp_regs[REG_EAX] &&
334 reg != &ia32_gp_regs[REG_EBX] &&
335 reg != &ia32_gp_regs[REG_ECX] &&
336 reg != &ia32_gp_regs[REG_EDX]) {
343 /* Technically we should build a Test8Bit because of the register
344 * constraints, but nobody changes registers at this point anymore. */
345 set_ia32_ls_mode(node, mode_Bu);
350 * AMD Athlon works faster when RET is not destination of
351 * conditional jump or directly preceded by other jump instruction.
352 * Can be avoided by placing a Rep prefix before the return.
354 static void peephole_ia32_Return(ir_node *node)
356 ir_node *block, *irn;
358 if (!ia32_cg_config.use_pad_return)
361 block = get_nodes_block(node);
363 /* check if this return is the first on the block */
364 sched_foreach_reverse_from(node, irn) {
365 switch (get_irn_opcode(irn)) {
367 /* the return node itself, ignore */
372 /* ignore no code generated */
375 /* arg, IncSP 0 nodes might occur, ignore these */
376 if (be_get_IncSP_offset(irn) == 0)
386 /* ensure, that the 3 byte return is generated */
387 be_Return_set_emit_pop(node, 1);
390 /* only optimize up to 48 stores behind IncSPs */
391 #define MAXPUSH_OPTIMIZE 48
394 * Tries to create Push's from IncSP, Store combinations.
395 * The Stores are replaced by Push's, the IncSP is modified
396 * (possibly into IncSP 0, but not removed).
398 static void peephole_IncSP_Store_to_push(ir_node *irn)
404 ir_node *stores[MAXPUSH_OPTIMIZE];
409 ir_node *first_push = NULL;
410 ir_edge_t const *edge;
411 ir_edge_t const *next;
413 memset(stores, 0, sizeof(stores));
415 assert(be_is_IncSP(irn));
417 inc_ofs = be_get_IncSP_offset(irn);
422 * We first walk the schedule after the IncSP node as long as we find
423 * suitable Stores that could be transformed to a Push.
424 * We save them into the stores array which is sorted by the frame offset/4
425 * attached to the node
428 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
433 /* it has to be a Store */
434 if (!is_ia32_Store(node))
437 /* it has to use our sp value */
438 if (get_irn_n(node, n_ia32_base) != irn)
440 /* Store has to be attached to NoMem */
441 mem = get_irn_n(node, n_ia32_mem);
445 /* unfortunately we can't support the full AMs possible for push at the
446 * moment. TODO: fix this */
447 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
450 offset = get_ia32_am_offs_int(node);
451 /* we should NEVER access uninitialized stack BELOW the current SP */
454 /* storing at half-slots is bad */
455 if ((offset & 3) != 0)
458 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
460 storeslot = offset >> 2;
462 /* storing into the same slot twice is bad (and shouldn't happen...) */
463 if (stores[storeslot] != NULL)
466 stores[storeslot] = node;
467 if (storeslot > maxslot)
473 for (i = -1; i < maxslot; ++i) {
474 if (stores[i + 1] == NULL)
478 /* walk through the Stores and create Pushs for them */
479 block = get_nodes_block(irn);
480 spmode = get_irn_mode(irn);
482 for (; i >= 0; --i) {
483 const arch_register_t *spreg;
485 ir_node *val, *mem, *mem_proj;
486 ir_node *store = stores[i];
487 ir_node *noreg = ia32_new_NoReg_gp(cg);
489 val = get_irn_n(store, n_ia32_unary_op);
490 mem = get_irn_n(store, n_ia32_mem);
491 spreg = arch_get_irn_register(curr_sp);
493 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
494 copy_mark(store, push);
496 if (first_push == NULL)
499 sched_add_after(skip_Proj(curr_sp), push);
501 /* create stackpointer Proj */
502 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
503 arch_set_irn_register(curr_sp, spreg);
505 /* create memory Proj */
506 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
508 /* use the memproj now */
509 be_peephole_exchange(store, mem_proj);
514 foreach_out_edge_safe(irn, edge, next) {
515 ir_node *const src = get_edge_src_irn(edge);
516 int const pos = get_edge_src_pos(edge);
518 if (src == first_push)
521 set_irn_n(src, pos, curr_sp);
524 be_set_IncSP_offset(irn, inc_ofs);
529 * Creates a Push instruction before the given schedule point.
531 * @param dbgi debug info
532 * @param block the block
533 * @param stack the previous stack value
534 * @param schedpoint the new node is added before this node
535 * @param reg the register to pop
537 * @return the new stack value
539 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
540 ir_node *stack, ir_node *schedpoint)
542 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
544 ir_node *val = ia32_new_NoReg_gp(cg);
545 ir_node *noreg = ia32_new_NoReg_gp(cg);
546 ir_node *nomem = new_NoMem();
547 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
548 sched_add_before(schedpoint, push);
550 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
551 arch_set_irn_register(stack, esp);
556 static void peephole_store_incsp(ir_node *store)
567 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
568 if (!be_is_IncSP(am_base)
569 || get_nodes_block(am_base) != get_nodes_block(store))
571 mem = get_irn_n(store, n_ia32_Store_mem);
572 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
576 int incsp_offset = be_get_IncSP_offset(am_base);
577 if (incsp_offset <= 0)
580 /* we have to be at offset 0 */
581 int my_offset = get_ia32_am_offs_int(store);
582 if (my_offset != 0) {
583 /* TODO here: find out wether there is a store with offset 0 before
584 * us and wether we can move it down to our place */
587 ir_mode *ls_mode = get_ia32_ls_mode(store);
588 int my_store_size = get_mode_size_bytes(ls_mode);
590 if (my_offset + my_store_size > incsp_offset)
593 /* correctness checking:
594 - noone else must write to that stackslot
595 (because after translation incsp won't allocate it anymore)
597 sched_foreach_reverse_from(store, node) {
603 /* make sure noone else can use the space on the stack */
604 arity = get_irn_arity(node);
605 for (i = 0; i < arity; ++i) {
606 ir_node *pred = get_irn_n(node, i);
610 if (i == n_ia32_base &&
611 (get_ia32_op_type(node) == ia32_AddrModeS
612 || get_ia32_op_type(node) == ia32_AddrModeD)) {
613 int node_offset = get_ia32_am_offs_int(node);
614 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
615 int node_size = get_mode_size_bytes(node_ls_mode);
616 /* overlapping with our position? abort */
617 if (node_offset < my_offset + my_store_size
618 && node_offset + node_size >= my_offset)
620 /* otherwise it's fine */
624 /* strange use of esp: abort */
629 /* all ok, change to push */
630 dbgi = get_irn_dbg_info(store);
631 block = get_nodes_block(store);
632 noreg = ia32_new_NoReg_gp(cg);
633 val = get_irn_n(store, n_ia32_Store_val);
635 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
637 create_push(dbgi, current_ir_graph, block, am_base, store);
642 * Return true if a mode can be stored in the GP register set
644 static inline int mode_needs_gp_reg(ir_mode *mode)
646 if (mode == mode_fpcw)
648 if (get_mode_size_bits(mode) > 32)
650 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
654 * Tries to create Pops from Load, IncSP combinations.
655 * The Loads are replaced by Pops, the IncSP is modified
656 * (possibly into IncSP 0, but not removed).
658 static void peephole_Load_IncSP_to_pop(ir_node *irn)
660 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
661 int i, maxslot, inc_ofs, ofs;
662 ir_node *node, *pred_sp, *block;
663 ir_node *loads[MAXPUSH_OPTIMIZE];
665 unsigned regmask = 0;
666 unsigned copymask = ~0;
668 memset(loads, 0, sizeof(loads));
669 assert(be_is_IncSP(irn));
671 inc_ofs = -be_get_IncSP_offset(irn);
676 * We first walk the schedule before the IncSP node as long as we find
677 * suitable Loads that could be transformed to a Pop.
678 * We save them into the stores array which is sorted by the frame offset/4
679 * attached to the node
682 pred_sp = be_get_IncSP_pred(irn);
683 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
686 const arch_register_t *sreg, *dreg;
688 /* it has to be a Load */
689 if (!is_ia32_Load(node)) {
690 if (be_is_Copy(node)) {
691 if (!mode_needs_gp_reg(get_irn_mode(node))) {
692 /* not a GP copy, ignore */
695 dreg = arch_get_irn_register(node);
696 sreg = arch_get_irn_register(be_get_Copy_op(node));
697 if (regmask & copymask & (1 << sreg->index)) {
700 if (regmask & copymask & (1 << dreg->index)) {
703 /* we CAN skip Copies if neither the destination nor the source
704 * is not in our regmask, ie none of our future Pop will overwrite it */
705 regmask |= (1 << dreg->index) | (1 << sreg->index);
706 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
712 /* we can handle only GP loads */
713 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
716 /* it has to use our predecessor sp value */
717 if (get_irn_n(node, n_ia32_base) != pred_sp) {
718 /* it would be ok if this load does not use a Pop result,
719 * but we do not check this */
723 /* should have NO index */
724 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
727 offset = get_ia32_am_offs_int(node);
728 /* we should NEVER access uninitialized stack BELOW the current SP */
731 /* storing at half-slots is bad */
732 if ((offset & 3) != 0)
735 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
737 /* ignore those outside the possible windows */
738 if (offset > inc_ofs - 4)
740 loadslot = offset >> 2;
742 /* loading from the same slot twice is bad (and shouldn't happen...) */
743 if (loads[loadslot] != NULL)
746 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
747 if (regmask & (1 << dreg->index)) {
748 /* this register is already used */
751 regmask |= 1 << dreg->index;
753 loads[loadslot] = node;
754 if (loadslot > maxslot)
761 /* find the first slot */
762 for (i = maxslot; i >= 0; --i) {
763 ir_node *load = loads[i];
769 ofs = inc_ofs - (maxslot + 1) * 4;
772 /* create a new IncSP if needed */
773 block = get_nodes_block(irn);
776 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
777 sched_add_before(irn, pred_sp);
780 /* walk through the Loads and create Pops for them */
781 for (++i; i <= maxslot; ++i) {
782 ir_node *load = loads[i];
784 const ir_edge_t *edge, *tmp;
785 const arch_register_t *reg;
787 mem = get_irn_n(load, n_ia32_mem);
788 reg = arch_irn_get_register(load, pn_ia32_Load_res);
790 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
791 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
793 copy_mark(load, pop);
795 /* create stackpointer Proj */
796 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
797 arch_set_irn_register(pred_sp, esp);
799 sched_add_before(irn, pop);
802 foreach_out_edge_safe(load, edge, tmp) {
803 ir_node *proj = get_edge_src_irn(edge);
805 set_Proj_pred(proj, pop);
808 /* we can remove the Load now */
813 be_set_IncSP_offset(irn, -ofs);
814 be_set_IncSP_pred(irn, pred_sp);
819 * Find a free GP register if possible, else return NULL.
821 static const arch_register_t *get_free_gp_reg(void)
825 for (i = 0; i < N_ia32_gp_REGS; ++i) {
826 const arch_register_t *reg = &ia32_gp_regs[i];
827 if (arch_register_type_is(reg, ignore))
830 if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
831 return &ia32_gp_regs[i];
838 * Creates a Pop instruction before the given schedule point.
840 * @param dbgi debug info
841 * @param block the block
842 * @param stack the previous stack value
843 * @param schedpoint the new node is added before this node
844 * @param reg the register to pop
846 * @return the new stack value
848 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
849 ir_node *stack, ir_node *schedpoint,
850 const arch_register_t *reg)
852 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
858 pop = new_bd_ia32_Pop(dbgi, block, new_NoMem(), stack);
860 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
861 arch_set_irn_register(stack, esp);
862 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
863 arch_set_irn_register(val, reg);
865 sched_add_before(schedpoint, pop);
868 keep = be_new_Keep(block, 1, in);
869 sched_add_before(schedpoint, keep);
875 * Optimize an IncSp by replacing it with Push/Pop.
877 static void peephole_be_IncSP(ir_node *node)
879 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
880 const arch_register_t *reg;
886 /* first optimize incsp->incsp combinations */
887 node = be_peephole_IncSP_IncSP(node);
889 /* transform IncSP->Store combinations to Push where possible */
890 peephole_IncSP_Store_to_push(node);
892 /* transform Load->IncSP combinations to Pop where possible */
893 peephole_Load_IncSP_to_pop(node);
895 if (arch_get_irn_register(node) != esp)
898 /* replace IncSP -4 by Pop freereg when possible */
899 offset = be_get_IncSP_offset(node);
900 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
901 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
902 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
903 (offset != +8 || ia32_cg_config.use_sub_esp_8))
907 /* we need a free register for pop */
908 reg = get_free_gp_reg();
912 dbgi = get_irn_dbg_info(node);
913 block = get_nodes_block(node);
914 stack = be_get_IncSP_pred(node);
916 stack = create_pop(dbgi, block, stack, node, reg);
919 stack = create_pop(dbgi, block, stack, node, reg);
922 dbgi = get_irn_dbg_info(node);
923 block = get_nodes_block(node);
924 stack = be_get_IncSP_pred(node);
925 stack = new_bd_ia32_PushEax(dbgi, block, stack);
926 arch_set_irn_register(stack, esp);
927 sched_add_before(node, stack);
930 stack = new_bd_ia32_PushEax(dbgi, block, stack);
931 arch_set_irn_register(stack, esp);
932 sched_add_before(node, stack);
936 be_peephole_exchange(node, stack);
940 * Peephole optimisation for ia32_Const's
942 static void peephole_ia32_Const(ir_node *node)
944 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
945 const arch_register_t *reg;
950 /* try to transform a mov 0, reg to xor reg reg */
951 if (attr->offset != 0 || attr->symconst != NULL)
953 if (ia32_cg_config.use_mov_0)
955 /* xor destroys the flags, so no-one must be using them */
956 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
959 reg = arch_get_irn_register(node);
960 assert(be_peephole_get_reg_value(reg) == NULL);
962 /* create xor(produceval, produceval) */
963 block = get_nodes_block(node);
964 dbgi = get_irn_dbg_info(node);
965 xor = new_bd_ia32_Xor0(dbgi, block);
966 arch_set_irn_register(xor, reg);
968 sched_add_before(node, xor);
970 copy_mark(node, xor);
971 be_peephole_exchange(node, xor);
974 static inline int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
976 return node == cg->noreg_gp;
979 ir_node *ia32_immediate_from_long(long val)
981 ir_graph *irg = current_ir_graph;
982 ir_node *start_block = get_irg_start_block(irg);
984 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
985 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
990 static ir_node *create_immediate_from_am(const ir_node *node)
992 ir_node *block = get_nodes_block(node);
993 int offset = get_ia32_am_offs_int(node);
994 int sc_sign = is_ia32_am_sc_sign(node);
995 const ia32_attr_t *attr = get_ia32_attr_const(node);
996 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
997 ir_entity *entity = get_ia32_am_sc(node);
1000 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1002 arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
1006 static int is_am_one(const ir_node *node)
1008 int offset = get_ia32_am_offs_int(node);
1009 ir_entity *entity = get_ia32_am_sc(node);
1011 return offset == 1 && entity == NULL;
1014 static int is_am_minus_one(const ir_node *node)
1016 int offset = get_ia32_am_offs_int(node);
1017 ir_entity *entity = get_ia32_am_sc(node);
1019 return offset == -1 && entity == NULL;
1023 * Transforms a LEA into an Add or SHL if possible.
1025 static void peephole_ia32_Lea(ir_node *node)
1029 const arch_register_t *base_reg;
1030 const arch_register_t *index_reg;
1031 const arch_register_t *out_reg;
1042 assert(is_ia32_Lea(node));
1044 /* we can only do this if it is allowed to clobber the flags */
1045 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1048 base = get_irn_n(node, n_ia32_Lea_base);
1049 index = get_irn_n(node, n_ia32_Lea_index);
1051 if (is_noreg(cg, base)) {
1055 base_reg = arch_get_irn_register(base);
1057 if (is_noreg(cg, index)) {
1061 index_reg = arch_get_irn_register(index);
1064 if (base == NULL && index == NULL) {
1065 /* we shouldn't construct these in the first place... */
1066 #ifdef DEBUG_libfirm
1067 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1072 out_reg = arch_get_irn_register(node);
1073 scale = get_ia32_am_scale(node);
1074 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1075 /* check if we have immediates values (frame entities should already be
1076 * expressed in the offsets) */
1077 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1083 /* we can transform leas where the out register is the same as either the
1084 * base or index register back to an Add or Shl */
1085 if (out_reg == base_reg) {
1086 if (index == NULL) {
1087 #ifdef DEBUG_libfirm
1088 if (!has_immediates) {
1089 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1094 goto make_add_immediate;
1096 if (scale == 0 && !has_immediates) {
1101 /* can't create an add */
1103 } else if (out_reg == index_reg) {
1105 if (has_immediates && scale == 0) {
1107 goto make_add_immediate;
1108 } else if (!has_immediates && scale > 0) {
1110 op2 = ia32_immediate_from_long(scale);
1112 } else if (!has_immediates) {
1113 #ifdef DEBUG_libfirm
1114 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1118 } else if (scale == 0 && !has_immediates) {
1123 /* can't create an add */
1126 /* can't create an add */
1131 if (ia32_cg_config.use_incdec) {
1132 if (is_am_one(node)) {
1133 dbgi = get_irn_dbg_info(node);
1134 block = get_nodes_block(node);
1135 res = new_bd_ia32_Inc(dbgi, block, op1);
1136 arch_set_irn_register(res, out_reg);
1139 if (is_am_minus_one(node)) {
1140 dbgi = get_irn_dbg_info(node);
1141 block = get_nodes_block(node);
1142 res = new_bd_ia32_Dec(dbgi, block, op1);
1143 arch_set_irn_register(res, out_reg);
1147 op2 = create_immediate_from_am(node);
1150 dbgi = get_irn_dbg_info(node);
1151 block = get_nodes_block(node);
1152 noreg = ia32_new_NoReg_gp(cg);
1153 nomem = new_NoMem();
1154 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1155 arch_set_irn_register(res, out_reg);
1156 set_ia32_commutative(res);
1160 dbgi = get_irn_dbg_info(node);
1161 block = get_nodes_block(node);
1162 noreg = ia32_new_NoReg_gp(cg);
1163 nomem = new_NoMem();
1164 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1165 arch_set_irn_register(res, out_reg);
1169 SET_IA32_ORIG_NODE(res, node);
1171 /* add new ADD/SHL to schedule */
1172 DBG_OPT_LEA2ADD(node, res);
1174 /* exchange the Add and the LEA */
1175 sched_add_before(node, res);
1176 copy_mark(node, res);
1177 be_peephole_exchange(node, res);
1181 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1183 static void peephole_ia32_Imul_split(ir_node *imul)
1185 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1186 const arch_register_t *reg;
1189 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1190 /* no memory, imm form ignore */
1193 /* we need a free register */
1194 reg = get_free_gp_reg();
1198 /* fine, we can rebuild it */
1199 res = turn_back_am(imul);
1200 arch_set_irn_register(res, reg);
1204 * Replace xorps r,r and xorpd r,r by pxor r,r
1206 static void peephole_ia32_xZero(ir_node *xor)
1208 set_irn_op(xor, op_ia32_xPzero);
1212 * Replace 16bit sign extension from ax to eax by shorter cwtl
1214 static void peephole_ia32_Conv_I2I(ir_node *node)
1216 const arch_register_t *eax = &ia32_gp_regs[REG_EAX];
1217 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1218 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1223 if (get_mode_size_bits(smaller_mode) != 16 ||
1224 !mode_is_signed(smaller_mode) ||
1225 eax != arch_get_irn_register(val) ||
1226 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1229 dbgi = get_irn_dbg_info(node);
1230 block = get_nodes_block(node);
1231 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1232 arch_set_irn_register(cwtl, eax);
1233 sched_add_before(node, cwtl);
1234 be_peephole_exchange(node, cwtl);
1238 * Register a peephole optimisation function.
1240 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1242 assert(op->ops.generic == NULL);
1243 op->ops.generic = (op_func)func;
1246 /* Perform peephole-optimizations. */
1247 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1251 /* register peephole optimisations */
1252 clear_irp_opcodes_generic_func();
1253 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1254 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1255 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1256 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1257 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1258 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1259 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1260 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1261 if (! ia32_cg_config.use_imul_mem_imm32)
1262 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1263 if (ia32_cg_config.use_pxor)
1264 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1265 if (ia32_cg_config.use_short_sex_eax)
1266 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1268 be_peephole_opt(cg->irg);
1272 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1273 * all it's Projs are removed as well.
1274 * @param irn The irn to be removed from schedule
1276 static inline void try_kill(ir_node *node)
1278 if (get_irn_mode(node) == mode_T) {
1279 const ir_edge_t *edge, *next;
1280 foreach_out_edge_safe(node, edge, next) {
1281 ir_node *proj = get_edge_src_irn(edge);
1286 if (get_irn_n_edges(node) != 0)
1289 if (sched_is_scheduled(node)) {
1296 static void optimize_conv_store(ir_node *node)
1301 ir_mode *store_mode;
1303 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1306 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1307 pred_proj = get_irn_n(node, n_ia32_Store_val);
1308 if (is_Proj(pred_proj)) {
1309 pred = get_Proj_pred(pred_proj);
1313 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1315 if (get_ia32_op_type(pred) != ia32_Normal)
1318 /* the store only stores the lower bits, so we only need the conv
1319 * it it shrinks the mode */
1320 conv_mode = get_ia32_ls_mode(pred);
1321 store_mode = get_ia32_ls_mode(node);
1322 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1325 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1326 if (get_irn_n_edges(pred_proj) == 0) {
1327 kill_node(pred_proj);
1328 if (pred != pred_proj)
1333 static void optimize_load_conv(ir_node *node)
1335 ir_node *pred, *predpred;
1339 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1342 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1343 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1347 predpred = get_Proj_pred(pred);
1348 if (!is_ia32_Load(predpred))
1351 /* the load is sign extending the upper bits, so we only need the conv
1352 * if it shrinks the mode */
1353 load_mode = get_ia32_ls_mode(predpred);
1354 conv_mode = get_ia32_ls_mode(node);
1355 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1358 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1359 /* change the load if it has only 1 user */
1360 if (get_irn_n_edges(pred) == 1) {
1362 if (get_mode_sign(conv_mode)) {
1363 newmode = find_signed_mode(load_mode);
1365 newmode = find_unsigned_mode(load_mode);
1367 assert(newmode != NULL);
1368 set_ia32_ls_mode(predpred, newmode);
1370 /* otherwise we have to keep the conv */
1376 exchange(node, pred);
1379 static void optimize_conv_conv(ir_node *node)
1381 ir_node *pred_proj, *pred, *result_conv;
1382 ir_mode *pred_mode, *conv_mode;
1386 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1389 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1390 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1391 if (is_Proj(pred_proj))
1392 pred = get_Proj_pred(pred_proj);
1396 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1399 /* we know that after a conv, the upper bits are sign extended
1400 * so we only need the 2nd conv if it shrinks the mode */
1401 conv_mode = get_ia32_ls_mode(node);
1402 conv_mode_bits = get_mode_size_bits(conv_mode);
1403 pred_mode = get_ia32_ls_mode(pred);
1404 pred_mode_bits = get_mode_size_bits(pred_mode);
1406 if (conv_mode_bits == pred_mode_bits
1407 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1408 result_conv = pred_proj;
1409 } else if (conv_mode_bits <= pred_mode_bits) {
1410 /* if 2nd conv is smaller then first conv, then we can always take the
1412 if (get_irn_n_edges(pred_proj) == 1) {
1413 result_conv = pred_proj;
1414 set_ia32_ls_mode(pred, conv_mode);
1416 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1417 if (get_mode_size_bits(conv_mode) == 8) {
1418 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1419 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1422 /* we don't want to end up with 2 loads, so we better do nothing */
1423 if (get_irn_mode(pred) == mode_T) {
1427 result_conv = exact_copy(pred);
1428 set_ia32_ls_mode(result_conv, conv_mode);
1430 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1431 if (get_mode_size_bits(conv_mode) == 8) {
1432 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1433 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1437 /* if both convs have the same sign, then we can take the smaller one */
1438 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1439 result_conv = pred_proj;
1441 /* no optimisation possible if smaller conv is sign-extend */
1442 if (mode_is_signed(pred_mode)) {
1445 /* we can take the smaller conv if it is unsigned */
1446 result_conv = pred_proj;
1450 /* Some user (like Phis) won't be happy if we change the mode. */
1451 set_irn_mode(result_conv, get_irn_mode(node));
1454 exchange(node, result_conv);
1456 if (get_irn_n_edges(pred_proj) == 0) {
1457 kill_node(pred_proj);
1458 if (pred != pred_proj)
1461 optimize_conv_conv(result_conv);
1464 static void optimize_node(ir_node *node, void *env)
1468 optimize_load_conv(node);
1469 optimize_conv_store(node);
1470 optimize_conv_conv(node);
1474 * Performs conv and address mode optimization.
1476 void ia32_optimize_graph(ia32_code_gen_t *cg)
1478 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1481 dump_ir_graph(cg->irg, "opt");
1484 void ia32_init_optimize(void)
1486 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");