2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
45 #include "../benode.h"
46 #include "../besched.h"
47 #include "../bepeephole.h"
49 #include "ia32_new_nodes.h"
50 #include "ia32_optimize.h"
51 #include "bearch_ia32_t.h"
52 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_common_transform.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static void copy_mark(const ir_node *old, ir_node *newn)
63 if (is_ia32_is_reload(old))
64 set_ia32_is_reload(newn);
65 if (is_ia32_is_spill(old))
66 set_ia32_is_spill(newn);
67 if (is_ia32_is_remat(old))
68 set_ia32_is_remat(newn);
71 typedef enum produces_flag_t {
78 * Return which usable flag the given node produces
80 * @param node the node to check
81 * @param pn the projection number of the used result
83 static produces_flag_t produces_test_flag(ir_node *node, int pn)
86 const ia32_immediate_attr_t *imm_attr;
88 if (!is_ia32_irn(node))
89 return produces_no_flag;
91 switch (get_ia32_irn_opcode(node)) {
106 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
107 count = get_irn_n(node, n_ia32_ShlD_count);
108 goto check_shift_amount;
113 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
114 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
115 count = get_irn_n(node, n_ia32_Shl_count);
117 /* when shift count is zero the flags are not affected, so we can only
118 * do this for constants != 0 */
119 if (!is_ia32_Immediate(count))
120 return produces_no_flag;
122 imm_attr = get_ia32_immediate_attr_const(count);
123 if (imm_attr->symconst != NULL)
124 return produces_no_flag;
125 if ((imm_attr->offset & 0x1f) == 0)
126 return produces_no_flag;
130 return pn == pn_ia32_Mul_res_high ?
131 produces_flag_carry : produces_no_flag;
134 return produces_no_flag;
137 return pn == pn_ia32_res ?
138 produces_flag_zero : produces_no_flag;
142 * Replace Cmp(x, 0) by a Test(x, x)
144 static void peephole_ia32_Cmp(ir_node *const node)
148 ia32_immediate_attr_t const *imm;
154 ia32_attr_t const *attr;
157 arch_register_t const *reg;
158 ir_edge_t const *edge;
159 ir_edge_t const *tmp;
161 if (get_ia32_op_type(node) != ia32_Normal)
164 right = get_irn_n(node, n_ia32_Cmp_right);
165 if (!is_ia32_Immediate(right))
168 imm = get_ia32_immediate_attr_const(right);
169 if (imm->symconst != NULL || imm->offset != 0)
172 dbgi = get_irn_dbg_info(node);
173 irg = get_irn_irg(node);
174 block = get_nodes_block(node);
175 noreg = ia32_new_NoReg_gp(irg);
176 nomem = get_irg_no_mem(current_ir_graph);
177 op = get_irn_n(node, n_ia32_Cmp_left);
178 attr = get_ia32_attr(node);
179 ins_permuted = attr->data.ins_permuted;
181 if (is_ia32_Cmp(node)) {
182 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
183 op, op, ins_permuted);
185 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
186 op, op, ins_permuted);
188 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
190 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
191 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
193 foreach_out_edge_safe(node, edge, tmp) {
194 ir_node *const user = get_edge_src_irn(edge);
197 exchange(user, test);
200 sched_add_before(node, test);
201 copy_mark(node, test);
202 be_peephole_exchange(node, test);
206 * Peephole optimization for Test instructions.
207 * - Remove the Test, if an appropriate flag was produced which is still live
208 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
210 static void peephole_ia32_Test(ir_node *node)
212 ir_node *left = get_irn_n(node, n_ia32_Test_left);
213 ir_node *right = get_irn_n(node, n_ia32_Test_right);
215 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
216 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
218 if (left == right) { /* we need a test for 0 */
219 ir_node *block = get_nodes_block(node);
220 int pn = pn_ia32_res;
225 const ir_edge_t *edge;
227 if (get_nodes_block(left) != block)
231 pn = get_Proj_proj(op);
232 op = get_Proj_pred(op);
235 /* walk schedule up and abort when we find left or some other node
236 * destroys the flags */
239 schedpoint = sched_prev(schedpoint);
240 if (schedpoint == op)
242 if (arch_irn_is(schedpoint, modify_flags))
244 if (schedpoint == block)
245 panic("couldn't find left");
248 /* make sure only Lg/Eq tests are used */
249 foreach_out_edge(node, edge) {
250 ir_node *user = get_edge_src_irn(edge);
251 ia32_condition_code_t cc = get_ia32_condcode(user);
253 if (cc != ia32_cc_equal && cc != ia32_cc_not_equal) {
258 switch (produces_test_flag(op, pn)) {
259 case produces_flag_zero:
262 case produces_flag_carry:
263 foreach_out_edge(node, edge) {
264 ir_node *user = get_edge_src_irn(edge);
265 ia32_condition_code_t cc = get_ia32_condcode(user);
268 case ia32_cc_equal: cc = ia32_cc_above_equal; break; /* CF = 0 */
269 case ia32_cc_not_equal: cc = ia32_cc_below; break; /* CF = 1 */
270 default: panic("unexpected pn");
272 set_ia32_condcode(user, cc);
280 if (get_irn_mode(op) != mode_T) {
281 set_irn_mode(op, mode_T);
283 /* If there are other users, reroute them to result proj */
284 if (get_irn_n_edges(op) != 2) {
285 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
287 edges_reroute(op, res);
288 /* Reattach the result proj to left */
289 set_Proj_pred(res, op);
292 if (get_irn_n_edges(left) == 2)
296 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
297 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
298 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
300 assert(get_irn_mode(node) != mode_T);
302 be_peephole_exchange(node, flags_proj);
303 } else if (is_ia32_Immediate(right)) {
304 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
307 /* A test with a symconst is rather strange, but better safe than sorry */
308 if (imm->symconst != NULL)
311 offset = imm->offset;
312 if (get_ia32_op_type(node) == ia32_AddrModeS) {
313 ia32_attr_t *const attr = get_ia32_attr(node);
315 if ((offset & 0xFFFFFF00) == 0) {
316 /* attr->am_offs += 0; */
317 } else if ((offset & 0xFFFF00FF) == 0) {
318 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
319 set_irn_n(node, n_ia32_Test_right, imm);
321 } else if ((offset & 0xFF00FFFF) == 0) {
322 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
323 set_irn_n(node, n_ia32_Test_right, imm);
325 } else if ((offset & 0x00FFFFFF) == 0) {
326 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
327 set_irn_n(node, n_ia32_Test_right, imm);
332 } else if (offset < 256) {
333 arch_register_t const* const reg = arch_get_irn_register(left);
335 if (reg != &ia32_registers[REG_EAX] &&
336 reg != &ia32_registers[REG_EBX] &&
337 reg != &ia32_registers[REG_ECX] &&
338 reg != &ia32_registers[REG_EDX]) {
345 /* Technically we should build a Test8Bit because of the register
346 * constraints, but nobody changes registers at this point anymore. */
347 set_ia32_ls_mode(node, mode_Bu);
352 * AMD Athlon works faster when RET is not destination of
353 * conditional jump or directly preceded by other jump instruction.
354 * Can be avoided by placing a Rep prefix before the return.
356 static void peephole_ia32_Return(ir_node *node)
358 ir_node *block, *irn;
360 if (!ia32_cg_config.use_pad_return)
363 block = get_nodes_block(node);
365 /* check if this return is the first on the block */
366 sched_foreach_reverse_from(node, irn) {
367 switch (get_irn_opcode(irn)) {
369 /* the return node itself, ignore */
373 /* ignore no code generated */
376 /* arg, IncSP 0 nodes might occur, ignore these */
377 if (be_get_IncSP_offset(irn) == 0)
387 /* ensure, that the 3 byte return is generated */
388 be_Return_set_emit_pop(node, 1);
391 /* only optimize up to 48 stores behind IncSPs */
392 #define MAXPUSH_OPTIMIZE 48
395 * Tries to create Push's from IncSP, Store combinations.
396 * The Stores are replaced by Push's, the IncSP is modified
397 * (possibly into IncSP 0, but not removed).
399 static void peephole_IncSP_Store_to_push(ir_node *irn)
405 ir_node *stores[MAXPUSH_OPTIMIZE];
410 ir_node *first_push = NULL;
411 ir_edge_t const *edge;
412 ir_edge_t const *next;
414 memset(stores, 0, sizeof(stores));
416 assert(be_is_IncSP(irn));
418 inc_ofs = be_get_IncSP_offset(irn);
423 * We first walk the schedule after the IncSP node as long as we find
424 * suitable Stores that could be transformed to a Push.
425 * We save them into the stores array which is sorted by the frame offset/4
426 * attached to the node
429 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
434 /* it has to be a Store */
435 if (!is_ia32_Store(node))
438 /* it has to use our sp value */
439 if (get_irn_n(node, n_ia32_base) != irn)
441 /* Store has to be attached to NoMem */
442 mem = get_irn_n(node, n_ia32_mem);
446 /* unfortunately we can't support the full AMs possible for push at the
447 * moment. TODO: fix this */
448 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
451 offset = get_ia32_am_offs_int(node);
452 /* we should NEVER access uninitialized stack BELOW the current SP */
455 /* storing at half-slots is bad */
456 if ((offset & 3) != 0)
459 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
461 storeslot = offset >> 2;
463 /* storing into the same slot twice is bad (and shouldn't happen...) */
464 if (stores[storeslot] != NULL)
467 stores[storeslot] = node;
468 if (storeslot > maxslot)
474 for (i = -1; i < maxslot; ++i) {
475 if (stores[i + 1] == NULL)
479 /* walk through the Stores and create Pushs for them */
480 block = get_nodes_block(irn);
481 spmode = get_irn_mode(irn);
482 irg = get_irn_irg(irn);
483 for (; i >= 0; --i) {
484 const arch_register_t *spreg;
486 ir_node *val, *mem, *mem_proj;
487 ir_node *store = stores[i];
488 ir_node *noreg = ia32_new_NoReg_gp(irg);
490 val = get_irn_n(store, n_ia32_unary_op);
491 mem = get_irn_n(store, n_ia32_mem);
492 spreg = arch_get_irn_register(curr_sp);
494 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
495 copy_mark(store, push);
497 if (first_push == NULL)
500 sched_add_after(skip_Proj(curr_sp), push);
502 /* create stackpointer Proj */
503 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
504 arch_set_irn_register(curr_sp, spreg);
506 /* create memory Proj */
507 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
509 /* use the memproj now */
510 be_peephole_exchange(store, mem_proj);
515 foreach_out_edge_safe(irn, edge, next) {
516 ir_node *const src = get_edge_src_irn(edge);
517 int const pos = get_edge_src_pos(edge);
519 if (src == first_push)
522 set_irn_n(src, pos, curr_sp);
525 be_set_IncSP_offset(irn, inc_ofs);
530 * Creates a Push instruction before the given schedule point.
532 * @param dbgi debug info
533 * @param block the block
534 * @param stack the previous stack value
535 * @param schedpoint the new node is added before this node
536 * @param reg the register to pop
538 * @return the new stack value
540 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
541 ir_node *stack, ir_node *schedpoint)
543 const arch_register_t *esp = &ia32_registers[REG_ESP];
545 ir_node *val = ia32_new_NoReg_gp(cg);
546 ir_node *noreg = ia32_new_NoReg_gp(cg);
547 ir_graph *irg = get_irn_irg(block);
548 ir_node *nomem = new_r_NoMem(irg);
549 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
550 sched_add_before(schedpoint, push);
552 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
553 arch_set_irn_register(stack, esp);
558 static void peephole_store_incsp(ir_node *store)
569 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
570 if (!be_is_IncSP(am_base)
571 || get_nodes_block(am_base) != get_nodes_block(store))
573 mem = get_irn_n(store, n_ia32_Store_mem);
574 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
578 int incsp_offset = be_get_IncSP_offset(am_base);
579 if (incsp_offset <= 0)
582 /* we have to be at offset 0 */
583 int my_offset = get_ia32_am_offs_int(store);
584 if (my_offset != 0) {
585 /* TODO here: find out whether there is a store with offset 0 before
586 * us and whether we can move it down to our place */
589 ir_mode *ls_mode = get_ia32_ls_mode(store);
590 int my_store_size = get_mode_size_bytes(ls_mode);
592 if (my_offset + my_store_size > incsp_offset)
595 /* correctness checking:
596 - noone else must write to that stackslot
597 (because after translation incsp won't allocate it anymore)
599 sched_foreach_reverse_from(store, node) {
605 /* make sure noone else can use the space on the stack */
606 arity = get_irn_arity(node);
607 for (i = 0; i < arity; ++i) {
608 ir_node *pred = get_irn_n(node, i);
612 if (i == n_ia32_base &&
613 (get_ia32_op_type(node) == ia32_AddrModeS
614 || get_ia32_op_type(node) == ia32_AddrModeD)) {
615 int node_offset = get_ia32_am_offs_int(node);
616 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
617 int node_size = get_mode_size_bytes(node_ls_mode);
618 /* overlapping with our position? abort */
619 if (node_offset < my_offset + my_store_size
620 && node_offset + node_size >= my_offset)
622 /* otherwise it's fine */
626 /* strange use of esp: abort */
631 /* all ok, change to push */
632 dbgi = get_irn_dbg_info(store);
633 block = get_nodes_block(store);
634 noreg = ia32_new_NoReg_gp(cg);
635 val = get_irn_n(store, n_ia32_Store_val);
637 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
639 create_push(dbgi, current_ir_graph, block, am_base, store);
644 * Return true if a mode can be stored in the GP register set
646 static inline int mode_needs_gp_reg(ir_mode *mode)
648 if (mode == ia32_mode_fpcw)
650 if (get_mode_size_bits(mode) > 32)
652 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
656 * Tries to create Pops from Load, IncSP combinations.
657 * The Loads are replaced by Pops, the IncSP is modified
658 * (possibly into IncSP 0, but not removed).
660 static void peephole_Load_IncSP_to_pop(ir_node *irn)
662 const arch_register_t *esp = &ia32_registers[REG_ESP];
663 int i, maxslot, inc_ofs, ofs;
664 ir_node *node, *pred_sp, *block;
665 ir_node *loads[MAXPUSH_OPTIMIZE];
667 unsigned regmask = 0;
668 unsigned copymask = ~0;
670 memset(loads, 0, sizeof(loads));
671 assert(be_is_IncSP(irn));
673 inc_ofs = -be_get_IncSP_offset(irn);
678 * We first walk the schedule before the IncSP node as long as we find
679 * suitable Loads that could be transformed to a Pop.
680 * We save them into the stores array which is sorted by the frame offset/4
681 * attached to the node
684 pred_sp = be_get_IncSP_pred(irn);
685 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
688 const arch_register_t *sreg, *dreg;
690 /* it has to be a Load */
691 if (!is_ia32_Load(node)) {
692 if (be_is_Copy(node)) {
693 if (!mode_needs_gp_reg(get_irn_mode(node))) {
694 /* not a GP copy, ignore */
697 dreg = arch_get_irn_register(node);
698 sreg = arch_get_irn_register(be_get_Copy_op(node));
699 if (regmask & copymask & (1 << sreg->index)) {
702 if (regmask & copymask & (1 << dreg->index)) {
705 /* we CAN skip Copies if neither the destination nor the source
706 * is not in our regmask, ie none of our future Pop will overwrite it */
707 regmask |= (1 << dreg->index) | (1 << sreg->index);
708 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
714 /* we can handle only GP loads */
715 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
718 /* it has to use our predecessor sp value */
719 if (get_irn_n(node, n_ia32_base) != pred_sp) {
720 /* it would be ok if this load does not use a Pop result,
721 * but we do not check this */
725 /* should have NO index */
726 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
729 offset = get_ia32_am_offs_int(node);
730 /* we should NEVER access uninitialized stack BELOW the current SP */
733 /* storing at half-slots is bad */
734 if ((offset & 3) != 0)
737 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
739 /* ignore those outside the possible windows */
740 if (offset > inc_ofs - 4)
742 loadslot = offset >> 2;
744 /* loading from the same slot twice is bad (and shouldn't happen...) */
745 if (loads[loadslot] != NULL)
748 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
749 if (regmask & (1 << dreg->index)) {
750 /* this register is already used */
753 regmask |= 1 << dreg->index;
755 loads[loadslot] = node;
756 if (loadslot > maxslot)
763 /* find the first slot */
764 for (i = maxslot; i >= 0; --i) {
765 ir_node *load = loads[i];
771 ofs = inc_ofs - (maxslot + 1) * 4;
774 /* create a new IncSP if needed */
775 block = get_nodes_block(irn);
776 irg = get_irn_irg(irn);
778 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
779 sched_add_before(irn, pred_sp);
782 /* walk through the Loads and create Pops for them */
783 for (++i; i <= maxslot; ++i) {
784 ir_node *load = loads[i];
786 const ir_edge_t *edge, *tmp;
787 const arch_register_t *reg;
789 mem = get_irn_n(load, n_ia32_mem);
790 reg = arch_irn_get_register(load, pn_ia32_Load_res);
792 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
793 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
795 copy_mark(load, pop);
797 /* create stackpointer Proj */
798 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
799 arch_set_irn_register(pred_sp, esp);
801 sched_add_before(irn, pop);
804 foreach_out_edge_safe(load, edge, tmp) {
805 ir_node *proj = get_edge_src_irn(edge);
807 set_Proj_pred(proj, pop);
810 /* we can remove the Load now */
815 be_set_IncSP_offset(irn, -ofs);
816 be_set_IncSP_pred(irn, pred_sp);
821 * Find a free GP register if possible, else return NULL.
823 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
825 be_irg_t *birg = be_birg_from_irg(irg);
828 for (i = 0; i < N_ia32_gp_REGS; ++i) {
829 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
830 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
833 if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
841 * Creates a Pop instruction before the given schedule point.
843 * @param dbgi debug info
844 * @param block the block
845 * @param stack the previous stack value
846 * @param schedpoint the new node is added before this node
847 * @param reg the register to pop
849 * @return the new stack value
851 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
852 ir_node *stack, ir_node *schedpoint,
853 const arch_register_t *reg)
855 const arch_register_t *esp = &ia32_registers[REG_ESP];
856 ir_graph *irg = get_irn_irg(block);
862 pop = new_bd_ia32_Pop(dbgi, block, new_r_NoMem(irg), stack);
864 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
865 arch_set_irn_register(stack, esp);
866 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
867 arch_set_irn_register(val, reg);
869 sched_add_before(schedpoint, pop);
872 keep = be_new_Keep(block, 1, in);
873 sched_add_before(schedpoint, keep);
879 * Optimize an IncSp by replacing it with Push/Pop.
881 static void peephole_be_IncSP(ir_node *node)
883 const arch_register_t *esp = &ia32_registers[REG_ESP];
884 const arch_register_t *reg;
890 /* first optimize incsp->incsp combinations */
891 node = be_peephole_IncSP_IncSP(node);
893 /* transform IncSP->Store combinations to Push where possible */
894 peephole_IncSP_Store_to_push(node);
896 /* transform Load->IncSP combinations to Pop where possible */
897 peephole_Load_IncSP_to_pop(node);
899 if (arch_get_irn_register(node) != esp)
902 /* replace IncSP -4 by Pop freereg when possible */
903 offset = be_get_IncSP_offset(node);
904 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
905 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
906 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
907 (offset != +8 || ia32_cg_config.use_sub_esp_8))
911 /* we need a free register for pop */
912 reg = get_free_gp_reg(get_irn_irg(node));
916 dbgi = get_irn_dbg_info(node);
917 block = get_nodes_block(node);
918 stack = be_get_IncSP_pred(node);
920 stack = create_pop(dbgi, block, stack, node, reg);
923 stack = create_pop(dbgi, block, stack, node, reg);
926 dbgi = get_irn_dbg_info(node);
927 block = get_nodes_block(node);
928 stack = be_get_IncSP_pred(node);
929 stack = new_bd_ia32_PushEax(dbgi, block, stack);
930 arch_set_irn_register(stack, esp);
931 sched_add_before(node, stack);
934 stack = new_bd_ia32_PushEax(dbgi, block, stack);
935 arch_set_irn_register(stack, esp);
936 sched_add_before(node, stack);
940 be_peephole_exchange(node, stack);
944 * Peephole optimisation for ia32_Const's
946 static void peephole_ia32_Const(ir_node *node)
948 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
949 const arch_register_t *reg;
954 /* try to transform a mov 0, reg to xor reg reg */
955 if (attr->offset != 0 || attr->symconst != NULL)
957 if (ia32_cg_config.use_mov_0)
959 /* xor destroys the flags, so no-one must be using them */
960 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
963 reg = arch_get_irn_register(node);
964 assert(be_peephole_get_reg_value(reg) == NULL);
966 /* create xor(produceval, produceval) */
967 block = get_nodes_block(node);
968 dbgi = get_irn_dbg_info(node);
969 xorn = new_bd_ia32_Xor0(dbgi, block);
970 arch_set_irn_register(xorn, reg);
972 sched_add_before(node, xorn);
974 copy_mark(node, xorn);
975 be_peephole_exchange(node, xorn);
978 static inline int is_noreg(const ir_node *node)
980 return is_ia32_NoReg_GP(node);
983 ir_node *ia32_immediate_from_long(long val)
985 ir_graph *irg = current_ir_graph;
986 ir_node *start_block = get_irg_start_block(irg);
988 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
989 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
994 static ir_node *create_immediate_from_am(const ir_node *node)
996 ir_node *block = get_nodes_block(node);
997 int offset = get_ia32_am_offs_int(node);
998 int sc_sign = is_ia32_am_sc_sign(node);
999 const ia32_attr_t *attr = get_ia32_attr_const(node);
1000 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1001 ir_entity *entity = get_ia32_am_sc(node);
1004 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1006 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1010 static int is_am_one(const ir_node *node)
1012 int offset = get_ia32_am_offs_int(node);
1013 ir_entity *entity = get_ia32_am_sc(node);
1015 return offset == 1 && entity == NULL;
1018 static int is_am_minus_one(const ir_node *node)
1020 int offset = get_ia32_am_offs_int(node);
1021 ir_entity *entity = get_ia32_am_sc(node);
1023 return offset == -1 && entity == NULL;
1027 * Transforms a LEA into an Add or SHL if possible.
1029 static void peephole_ia32_Lea(ir_node *node)
1034 const arch_register_t *base_reg;
1035 const arch_register_t *index_reg;
1036 const arch_register_t *out_reg;
1047 assert(is_ia32_Lea(node));
1049 /* we can only do this if it is allowed to clobber the flags */
1050 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
1053 base = get_irn_n(node, n_ia32_Lea_base);
1054 index = get_irn_n(node, n_ia32_Lea_index);
1056 if (is_noreg(base)) {
1060 base_reg = arch_get_irn_register(base);
1062 if (is_noreg(index)) {
1066 index_reg = arch_get_irn_register(index);
1069 if (base == NULL && index == NULL) {
1070 /* we shouldn't construct these in the first place... */
1071 #ifdef DEBUG_libfirm
1072 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1077 out_reg = arch_get_irn_register(node);
1078 scale = get_ia32_am_scale(node);
1079 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1080 /* check if we have immediates values (frame entities should already be
1081 * expressed in the offsets) */
1082 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1088 /* we can transform leas where the out register is the same as either the
1089 * base or index register back to an Add or Shl */
1090 if (out_reg == base_reg) {
1091 if (index == NULL) {
1092 #ifdef DEBUG_libfirm
1093 if (!has_immediates) {
1094 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1099 goto make_add_immediate;
1101 if (scale == 0 && !has_immediates) {
1106 /* can't create an add */
1108 } else if (out_reg == index_reg) {
1110 if (has_immediates && scale == 0) {
1112 goto make_add_immediate;
1113 } else if (!has_immediates && scale > 0) {
1115 op2 = ia32_immediate_from_long(scale);
1117 } else if (!has_immediates) {
1118 #ifdef DEBUG_libfirm
1119 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1123 } else if (scale == 0 && !has_immediates) {
1128 /* can't create an add */
1131 /* can't create an add */
1136 if (ia32_cg_config.use_incdec) {
1137 if (is_am_one(node)) {
1138 dbgi = get_irn_dbg_info(node);
1139 block = get_nodes_block(node);
1140 res = new_bd_ia32_Inc(dbgi, block, op1);
1141 arch_set_irn_register(res, out_reg);
1144 if (is_am_minus_one(node)) {
1145 dbgi = get_irn_dbg_info(node);
1146 block = get_nodes_block(node);
1147 res = new_bd_ia32_Dec(dbgi, block, op1);
1148 arch_set_irn_register(res, out_reg);
1152 op2 = create_immediate_from_am(node);
1155 dbgi = get_irn_dbg_info(node);
1156 block = get_nodes_block(node);
1157 irg = get_irn_irg(node);
1158 noreg = ia32_new_NoReg_gp(irg);
1159 nomem = new_r_NoMem(irg);
1160 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1161 arch_set_irn_register(res, out_reg);
1162 set_ia32_commutative(res);
1166 dbgi = get_irn_dbg_info(node);
1167 block = get_nodes_block(node);
1168 irg = get_irn_irg(node);
1169 noreg = ia32_new_NoReg_gp(irg);
1170 nomem = new_r_NoMem(irg);
1171 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1172 arch_set_irn_register(res, out_reg);
1176 SET_IA32_ORIG_NODE(res, node);
1178 /* add new ADD/SHL to schedule */
1179 DBG_OPT_LEA2ADD(node, res);
1181 /* exchange the Add and the LEA */
1182 sched_add_before(node, res);
1183 copy_mark(node, res);
1184 be_peephole_exchange(node, res);
1188 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1190 static void peephole_ia32_Imul_split(ir_node *imul)
1192 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1193 const arch_register_t *reg;
1196 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1197 /* no memory, imm form ignore */
1200 /* we need a free register */
1201 reg = get_free_gp_reg(get_irn_irg(imul));
1205 /* fine, we can rebuild it */
1206 res = ia32_turn_back_am(imul);
1207 arch_set_irn_register(res, reg);
1211 * Replace xorps r,r and xorpd r,r by pxor r,r
1213 static void peephole_ia32_xZero(ir_node *xorn)
1215 set_irn_op(xorn, op_ia32_xPzero);
1219 * Replace 16bit sign extension from ax to eax by shorter cwtl
1221 static void peephole_ia32_Conv_I2I(ir_node *node)
1223 const arch_register_t *eax = &ia32_registers[REG_EAX];
1224 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1225 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1230 if (get_mode_size_bits(smaller_mode) != 16 ||
1231 !mode_is_signed(smaller_mode) ||
1232 eax != arch_get_irn_register(val) ||
1233 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1236 dbgi = get_irn_dbg_info(node);
1237 block = get_nodes_block(node);
1238 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1239 arch_set_irn_register(cwtl, eax);
1240 sched_add_before(node, cwtl);
1241 be_peephole_exchange(node, cwtl);
1245 * Register a peephole optimisation function.
1247 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1249 assert(op->ops.generic == NULL);
1250 op->ops.generic = (op_func)func;
1253 /* Perform peephole-optimizations. */
1254 void ia32_peephole_optimization(ir_graph *irg)
1256 /* register peephole optimisations */
1257 clear_irp_opcodes_generic_func();
1258 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1259 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1260 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1261 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1262 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1263 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1264 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1265 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1266 if (! ia32_cg_config.use_imul_mem_imm32)
1267 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1268 if (ia32_cg_config.use_pxor)
1269 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1270 if (ia32_cg_config.use_short_sex_eax)
1271 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1273 be_peephole_opt(irg);
1277 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1278 * all its Projs are removed as well.
1279 * @param irn The irn to be removed from schedule
1281 static inline void try_kill(ir_node *node)
1283 if (get_irn_mode(node) == mode_T) {
1284 const ir_edge_t *edge, *next;
1285 foreach_out_edge_safe(node, edge, next) {
1286 ir_node *proj = get_edge_src_irn(edge);
1291 if (get_irn_n_edges(node) != 0)
1294 if (sched_is_scheduled(node)) {
1301 static void optimize_conv_store(ir_node *node)
1306 ir_mode *store_mode;
1308 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1311 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1312 pred_proj = get_irn_n(node, n_ia32_Store_val);
1313 if (is_Proj(pred_proj)) {
1314 pred = get_Proj_pred(pred_proj);
1318 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1320 if (get_ia32_op_type(pred) != ia32_Normal)
1323 /* the store only stores the lower bits, so we only need the conv
1324 * it it shrinks the mode */
1325 conv_mode = get_ia32_ls_mode(pred);
1326 store_mode = get_ia32_ls_mode(node);
1327 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1330 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1331 if (get_irn_n_edges(pred_proj) == 0) {
1332 kill_node(pred_proj);
1333 if (pred != pred_proj)
1338 static void optimize_load_conv(ir_node *node)
1340 ir_node *pred, *predpred;
1344 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1347 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1348 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1352 predpred = get_Proj_pred(pred);
1353 if (!is_ia32_Load(predpred))
1356 /* the load is sign extending the upper bits, so we only need the conv
1357 * if it shrinks the mode */
1358 load_mode = get_ia32_ls_mode(predpred);
1359 conv_mode = get_ia32_ls_mode(node);
1360 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1363 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1364 /* change the load if it has only 1 user */
1365 if (get_irn_n_edges(pred) == 1) {
1367 if (get_mode_sign(conv_mode)) {
1368 newmode = find_signed_mode(load_mode);
1370 newmode = find_unsigned_mode(load_mode);
1372 assert(newmode != NULL);
1373 set_ia32_ls_mode(predpred, newmode);
1375 /* otherwise we have to keep the conv */
1381 exchange(node, pred);
1384 static void optimize_conv_conv(ir_node *node)
1386 ir_node *pred_proj, *pred, *result_conv;
1387 ir_mode *pred_mode, *conv_mode;
1391 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1394 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1395 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1396 if (is_Proj(pred_proj))
1397 pred = get_Proj_pred(pred_proj);
1401 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1404 /* we know that after a conv, the upper bits are sign extended
1405 * so we only need the 2nd conv if it shrinks the mode */
1406 conv_mode = get_ia32_ls_mode(node);
1407 conv_mode_bits = get_mode_size_bits(conv_mode);
1408 pred_mode = get_ia32_ls_mode(pred);
1409 pred_mode_bits = get_mode_size_bits(pred_mode);
1411 if (conv_mode_bits == pred_mode_bits
1412 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1413 result_conv = pred_proj;
1414 } else if (conv_mode_bits <= pred_mode_bits) {
1415 /* if 2nd conv is smaller then first conv, then we can always take the
1417 if (get_irn_n_edges(pred_proj) == 1) {
1418 result_conv = pred_proj;
1419 set_ia32_ls_mode(pred, conv_mode);
1421 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1422 if (get_mode_size_bits(conv_mode) == 8) {
1423 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1424 arch_set_in_register_reqs(pred,
1425 arch_get_in_register_reqs(node));
1428 /* we don't want to end up with 2 loads, so we better do nothing */
1429 if (get_irn_mode(pred) == mode_T) {
1433 result_conv = exact_copy(pred);
1434 set_ia32_ls_mode(result_conv, conv_mode);
1436 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1437 if (get_mode_size_bits(conv_mode) == 8) {
1438 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1439 arch_set_in_register_reqs(result_conv,
1440 arch_get_in_register_reqs(node));
1444 /* if both convs have the same sign, then we can take the smaller one */
1445 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1446 result_conv = pred_proj;
1448 /* no optimisation possible if smaller conv is sign-extend */
1449 if (mode_is_signed(pred_mode)) {
1452 /* we can take the smaller conv if it is unsigned */
1453 result_conv = pred_proj;
1457 /* Some user (like Phis) won't be happy if we change the mode. */
1458 set_irn_mode(result_conv, get_irn_mode(node));
1461 exchange(node, result_conv);
1463 if (get_irn_n_edges(pred_proj) == 0) {
1464 kill_node(pred_proj);
1465 if (pred != pred_proj)
1468 optimize_conv_conv(result_conv);
1471 static void optimize_node(ir_node *node, void *env)
1475 optimize_load_conv(node);
1476 optimize_conv_store(node);
1477 optimize_conv_conv(node);
1481 * Performs conv and address mode optimization.
1483 void ia32_optimize_graph(ir_graph *irg)
1485 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1488 void ia32_init_optimize(void)
1490 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");