2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
31 #include "firm_types.h"
40 #include "firmstat_t.h"
46 #include "bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_architecture.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 static void copy_mark(const ir_node *old, ir_node *newn)
61 if (is_ia32_is_reload(old))
62 set_ia32_is_reload(newn);
63 if (is_ia32_is_spill(old))
64 set_ia32_is_spill(newn);
65 if (is_ia32_is_remat(old))
66 set_ia32_is_remat(newn);
69 typedef enum produces_flag_t {
72 produces_zero_in_carry
76 * Return which usable flag the given node produces about the result.
77 * That is zero (ZF) and sign(SF).
78 * We do not check for carry (CF) or overflow (OF).
80 * @param node the node to check
81 * @param pn the projection number of the used result
83 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
86 const ia32_immediate_attr_t *imm_attr;
88 if (!is_ia32_irn(node))
89 return produces_no_flag;
91 switch (get_ia32_irn_opcode(node)) {
106 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
107 count = get_irn_n(node, n_ia32_ShlD_count);
108 goto check_shift_amount;
113 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
114 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
115 count = get_irn_n(node, n_ia32_Shl_count);
117 /* when shift count is zero the flags are not affected, so we can only
118 * do this for constants != 0 */
119 if (!is_ia32_Immediate(count))
120 return produces_no_flag;
122 imm_attr = get_ia32_immediate_attr_const(count);
123 if (imm_attr->symconst != NULL)
124 return produces_no_flag;
125 if ((imm_attr->offset & 0x1f) == 0)
126 return produces_no_flag;
130 return pn == pn_ia32_Mul_res_high ?
131 produces_zero_in_carry : produces_no_flag;
134 return produces_no_flag;
137 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
141 * Replace Cmp(x, 0) by a Test(x, x)
143 static void peephole_ia32_Cmp(ir_node *const node)
147 ia32_immediate_attr_t const *imm;
153 ia32_attr_t const *attr;
156 arch_register_t const *reg;
158 if (get_ia32_op_type(node) != ia32_Normal)
161 right = get_irn_n(node, n_ia32_Cmp_right);
162 if (!is_ia32_Immediate(right))
165 imm = get_ia32_immediate_attr_const(right);
166 if (imm->symconst != NULL || imm->offset != 0)
169 dbgi = get_irn_dbg_info(node);
170 block = get_nodes_block(node);
171 irg = get_Block_irg(block);
172 noreg = ia32_new_NoReg_gp(irg);
173 nomem = get_irg_no_mem(irg);
174 op = get_irn_n(node, n_ia32_Cmp_left);
175 attr = get_ia32_attr(node);
176 ins_permuted = attr->data.ins_permuted;
178 if (is_ia32_Cmp(node)) {
179 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
180 op, op, ins_permuted);
182 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
183 op, op, ins_permuted);
185 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
187 reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
188 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
190 foreach_out_edge_safe(node, edge) {
191 ir_node *const user = get_edge_src_irn(edge);
194 exchange(user, test);
197 sched_add_before(node, test);
198 copy_mark(node, test);
199 be_peephole_exchange(node, test);
203 * Peephole optimization for Test instructions.
204 * - Remove the Test, if an appropriate flag was produced which is still live
205 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
207 static void peephole_ia32_Test(ir_node *node)
209 ir_node *left = get_irn_n(node, n_ia32_Test_left);
210 ir_node *right = get_irn_n(node, n_ia32_Test_right);
212 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
213 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
215 if (left == right) { /* we need a test for 0 */
216 ir_node *block = get_nodes_block(node);
217 int pn = pn_ia32_res;
223 produces_flag_t produced;
225 if (get_nodes_block(left) != block)
229 pn = get_Proj_proj(op);
230 op = get_Proj_pred(op);
233 /* walk schedule up and abort when we find left or some other node
234 * destroys the flags */
237 schedpoint = sched_prev(schedpoint);
238 if (schedpoint == op)
240 if (arch_irn_is(schedpoint, modify_flags))
242 if (schedpoint == block)
243 panic("couldn't find left");
246 produced = check_produces_zero_sign(op, pn);
247 if (produced == produces_no_flag)
250 /* make sure users only look at the sign/zero flag */
251 foreach_out_edge(node, edge) {
252 ir_node *user = get_edge_src_irn(edge);
253 ia32_condition_code_t cc = get_ia32_condcode(user);
255 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
257 if (produced == produces_zero_sign
258 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
264 op_mode = get_ia32_ls_mode(op);
266 op_mode = get_irn_mode(op);
268 /* Make sure we operate on the same bit size */
269 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
272 if (produced == produces_zero_in_carry) {
273 /* patch users to look at the carry instead of the zero flag */
274 foreach_out_edge(node, edge) {
275 ir_node *user = get_edge_src_irn(edge);
276 ia32_condition_code_t cc = get_ia32_condcode(user);
279 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
280 case ia32_cc_not_equal: cc = ia32_cc_below; break;
281 default: panic("unexpected pn");
283 set_ia32_condcode(user, cc);
287 if (get_irn_mode(op) != mode_T) {
288 set_irn_mode(op, mode_T);
290 /* If there are other users, reroute them to result proj */
291 if (get_irn_n_edges(op) != 2) {
292 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
293 edges_reroute_except(op, res, res);
296 if (get_irn_n_edges(left) == 2)
300 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
301 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
302 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
304 assert(get_irn_mode(node) != mode_T);
306 be_peephole_exchange(node, flags_proj);
307 } else if (is_ia32_Immediate(right)) {
308 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
311 /* A test with a symconst is rather strange, but better safe than sorry */
312 if (imm->symconst != NULL)
315 offset = imm->offset;
316 if (get_ia32_op_type(node) == ia32_AddrModeS) {
317 ia32_attr_t *const attr = get_ia32_attr(node);
318 ir_graph *const irg = get_irn_irg(node);
320 if ((offset & 0xFFFFFF00) == 0) {
321 /* attr->am_offs += 0; */
322 } else if ((offset & 0xFFFF00FF) == 0) {
323 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 8);
324 set_irn_n(node, n_ia32_Test_right, imm_node);
326 } else if ((offset & 0xFF00FFFF) == 0) {
327 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 16);
328 set_irn_n(node, n_ia32_Test_right, imm_node);
330 } else if ((offset & 0x00FFFFFF) == 0) {
331 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 24);
332 set_irn_n(node, n_ia32_Test_right, imm_node);
337 } else if (offset < 256) {
338 arch_register_t const* const reg = arch_get_irn_register(left);
340 if (reg != &ia32_registers[REG_EAX] &&
341 reg != &ia32_registers[REG_EBX] &&
342 reg != &ia32_registers[REG_ECX] &&
343 reg != &ia32_registers[REG_EDX]) {
350 /* Technically we should build a Test8Bit because of the register
351 * constraints, but nobody changes registers at this point anymore. */
352 set_ia32_ls_mode(node, mode_Bu);
357 * AMD Athlon works faster when RET is not destination of
358 * conditional jump or directly preceded by other jump instruction.
359 * Can be avoided by placing a Rep prefix before the return.
361 static void peephole_ia32_Return(ir_node *node)
363 if (!ia32_cg_config.use_pad_return)
366 /* check if this return is the first on the block */
367 sched_foreach_reverse_from(node, irn) {
368 switch (get_irn_opcode(irn)) {
370 /* the return node itself, ignore */
374 /* ignore no code generated */
377 /* arg, IncSP 0 nodes might occur, ignore these */
378 if (be_get_IncSP_offset(irn) == 0)
388 /* ensure, that the 3 byte return is generated */
389 be_Return_set_emit_pop(node, 1);
392 /* only optimize up to 48 stores behind IncSPs */
393 #define MAXPUSH_OPTIMIZE 48
396 * Tries to create Push's from IncSP, Store combinations.
397 * The Stores are replaced by Push's, the IncSP is modified
398 * (possibly into IncSP 0, but not removed).
400 static void peephole_IncSP_Store_to_push(ir_node *irn)
406 ir_node *stores[MAXPUSH_OPTIMIZE];
411 ir_node *first_push = NULL;
413 memset(stores, 0, sizeof(stores));
415 assert(be_is_IncSP(irn));
417 inc_ofs = be_get_IncSP_offset(irn);
422 * We first walk the schedule after the IncSP node as long as we find
423 * suitable Stores that could be transformed to a Push.
424 * We save them into the stores array which is sorted by the frame offset/4
425 * attached to the node
428 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
433 /* it has to be a Store */
434 if (!is_ia32_Store(node))
437 /* it has to use our sp value */
438 if (get_irn_n(node, n_ia32_base) != irn)
440 /* Store has to be attached to NoMem */
441 mem = get_irn_n(node, n_ia32_mem);
445 /* unfortunately we can't support the full AMs possible for push at the
446 * moment. TODO: fix this */
447 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
450 offset = get_ia32_am_offs_int(node);
451 /* we should NEVER access uninitialized stack BELOW the current SP */
454 /* storing at half-slots is bad */
455 if ((offset & 3) != 0)
458 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
460 storeslot = offset >> 2;
462 /* storing into the same slot twice is bad (and shouldn't happen...) */
463 if (stores[storeslot] != NULL)
466 stores[storeslot] = node;
467 if (storeslot > maxslot)
473 for (i = -1; i < maxslot; ++i) {
474 if (stores[i + 1] == NULL)
478 /* walk through the Stores and create Pushs for them */
479 block = get_nodes_block(irn);
480 spmode = get_irn_mode(irn);
481 irg = get_irn_irg(irn);
482 for (; i >= 0; --i) {
483 const arch_register_t *spreg;
485 ir_node *val, *mem, *mem_proj;
486 ir_node *store = stores[i];
487 ir_node *noreg = ia32_new_NoReg_gp(irg);
489 val = get_irn_n(store, n_ia32_unary_op);
490 mem = get_irn_n(store, n_ia32_mem);
491 spreg = arch_get_irn_register(curr_sp);
493 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
495 copy_mark(store, push);
497 if (first_push == NULL)
500 sched_add_after(skip_Proj(curr_sp), push);
502 /* create stackpointer Proj */
503 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
504 arch_set_irn_register(curr_sp, spreg);
506 /* create memory Proj */
507 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
509 /* rewire Store Projs */
510 foreach_out_edge_safe(store, edge) {
511 ir_node *proj = get_edge_src_irn(edge);
514 switch (get_Proj_proj(proj)) {
515 case pn_ia32_Store_M:
516 exchange(proj, mem_proj);
519 panic("unexpected Proj on Store->IncSp");
523 /* use the memproj now */
524 be_peephole_exchange(store, push);
529 foreach_out_edge_safe(irn, edge) {
530 ir_node *const src = get_edge_src_irn(edge);
531 int const pos = get_edge_src_pos(edge);
533 if (src == first_push)
536 set_irn_n(src, pos, curr_sp);
539 be_set_IncSP_offset(irn, inc_ofs);
544 * Creates a Push instruction before the given schedule point.
546 * @param dbgi debug info
547 * @param block the block
548 * @param stack the previous stack value
549 * @param schedpoint the new node is added before this node
550 * @param reg the register to pop
552 * @return the new stack value
554 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
555 ir_node *stack, ir_node *schedpoint)
557 const arch_register_t *esp = &ia32_registers[REG_ESP];
559 ir_node *val = ia32_new_NoReg_gp(cg);
560 ir_node *noreg = ia32_new_NoReg_gp(cg);
561 ir_graph *irg = get_irn_irg(block);
562 ir_node *nomem = get_irg_no_mem(irg);
563 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
564 sched_add_before(schedpoint, push);
566 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
567 arch_set_irn_register(stack, esp);
572 static void peephole_store_incsp(ir_node *store)
582 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
583 if (!be_is_IncSP(am_base)
584 || get_nodes_block(am_base) != get_nodes_block(store))
586 mem = get_irn_n(store, n_ia32_Store_mem);
587 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
591 int incsp_offset = be_get_IncSP_offset(am_base);
592 if (incsp_offset <= 0)
595 /* we have to be at offset 0 */
596 int my_offset = get_ia32_am_offs_int(store);
597 if (my_offset != 0) {
598 /* TODO here: find out whether there is a store with offset 0 before
599 * us and whether we can move it down to our place */
602 ir_mode *ls_mode = get_ia32_ls_mode(store);
603 int my_store_size = get_mode_size_bytes(ls_mode);
605 if (my_offset + my_store_size > incsp_offset)
608 /* correctness checking:
609 - noone else must write to that stackslot
610 (because after translation incsp won't allocate it anymore)
612 sched_foreach_reverse_from(store, node) {
618 /* make sure noone else can use the space on the stack */
619 arity = get_irn_arity(node);
620 for (i = 0; i < arity; ++i) {
621 ir_node *pred = get_irn_n(node, i);
625 if (i == n_ia32_base &&
626 (get_ia32_op_type(node) == ia32_AddrModeS
627 || get_ia32_op_type(node) == ia32_AddrModeD)) {
628 int node_offset = get_ia32_am_offs_int(node);
629 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
630 int node_size = get_mode_size_bytes(node_ls_mode);
631 /* overlapping with our position? abort */
632 if (node_offset < my_offset + my_store_size
633 && node_offset + node_size >= my_offset)
635 /* otherwise it's fine */
639 /* strange use of esp: abort */
644 /* all ok, change to push */
645 dbgi = get_irn_dbg_info(store);
646 block = get_nodes_block(store);
647 noreg = ia32_new_NoReg_gp(cg);
648 val = get_irn_n(store, n_ia32_Store_val);
650 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
652 create_push(dbgi, block, am_base, store);
657 * Return true if a mode can be stored in the GP register set
659 static inline int mode_needs_gp_reg(ir_mode *mode)
661 if (mode == ia32_mode_fpcw)
663 if (get_mode_size_bits(mode) > 32)
665 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
669 * Tries to create Pops from Load, IncSP combinations.
670 * The Loads are replaced by Pops, the IncSP is modified
671 * (possibly into IncSP 0, but not removed).
673 static void peephole_Load_IncSP_to_pop(ir_node *irn)
675 const arch_register_t *esp = &ia32_registers[REG_ESP];
676 int i, maxslot, inc_ofs, ofs;
677 ir_node *node, *pred_sp, *block;
678 ir_node *loads[MAXPUSH_OPTIMIZE];
679 unsigned regmask = 0;
680 unsigned copymask = ~0;
682 memset(loads, 0, sizeof(loads));
683 assert(be_is_IncSP(irn));
685 inc_ofs = -be_get_IncSP_offset(irn);
690 * We first walk the schedule before the IncSP node as long as we find
691 * suitable Loads that could be transformed to a Pop.
692 * We save them into the stores array which is sorted by the frame offset/4
693 * attached to the node
696 pred_sp = be_get_IncSP_pred(irn);
697 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
700 const arch_register_t *sreg, *dreg;
702 /* it has to be a Load */
703 if (!is_ia32_Load(node)) {
704 if (be_is_Copy(node)) {
705 if (!mode_needs_gp_reg(get_irn_mode(node))) {
706 /* not a GP copy, ignore */
709 dreg = arch_get_irn_register(node);
710 sreg = arch_get_irn_register(be_get_Copy_op(node));
711 if (regmask & copymask & (1 << sreg->index)) {
714 if (regmask & copymask & (1 << dreg->index)) {
717 /* we CAN skip Copies if neither the destination nor the source
718 * is not in our regmask, ie none of our future Pop will overwrite it */
719 regmask |= (1 << dreg->index) | (1 << sreg->index);
720 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
726 /* we can handle only GP loads */
727 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
730 /* it has to use our predecessor sp value */
731 if (get_irn_n(node, n_ia32_base) != pred_sp) {
732 /* it would be ok if this load does not use a Pop result,
733 * but we do not check this */
737 /* should have NO index */
738 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
741 offset = get_ia32_am_offs_int(node);
742 /* we should NEVER access uninitialized stack BELOW the current SP */
745 /* storing at half-slots is bad */
746 if ((offset & 3) != 0)
749 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
751 /* ignore those outside the possible windows */
752 if (offset > inc_ofs - 4)
754 loadslot = offset >> 2;
756 /* loading from the same slot twice is bad (and shouldn't happen...) */
757 if (loads[loadslot] != NULL)
760 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
761 if (regmask & (1 << dreg->index)) {
762 /* this register is already used */
765 regmask |= 1 << dreg->index;
767 loads[loadslot] = node;
768 if (loadslot > maxslot)
775 /* find the first slot */
776 for (i = maxslot; i >= 0; --i) {
777 ir_node *load = loads[i];
783 ofs = inc_ofs - (maxslot + 1) * 4;
786 /* create a new IncSP if needed */
787 block = get_nodes_block(irn);
789 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
790 sched_add_before(irn, pred_sp);
793 /* walk through the Loads and create Pops for them */
794 for (++i; i <= maxslot; ++i) {
795 ir_node *load = loads[i];
797 const arch_register_t *reg;
799 mem = get_irn_n(load, n_ia32_mem);
800 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
802 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
803 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
805 copy_mark(load, pop);
807 /* create stackpointer Proj */
808 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
809 arch_set_irn_register(pred_sp, esp);
811 sched_add_before(irn, pop);
814 foreach_out_edge_safe(load, edge) {
815 ir_node *proj = get_edge_src_irn(edge);
817 set_Proj_pred(proj, pop);
820 /* we can remove the Load now */
825 be_set_IncSP_offset(irn, -ofs);
826 be_set_IncSP_pred(irn, pred_sp);
831 * Find a free GP register if possible, else return NULL.
833 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
835 be_irg_t *birg = be_birg_from_irg(irg);
838 for (i = 0; i < N_ia32_gp_REGS; ++i) {
839 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
840 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
843 if (be_peephole_get_value(reg->global_index) == NULL)
851 * Creates a Pop instruction before the given schedule point.
853 * @param dbgi debug info
854 * @param block the block
855 * @param stack the previous stack value
856 * @param schedpoint the new node is added before this node
857 * @param reg the register to pop
859 * @return the new stack value
861 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
862 ir_node *stack, ir_node *schedpoint,
863 const arch_register_t *reg)
865 const arch_register_t *esp = &ia32_registers[REG_ESP];
866 ir_graph *irg = get_irn_irg(block);
872 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
874 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
875 arch_set_irn_register(stack, esp);
876 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
877 arch_set_irn_register(val, reg);
879 sched_add_before(schedpoint, pop);
882 keep = be_new_Keep(block, 1, in);
883 sched_add_before(schedpoint, keep);
889 * Optimize an IncSp by replacing it with Push/Pop.
891 static void peephole_be_IncSP(ir_node *node)
893 const arch_register_t *esp = &ia32_registers[REG_ESP];
894 const arch_register_t *reg;
900 /* first optimize incsp->incsp combinations */
901 node = be_peephole_IncSP_IncSP(node);
903 /* transform IncSP->Store combinations to Push where possible */
904 peephole_IncSP_Store_to_push(node);
906 /* transform Load->IncSP combinations to Pop where possible */
907 peephole_Load_IncSP_to_pop(node);
909 if (arch_get_irn_register(node) != esp)
912 /* replace IncSP -4 by Pop freereg when possible */
913 offset = be_get_IncSP_offset(node);
914 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
915 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
916 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
917 (offset != +8 || ia32_cg_config.use_sub_esp_8))
921 /* we need a free register for pop */
922 reg = get_free_gp_reg(get_irn_irg(node));
926 dbgi = get_irn_dbg_info(node);
927 block = get_nodes_block(node);
928 stack = be_get_IncSP_pred(node);
930 stack = create_pop(dbgi, block, stack, node, reg);
933 stack = create_pop(dbgi, block, stack, node, reg);
936 dbgi = get_irn_dbg_info(node);
937 block = get_nodes_block(node);
938 stack = be_get_IncSP_pred(node);
939 stack = new_bd_ia32_PushEax(dbgi, block, stack);
940 arch_set_irn_register(stack, esp);
941 sched_add_before(node, stack);
944 stack = new_bd_ia32_PushEax(dbgi, block, stack);
945 arch_set_irn_register(stack, esp);
946 sched_add_before(node, stack);
950 be_peephole_exchange(node, stack);
954 * Peephole optimisation for ia32_Const's
956 static void peephole_ia32_Const(ir_node *node)
958 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
959 const arch_register_t *reg;
964 /* try to transform a mov 0, reg to xor reg reg */
965 if (attr->offset != 0 || attr->symconst != NULL)
967 if (ia32_cg_config.use_mov_0)
969 /* xor destroys the flags, so no-one must be using them */
970 if (be_peephole_get_value(REG_EFLAGS) != NULL)
973 reg = arch_get_irn_register(node);
974 assert(be_peephole_get_reg_value(reg) == NULL);
976 /* create xor(produceval, produceval) */
977 block = get_nodes_block(node);
978 dbgi = get_irn_dbg_info(node);
979 xorn = new_bd_ia32_Xor0(dbgi, block);
980 arch_set_irn_register(xorn, reg);
982 sched_add_before(node, xorn);
984 copy_mark(node, xorn);
985 be_peephole_exchange(node, xorn);
988 static inline int is_noreg(const ir_node *node)
990 return is_ia32_NoReg_GP(node);
993 ir_node *ia32_immediate_from_long(long val)
995 ir_graph *irg = current_ir_graph;
996 ir_node *start_block = get_irg_start_block(irg);
998 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
999 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
1004 static ir_node *create_immediate_from_am(const ir_node *node)
1006 ir_node *block = get_nodes_block(node);
1007 int offset = get_ia32_am_offs_int(node);
1008 int sc_sign = is_ia32_am_sc_sign(node);
1009 const ia32_attr_t *attr = get_ia32_attr_const(node);
1010 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1011 ir_entity *entity = get_ia32_am_sc(node);
1014 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1016 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1020 static int is_am_one(const ir_node *node)
1022 int offset = get_ia32_am_offs_int(node);
1023 ir_entity *entity = get_ia32_am_sc(node);
1025 return offset == 1 && entity == NULL;
1028 static int is_am_minus_one(const ir_node *node)
1030 int offset = get_ia32_am_offs_int(node);
1031 ir_entity *entity = get_ia32_am_sc(node);
1033 return offset == -1 && entity == NULL;
1037 * Transforms a LEA into an Add or SHL if possible.
1039 static void peephole_ia32_Lea(ir_node *node)
1043 const arch_register_t *base_reg;
1044 const arch_register_t *index_reg;
1045 const arch_register_t *out_reg;
1054 assert(is_ia32_Lea(node));
1056 /* we can only do this if it is allowed to clobber the flags */
1057 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1060 base = get_irn_n(node, n_ia32_Lea_base);
1061 index = get_irn_n(node, n_ia32_Lea_index);
1063 if (is_noreg(base)) {
1067 base_reg = arch_get_irn_register(base);
1069 if (is_noreg(index)) {
1073 index_reg = arch_get_irn_register(index);
1076 if (base == NULL && index == NULL) {
1077 /* we shouldn't construct these in the first place... */
1078 #ifdef DEBUG_libfirm
1079 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1084 out_reg = arch_get_irn_register(node);
1085 scale = get_ia32_am_scale(node);
1086 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1087 /* check if we have immediates values (frame entities should already be
1088 * expressed in the offsets) */
1089 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1095 /* we can transform leas where the out register is the same as either the
1096 * base or index register back to an Add or Shl */
1097 if (out_reg == base_reg) {
1098 if (index == NULL) {
1099 #ifdef DEBUG_libfirm
1100 if (!has_immediates) {
1101 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1106 goto make_add_immediate;
1108 if (scale == 0 && !has_immediates) {
1113 /* can't create an add */
1115 } else if (out_reg == index_reg) {
1117 if (has_immediates && scale == 0) {
1119 goto make_add_immediate;
1120 } else if (!has_immediates && scale > 0) {
1122 op2 = ia32_immediate_from_long(scale);
1124 } else if (!has_immediates) {
1125 #ifdef DEBUG_libfirm
1126 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1130 } else if (scale == 0 && !has_immediates) {
1135 /* can't create an add */
1138 /* can't create an add */
1143 if (ia32_cg_config.use_incdec) {
1144 if (is_am_one(node)) {
1145 dbgi = get_irn_dbg_info(node);
1146 block = get_nodes_block(node);
1147 res = new_bd_ia32_Inc(dbgi, block, op1);
1148 arch_set_irn_register(res, out_reg);
1151 if (is_am_minus_one(node)) {
1152 dbgi = get_irn_dbg_info(node);
1153 block = get_nodes_block(node);
1154 res = new_bd_ia32_Dec(dbgi, block, op1);
1155 arch_set_irn_register(res, out_reg);
1159 op2 = create_immediate_from_am(node);
1162 dbgi = get_irn_dbg_info(node);
1163 block = get_nodes_block(node);
1164 ir_graph *irg = get_irn_irg(node);
1165 ir_node *noreg = ia32_new_NoReg_gp(irg);
1166 ir_node *nomem = get_irg_no_mem(irg);
1167 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1168 arch_set_irn_register(res, out_reg);
1169 set_ia32_commutative(res);
1173 dbgi = get_irn_dbg_info(node);
1174 block = get_nodes_block(node);
1175 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1176 arch_set_irn_register(res, out_reg);
1180 SET_IA32_ORIG_NODE(res, node);
1182 /* add new ADD/SHL to schedule */
1183 DBG_OPT_LEA2ADD(node, res);
1185 /* exchange the Add and the LEA */
1186 sched_add_before(node, res);
1187 copy_mark(node, res);
1188 be_peephole_exchange(node, res);
1192 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1194 static void peephole_ia32_Imul_split(ir_node *imul)
1196 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1197 const arch_register_t *reg;
1200 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1201 /* no memory, imm form ignore */
1204 /* we need a free register */
1205 reg = get_free_gp_reg(get_irn_irg(imul));
1209 /* fine, we can rebuild it */
1210 res = ia32_turn_back_am(imul);
1211 arch_set_irn_register(res, reg);
1215 * Replace xorps r,r and xorpd r,r by pxor r,r
1217 static void peephole_ia32_xZero(ir_node *xorn)
1219 set_irn_op(xorn, op_ia32_xPzero);
1223 * Replace 16bit sign extension from ax to eax by shorter cwtl
1225 static void peephole_ia32_Conv_I2I(ir_node *node)
1227 const arch_register_t *eax = &ia32_registers[REG_EAX];
1228 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1229 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1234 if (get_mode_size_bits(smaller_mode) != 16 ||
1235 !mode_is_signed(smaller_mode) ||
1236 eax != arch_get_irn_register(val) ||
1237 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1240 dbgi = get_irn_dbg_info(node);
1241 block = get_nodes_block(node);
1242 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1243 arch_set_irn_register(cwtl, eax);
1244 sched_add_before(node, cwtl);
1245 be_peephole_exchange(node, cwtl);
1249 * Register a peephole optimisation function.
1251 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1253 assert(op->ops.generic == NULL);
1254 op->ops.generic = (op_func)func;
1257 /* Perform peephole-optimizations. */
1258 void ia32_peephole_optimization(ir_graph *irg)
1260 /* we currently do it in 2 passes because:
1261 * Lea -> Add could be usefull as flag producer for Test later
1265 ir_clear_opcodes_generic_func();
1266 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1267 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1268 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1269 if (ia32_cg_config.use_short_sex_eax)
1270 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1271 if (ia32_cg_config.use_pxor)
1272 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1273 if (! ia32_cg_config.use_imul_mem_imm32)
1274 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1275 be_peephole_opt(irg);
1278 ir_clear_opcodes_generic_func();
1279 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1280 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1281 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1282 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1283 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1284 be_peephole_opt(irg);
1288 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1289 * all its Projs are removed as well.
1290 * @param irn The irn to be removed from schedule
1292 static inline void try_kill(ir_node *node)
1294 if (get_irn_mode(node) == mode_T) {
1295 foreach_out_edge_safe(node, edge) {
1296 ir_node *proj = get_edge_src_irn(edge);
1301 if (get_irn_n_edges(node) != 0)
1304 if (sched_is_scheduled(node)) {
1311 static void optimize_conv_store(ir_node *node)
1316 ir_mode *store_mode;
1318 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1321 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1322 pred_proj = get_irn_n(node, n_ia32_Store_val);
1323 if (is_Proj(pred_proj)) {
1324 pred = get_Proj_pred(pred_proj);
1328 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1330 if (get_ia32_op_type(pred) != ia32_Normal)
1333 /* the store only stores the lower bits, so we only need the conv
1334 * it it shrinks the mode */
1335 conv_mode = get_ia32_ls_mode(pred);
1336 store_mode = get_ia32_ls_mode(node);
1337 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1340 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Store(Conv) (%+F, %+F)\n", node, pred);
1341 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1342 if (get_irn_n_edges(pred_proj) == 0) {
1343 kill_node(pred_proj);
1344 if (pred != pred_proj)
1349 static void optimize_load_conv(ir_node *node)
1351 ir_node *pred, *predpred;
1355 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1358 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1359 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1363 predpred = get_Proj_pred(pred);
1364 if (!is_ia32_Load(predpred))
1367 /* the load is sign extending the upper bits, so we only need the conv
1368 * if it shrinks the mode */
1369 load_mode = get_ia32_ls_mode(predpred);
1370 conv_mode = get_ia32_ls_mode(node);
1371 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1374 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1375 /* change the load if it has only 1 user */
1376 if (get_irn_n_edges(pred) == 1) {
1378 if (get_mode_sign(conv_mode)) {
1379 newmode = find_signed_mode(load_mode);
1381 newmode = find_unsigned_mode(load_mode);
1383 assert(newmode != NULL);
1384 set_ia32_ls_mode(predpred, newmode);
1386 /* otherwise we have to keep the conv */
1392 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Load) (%+F, %+F)\n", node, predpred);
1393 exchange(node, pred);
1396 static void optimize_conv_conv(ir_node *node)
1398 ir_node *pred_proj, *pred, *result_conv;
1399 ir_mode *pred_mode, *conv_mode;
1403 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1406 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1407 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1408 if (is_Proj(pred_proj))
1409 pred = get_Proj_pred(pred_proj);
1413 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1416 /* we know that after a conv, the upper bits are sign extended
1417 * so we only need the 2nd conv if it shrinks the mode */
1418 conv_mode = get_ia32_ls_mode(node);
1419 conv_mode_bits = get_mode_size_bits(conv_mode);
1420 pred_mode = get_ia32_ls_mode(pred);
1421 pred_mode_bits = get_mode_size_bits(pred_mode);
1423 if (conv_mode_bits == pred_mode_bits
1424 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1425 result_conv = pred_proj;
1426 } else if (conv_mode_bits <= pred_mode_bits) {
1427 /* if 2nd conv is smaller then first conv, then we can always take the
1429 if (get_irn_n_edges(pred_proj) == 1) {
1430 result_conv = pred_proj;
1431 set_ia32_ls_mode(pred, conv_mode);
1433 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1434 if (get_mode_size_bits(conv_mode) == 8) {
1435 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1436 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1437 arch_set_irn_register_reqs_in(pred, reqs);
1440 /* we don't want to end up with 2 loads, so we better do nothing */
1441 if (get_irn_mode(pred) == mode_T) {
1445 result_conv = exact_copy(pred);
1446 set_ia32_ls_mode(result_conv, conv_mode);
1448 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1449 if (get_mode_size_bits(conv_mode) == 8) {
1450 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1451 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1452 arch_set_irn_register_reqs_in(result_conv, reqs);
1456 /* if both convs have the same sign, then we can take the smaller one */
1457 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1458 result_conv = pred_proj;
1460 /* no optimisation possible if smaller conv is sign-extend */
1461 if (mode_is_signed(pred_mode)) {
1464 /* we can take the smaller conv if it is unsigned */
1465 result_conv = pred_proj;
1469 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Conv) (%+F, %+F)\n", node, pred);
1470 /* Some user (like Phis) won't be happy if we change the mode. */
1471 set_irn_mode(result_conv, get_irn_mode(node));
1474 exchange(node, result_conv);
1476 if (get_irn_n_edges(pred_proj) == 0) {
1477 kill_node(pred_proj);
1478 if (pred != pred_proj)
1481 optimize_conv_conv(result_conv);
1484 static void optimize_node(ir_node *node, void *env)
1488 optimize_load_conv(node);
1489 optimize_conv_store(node);
1490 optimize_conv_conv(node);
1494 * Performs conv and address mode optimization.
1496 void ia32_optimize_graph(ir_graph *irg)
1498 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1501 void ia32_init_optimize(void)
1503 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");