2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
31 #include "firm_types.h"
40 #include "firmstat_t.h"
46 #include "bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_architecture.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 static void copy_mark(const ir_node *old, ir_node *newn)
61 if (is_ia32_is_reload(old))
62 set_ia32_is_reload(newn);
63 if (is_ia32_is_spill(old))
64 set_ia32_is_spill(newn);
65 if (is_ia32_is_remat(old))
66 set_ia32_is_remat(newn);
69 typedef enum produces_flag_t {
72 produces_zero_in_carry
76 * Return which usable flag the given node produces about the result.
77 * That is zero (ZF) and sign(SF).
78 * We do not check for carry (CF) or overflow (OF).
80 * @param node the node to check
81 * @param pn the projection number of the used result
83 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
86 const ia32_immediate_attr_t *imm_attr;
88 if (!is_ia32_irn(node))
89 return produces_no_flag;
91 switch (get_ia32_irn_opcode(node)) {
106 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
107 count = get_irn_n(node, n_ia32_ShlD_count);
108 goto check_shift_amount;
113 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
114 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
115 count = get_irn_n(node, n_ia32_Shl_count);
117 /* when shift count is zero the flags are not affected, so we can only
118 * do this for constants != 0 */
119 if (!is_ia32_Immediate(count))
120 return produces_no_flag;
122 imm_attr = get_ia32_immediate_attr_const(count);
123 if (imm_attr->symconst != NULL)
124 return produces_no_flag;
125 if ((imm_attr->offset & 0x1f) == 0)
126 return produces_no_flag;
130 return pn == pn_ia32_Mul_res_high ?
131 produces_zero_in_carry : produces_no_flag;
134 return produces_no_flag;
137 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
141 * Replace Cmp(x, 0) by a Test(x, x)
143 static void peephole_ia32_Cmp(ir_node *const node)
145 if (get_ia32_op_type(node) != ia32_Normal)
148 ir_node *const right = get_irn_n(node, n_ia32_Cmp_right);
149 if (!is_ia32_Immediate(right))
152 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
153 if (imm->symconst != NULL || imm->offset != 0)
156 dbg_info *const dbgi = get_irn_dbg_info(node);
157 ir_node *const block = get_nodes_block(node);
158 ir_graph *const irg = get_Block_irg(block);
159 ir_node *const noreg = ia32_new_NoReg_gp(irg);
160 ir_node *const nomem = get_irg_no_mem(irg);
161 ir_node *const op = get_irn_n(node, n_ia32_Cmp_left);
162 int const ins_permuted = get_ia32_attr(node)->data.ins_permuted;
165 if (is_ia32_Cmp(node)) {
166 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem, op, op, ins_permuted);
168 test = new_bd_ia32_Test_8bit(dbgi, block, noreg, noreg, nomem, op, op, ins_permuted);
170 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
172 arch_register_t const *const reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
173 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
175 foreach_out_edge_safe(node, edge) {
176 ir_node *const user = get_edge_src_irn(edge);
179 exchange(user, test);
182 sched_add_before(node, test);
183 copy_mark(node, test);
184 be_peephole_exchange(node, test);
188 * Peephole optimization for Test instructions.
189 * - Remove the Test, if an appropriate flag was produced which is still live
190 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
192 static void peephole_ia32_Test(ir_node *node)
194 ir_node *left = get_irn_n(node, n_ia32_Test_left);
195 ir_node *right = get_irn_n(node, n_ia32_Test_right);
197 if (left == right) { /* we need a test for 0 */
198 ir_node *block = get_nodes_block(node);
199 int pn = pn_ia32_res;
205 produces_flag_t produced;
207 if (get_nodes_block(left) != block)
211 pn = get_Proj_proj(op);
212 op = get_Proj_pred(op);
215 /* walk schedule up and abort when we find left or some other node
216 * destroys the flags */
219 schedpoint = sched_prev(schedpoint);
220 if (schedpoint == op)
222 if (arch_irn_is(schedpoint, modify_flags))
224 if (schedpoint == block)
225 panic("couldn't find left");
228 produced = check_produces_zero_sign(op, pn);
229 if (produced == produces_no_flag)
232 /* make sure users only look at the sign/zero flag */
233 foreach_out_edge(node, edge) {
234 ir_node *user = get_edge_src_irn(edge);
235 ia32_condition_code_t cc = get_ia32_condcode(user);
237 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
239 if (produced == produces_zero_sign
240 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
246 op_mode = get_ia32_ls_mode(op);
248 op_mode = get_irn_mode(op);
250 /* Make sure we operate on the same bit size */
251 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
254 if (produced == produces_zero_in_carry) {
255 /* patch users to look at the carry instead of the zero flag */
256 foreach_out_edge(node, edge) {
257 ir_node *user = get_edge_src_irn(edge);
258 ia32_condition_code_t cc = get_ia32_condcode(user);
261 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
262 case ia32_cc_not_equal: cc = ia32_cc_below; break;
263 default: panic("unexpected pn");
265 set_ia32_condcode(user, cc);
269 if (get_irn_mode(op) != mode_T) {
270 set_irn_mode(op, mode_T);
272 /* If there are other users, reroute them to result proj */
273 if (get_irn_n_edges(op) != 2) {
274 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
275 edges_reroute_except(op, res, res);
278 if (get_irn_n_edges(left) == 2)
282 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
283 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
284 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
286 assert(get_irn_mode(node) != mode_T);
288 be_peephole_exchange(node, flags_proj);
289 } else if (is_ia32_Immediate(right)) {
290 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
293 /* A test with a symconst is rather strange, but better safe than sorry */
294 if (imm->symconst != NULL)
297 offset = imm->offset;
298 if (get_ia32_op_type(node) == ia32_AddrModeS) {
299 ia32_attr_t *const attr = get_ia32_attr(node);
300 ir_graph *const irg = get_irn_irg(node);
302 if ((offset & 0xFFFFFF00) == 0) {
303 /* attr->am_offs += 0; */
304 } else if ((offset & 0xFFFF00FF) == 0) {
305 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 8);
306 set_irn_n(node, n_ia32_Test_right, imm_node);
308 } else if ((offset & 0xFF00FFFF) == 0) {
309 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 16);
310 set_irn_n(node, n_ia32_Test_right, imm_node);
312 } else if ((offset & 0x00FFFFFF) == 0) {
313 ir_node *imm_node = ia32_create_Immediate(irg, NULL, 0, offset >> 24);
314 set_irn_n(node, n_ia32_Test_right, imm_node);
319 } else if (offset < 256) {
320 arch_register_t const* const reg = arch_get_irn_register(left);
322 if (reg != &ia32_registers[REG_EAX] &&
323 reg != &ia32_registers[REG_EBX] &&
324 reg != &ia32_registers[REG_ECX] &&
325 reg != &ia32_registers[REG_EDX]) {
332 /* Technically we should build a Test8Bit because of the register
333 * constraints, but nobody changes registers at this point anymore. */
334 set_ia32_ls_mode(node, mode_Bu);
339 * AMD Athlon works faster when RET is not destination of
340 * conditional jump or directly preceded by other jump instruction.
341 * Can be avoided by placing a Rep prefix before the return.
343 static void peephole_ia32_Return(ir_node *node)
345 if (!ia32_cg_config.use_pad_return)
348 /* check if this return is the first on the block */
349 sched_foreach_reverse_from(node, irn) {
350 switch (get_irn_opcode(irn)) {
352 /* the return node itself, ignore */
356 /* ignore no code generated */
359 /* arg, IncSP 0 nodes might occur, ignore these */
360 if (be_get_IncSP_offset(irn) == 0)
370 /* ensure, that the 3 byte return is generated */
371 be_Return_set_emit_pop(node, 1);
374 /* only optimize up to 48 stores behind IncSPs */
375 #define MAXPUSH_OPTIMIZE 48
378 * Tries to create Push's from IncSP, Store combinations.
379 * The Stores are replaced by Push's, the IncSP is modified
380 * (possibly into IncSP 0, but not removed).
382 static void peephole_IncSP_Store_to_push(ir_node *irn)
388 ir_node *stores[MAXPUSH_OPTIMIZE];
393 ir_node *first_push = NULL;
395 memset(stores, 0, sizeof(stores));
397 assert(be_is_IncSP(irn));
399 inc_ofs = be_get_IncSP_offset(irn);
404 * We first walk the schedule after the IncSP node as long as we find
405 * suitable Stores that could be transformed to a Push.
406 * We save them into the stores array which is sorted by the frame offset/4
407 * attached to the node
410 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
415 /* it has to be a Store */
416 if (!is_ia32_Store(node))
419 /* it has to use our sp value */
420 if (get_irn_n(node, n_ia32_base) != irn)
422 /* Store has to be attached to NoMem */
423 mem = get_irn_n(node, n_ia32_mem);
427 /* unfortunately we can't support the full AMs possible for push at the
428 * moment. TODO: fix this */
429 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
432 offset = get_ia32_am_offs_int(node);
433 /* we should NEVER access uninitialized stack BELOW the current SP */
436 /* storing at half-slots is bad */
437 if ((offset & 3) != 0)
440 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
442 storeslot = offset >> 2;
444 /* storing into the same slot twice is bad (and shouldn't happen...) */
445 if (stores[storeslot] != NULL)
448 stores[storeslot] = node;
449 if (storeslot > maxslot)
455 for (i = -1; i < maxslot; ++i) {
456 if (stores[i + 1] == NULL)
460 /* walk through the Stores and create Pushs for them */
461 block = get_nodes_block(irn);
462 spmode = get_irn_mode(irn);
463 irg = get_irn_irg(irn);
464 for (; i >= 0; --i) {
465 const arch_register_t *spreg;
467 ir_node *val, *mem, *mem_proj;
468 ir_node *store = stores[i];
469 ir_node *noreg = ia32_new_NoReg_gp(irg);
471 val = get_irn_n(store, n_ia32_unary_op);
472 mem = get_irn_n(store, n_ia32_mem);
473 spreg = arch_get_irn_register(curr_sp);
475 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
477 copy_mark(store, push);
479 if (first_push == NULL)
482 sched_add_after(skip_Proj(curr_sp), push);
484 /* create stackpointer Proj */
485 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
486 arch_set_irn_register(curr_sp, spreg);
488 /* create memory Proj */
489 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
491 /* rewire Store Projs */
492 foreach_out_edge_safe(store, edge) {
493 ir_node *proj = get_edge_src_irn(edge);
496 switch (get_Proj_proj(proj)) {
497 case pn_ia32_Store_M:
498 exchange(proj, mem_proj);
501 panic("unexpected Proj on Store->IncSp");
505 /* use the memproj now */
506 be_peephole_exchange(store, push);
511 foreach_out_edge_safe(irn, edge) {
512 ir_node *const src = get_edge_src_irn(edge);
513 int const pos = get_edge_src_pos(edge);
515 if (src == first_push)
518 set_irn_n(src, pos, curr_sp);
521 be_set_IncSP_offset(irn, inc_ofs);
526 * Creates a Push instruction before the given schedule point.
528 * @param dbgi debug info
529 * @param block the block
530 * @param stack the previous stack value
531 * @param schedpoint the new node is added before this node
532 * @param reg the register to pop
534 * @return the new stack value
536 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
537 ir_node *stack, ir_node *schedpoint)
539 const arch_register_t *esp = &ia32_registers[REG_ESP];
541 ir_node *val = ia32_new_NoReg_gp(cg);
542 ir_node *noreg = ia32_new_NoReg_gp(cg);
543 ir_graph *irg = get_irn_irg(block);
544 ir_node *nomem = get_irg_no_mem(irg);
545 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
546 sched_add_before(schedpoint, push);
548 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
549 arch_set_irn_register(stack, esp);
554 static void peephole_store_incsp(ir_node *store)
564 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
565 if (!be_is_IncSP(am_base)
566 || get_nodes_block(am_base) != get_nodes_block(store))
568 mem = get_irn_n(store, n_ia32_Store_mem);
569 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
573 int incsp_offset = be_get_IncSP_offset(am_base);
574 if (incsp_offset <= 0)
577 /* we have to be at offset 0 */
578 int my_offset = get_ia32_am_offs_int(store);
579 if (my_offset != 0) {
580 /* TODO here: find out whether there is a store with offset 0 before
581 * us and whether we can move it down to our place */
584 ir_mode *ls_mode = get_ia32_ls_mode(store);
585 int my_store_size = get_mode_size_bytes(ls_mode);
587 if (my_offset + my_store_size > incsp_offset)
590 /* correctness checking:
591 - noone else must write to that stackslot
592 (because after translation incsp won't allocate it anymore)
594 sched_foreach_reverse_from(store, node) {
600 /* make sure noone else can use the space on the stack */
601 arity = get_irn_arity(node);
602 for (i = 0; i < arity; ++i) {
603 ir_node *pred = get_irn_n(node, i);
607 if (i == n_ia32_base &&
608 (get_ia32_op_type(node) == ia32_AddrModeS
609 || get_ia32_op_type(node) == ia32_AddrModeD)) {
610 int node_offset = get_ia32_am_offs_int(node);
611 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
612 int node_size = get_mode_size_bytes(node_ls_mode);
613 /* overlapping with our position? abort */
614 if (node_offset < my_offset + my_store_size
615 && node_offset + node_size >= my_offset)
617 /* otherwise it's fine */
621 /* strange use of esp: abort */
626 /* all ok, change to push */
627 dbgi = get_irn_dbg_info(store);
628 block = get_nodes_block(store);
629 noreg = ia32_new_NoReg_gp(cg);
630 val = get_irn_n(store, n_ia32_Store_val);
632 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
634 create_push(dbgi, block, am_base, store);
639 * Return true if a mode can be stored in the GP register set
641 static inline int mode_needs_gp_reg(ir_mode *mode)
643 if (mode == ia32_mode_fpcw)
645 if (get_mode_size_bits(mode) > 32)
647 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
651 * Tries to create Pops from Load, IncSP combinations.
652 * The Loads are replaced by Pops, the IncSP is modified
653 * (possibly into IncSP 0, but not removed).
655 static void peephole_Load_IncSP_to_pop(ir_node *irn)
657 const arch_register_t *esp = &ia32_registers[REG_ESP];
658 int i, maxslot, inc_ofs, ofs;
659 ir_node *node, *pred_sp, *block;
660 ir_node *loads[MAXPUSH_OPTIMIZE];
661 unsigned regmask = 0;
662 unsigned copymask = ~0;
664 memset(loads, 0, sizeof(loads));
665 assert(be_is_IncSP(irn));
667 inc_ofs = -be_get_IncSP_offset(irn);
672 * We first walk the schedule before the IncSP node as long as we find
673 * suitable Loads that could be transformed to a Pop.
674 * We save them into the stores array which is sorted by the frame offset/4
675 * attached to the node
678 pred_sp = be_get_IncSP_pred(irn);
679 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
682 const arch_register_t *sreg, *dreg;
684 /* it has to be a Load */
685 if (!is_ia32_Load(node)) {
686 if (be_is_Copy(node)) {
687 if (!mode_needs_gp_reg(get_irn_mode(node))) {
688 /* not a GP copy, ignore */
691 dreg = arch_get_irn_register(node);
692 sreg = arch_get_irn_register(be_get_Copy_op(node));
693 if (regmask & copymask & (1 << sreg->index)) {
696 if (regmask & copymask & (1 << dreg->index)) {
699 /* we CAN skip Copies if neither the destination nor the source
700 * is not in our regmask, ie none of our future Pop will overwrite it */
701 regmask |= (1 << dreg->index) | (1 << sreg->index);
702 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
708 /* we can handle only GP loads */
709 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
712 /* it has to use our predecessor sp value */
713 if (get_irn_n(node, n_ia32_base) != pred_sp) {
714 /* it would be ok if this load does not use a Pop result,
715 * but we do not check this */
719 /* should have NO index */
720 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
723 offset = get_ia32_am_offs_int(node);
724 /* we should NEVER access uninitialized stack BELOW the current SP */
727 /* storing at half-slots is bad */
728 if ((offset & 3) != 0)
731 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
733 /* ignore those outside the possible windows */
734 if (offset > inc_ofs - 4)
736 loadslot = offset >> 2;
738 /* loading from the same slot twice is bad (and shouldn't happen...) */
739 if (loads[loadslot] != NULL)
742 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
743 if (regmask & (1 << dreg->index)) {
744 /* this register is already used */
747 regmask |= 1 << dreg->index;
749 loads[loadslot] = node;
750 if (loadslot > maxslot)
757 /* find the first slot */
758 for (i = maxslot; i >= 0; --i) {
759 ir_node *load = loads[i];
765 ofs = inc_ofs - (maxslot + 1) * 4;
768 /* create a new IncSP if needed */
769 block = get_nodes_block(irn);
771 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
772 sched_add_before(irn, pred_sp);
775 /* walk through the Loads and create Pops for them */
776 for (++i; i <= maxslot; ++i) {
777 ir_node *load = loads[i];
779 const arch_register_t *reg;
781 mem = get_irn_n(load, n_ia32_mem);
782 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
784 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
785 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
787 copy_mark(load, pop);
789 /* create stackpointer Proj */
790 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
791 arch_set_irn_register(pred_sp, esp);
793 sched_add_before(irn, pop);
796 foreach_out_edge_safe(load, edge) {
797 ir_node *proj = get_edge_src_irn(edge);
799 set_Proj_pred(proj, pop);
802 /* we can remove the Load now */
807 be_set_IncSP_offset(irn, -ofs);
808 be_set_IncSP_pred(irn, pred_sp);
813 * Find a free GP register if possible, else return NULL.
815 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
817 be_irg_t *birg = be_birg_from_irg(irg);
820 for (i = 0; i < N_ia32_gp_REGS; ++i) {
821 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
822 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
825 if (be_peephole_get_value(reg->global_index) == NULL)
833 * Creates a Pop instruction before the given schedule point.
835 * @param dbgi debug info
836 * @param block the block
837 * @param stack the previous stack value
838 * @param schedpoint the new node is added before this node
839 * @param reg the register to pop
841 * @return the new stack value
843 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
844 ir_node *stack, ir_node *schedpoint,
845 const arch_register_t *reg)
847 const arch_register_t *esp = &ia32_registers[REG_ESP];
848 ir_graph *irg = get_irn_irg(block);
854 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
856 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
857 arch_set_irn_register(stack, esp);
858 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
859 arch_set_irn_register(val, reg);
861 sched_add_before(schedpoint, pop);
864 keep = be_new_Keep(block, 1, in);
865 sched_add_before(schedpoint, keep);
871 * Optimize an IncSp by replacing it with Push/Pop.
873 static void peephole_be_IncSP(ir_node *node)
875 const arch_register_t *esp = &ia32_registers[REG_ESP];
876 const arch_register_t *reg;
882 /* first optimize incsp->incsp combinations */
883 node = be_peephole_IncSP_IncSP(node);
885 /* transform IncSP->Store combinations to Push where possible */
886 peephole_IncSP_Store_to_push(node);
888 /* transform Load->IncSP combinations to Pop where possible */
889 peephole_Load_IncSP_to_pop(node);
891 if (arch_get_irn_register(node) != esp)
894 /* replace IncSP -4 by Pop freereg when possible */
895 offset = be_get_IncSP_offset(node);
896 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
897 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
898 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
899 (offset != +8 || ia32_cg_config.use_sub_esp_8))
903 /* we need a free register for pop */
904 reg = get_free_gp_reg(get_irn_irg(node));
908 dbgi = get_irn_dbg_info(node);
909 block = get_nodes_block(node);
910 stack = be_get_IncSP_pred(node);
912 stack = create_pop(dbgi, block, stack, node, reg);
915 stack = create_pop(dbgi, block, stack, node, reg);
918 dbgi = get_irn_dbg_info(node);
919 block = get_nodes_block(node);
920 stack = be_get_IncSP_pred(node);
921 stack = new_bd_ia32_PushEax(dbgi, block, stack);
922 arch_set_irn_register(stack, esp);
923 sched_add_before(node, stack);
926 stack = new_bd_ia32_PushEax(dbgi, block, stack);
927 arch_set_irn_register(stack, esp);
928 sched_add_before(node, stack);
932 be_peephole_exchange(node, stack);
936 * Peephole optimisation for ia32_Const's
938 static void peephole_ia32_Const(ir_node *node)
940 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
941 const arch_register_t *reg;
946 /* try to transform a mov 0, reg to xor reg reg */
947 if (attr->offset != 0 || attr->symconst != NULL)
949 if (ia32_cg_config.use_mov_0)
951 /* xor destroys the flags, so no-one must be using them */
952 if (be_peephole_get_value(REG_EFLAGS) != NULL)
955 reg = arch_get_irn_register(node);
956 assert(be_peephole_get_reg_value(reg) == NULL);
958 /* create xor(produceval, produceval) */
959 block = get_nodes_block(node);
960 dbgi = get_irn_dbg_info(node);
961 xorn = new_bd_ia32_Xor0(dbgi, block);
962 arch_set_irn_register(xorn, reg);
964 sched_add_before(node, xorn);
966 copy_mark(node, xorn);
967 be_peephole_exchange(node, xorn);
970 static inline int is_noreg(const ir_node *node)
972 return is_ia32_NoReg_GP(node);
975 ir_node *ia32_immediate_from_long(long val)
977 ir_graph *irg = current_ir_graph;
978 ir_node *start_block = get_irg_start_block(irg);
980 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
981 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
986 static ir_node *create_immediate_from_am(const ir_node *node)
988 ir_node *block = get_nodes_block(node);
989 int offset = get_ia32_am_offs_int(node);
990 int sc_sign = is_ia32_am_sc_sign(node);
991 const ia32_attr_t *attr = get_ia32_attr_const(node);
992 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
993 ir_entity *entity = get_ia32_am_sc(node);
996 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
998 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1002 static int is_am_one(const ir_node *node)
1004 int offset = get_ia32_am_offs_int(node);
1005 ir_entity *entity = get_ia32_am_sc(node);
1007 return offset == 1 && entity == NULL;
1010 static int is_am_minus_one(const ir_node *node)
1012 int offset = get_ia32_am_offs_int(node);
1013 ir_entity *entity = get_ia32_am_sc(node);
1015 return offset == -1 && entity == NULL;
1019 * Transforms a LEA into an Add or SHL if possible.
1021 static void peephole_ia32_Lea(ir_node *node)
1025 const arch_register_t *base_reg;
1026 const arch_register_t *index_reg;
1027 const arch_register_t *out_reg;
1036 assert(is_ia32_Lea(node));
1038 /* we can only do this if it is allowed to clobber the flags */
1039 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1042 base = get_irn_n(node, n_ia32_Lea_base);
1043 index = get_irn_n(node, n_ia32_Lea_index);
1045 if (is_noreg(base)) {
1049 base_reg = arch_get_irn_register(base);
1051 if (is_noreg(index)) {
1055 index_reg = arch_get_irn_register(index);
1058 if (base == NULL && index == NULL) {
1059 /* we shouldn't construct these in the first place... */
1060 #ifdef DEBUG_libfirm
1061 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1066 out_reg = arch_get_irn_register(node);
1067 scale = get_ia32_am_scale(node);
1068 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1069 /* check if we have immediates values (frame entities should already be
1070 * expressed in the offsets) */
1071 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1077 /* we can transform leas where the out register is the same as either the
1078 * base or index register back to an Add or Shl */
1079 if (out_reg == base_reg) {
1080 if (index == NULL) {
1081 #ifdef DEBUG_libfirm
1082 if (!has_immediates) {
1083 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1088 goto make_add_immediate;
1090 if (scale == 0 && !has_immediates) {
1095 /* can't create an add */
1097 } else if (out_reg == index_reg) {
1099 if (has_immediates && scale == 0) {
1101 goto make_add_immediate;
1102 } else if (!has_immediates && scale > 0) {
1104 op2 = ia32_immediate_from_long(scale);
1106 } else if (!has_immediates) {
1107 #ifdef DEBUG_libfirm
1108 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1112 } else if (scale == 0 && !has_immediates) {
1117 /* can't create an add */
1120 /* can't create an add */
1125 if (ia32_cg_config.use_incdec) {
1126 if (is_am_one(node)) {
1127 dbgi = get_irn_dbg_info(node);
1128 block = get_nodes_block(node);
1129 res = new_bd_ia32_Inc(dbgi, block, op1);
1130 arch_set_irn_register(res, out_reg);
1133 if (is_am_minus_one(node)) {
1134 dbgi = get_irn_dbg_info(node);
1135 block = get_nodes_block(node);
1136 res = new_bd_ia32_Dec(dbgi, block, op1);
1137 arch_set_irn_register(res, out_reg);
1141 op2 = create_immediate_from_am(node);
1144 dbgi = get_irn_dbg_info(node);
1145 block = get_nodes_block(node);
1146 ir_graph *irg = get_irn_irg(node);
1147 ir_node *noreg = ia32_new_NoReg_gp(irg);
1148 ir_node *nomem = get_irg_no_mem(irg);
1149 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1150 arch_set_irn_register(res, out_reg);
1151 set_ia32_commutative(res);
1155 dbgi = get_irn_dbg_info(node);
1156 block = get_nodes_block(node);
1157 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1158 arch_set_irn_register(res, out_reg);
1162 SET_IA32_ORIG_NODE(res, node);
1164 /* add new ADD/SHL to schedule */
1165 DBG_OPT_LEA2ADD(node, res);
1167 /* exchange the Add and the LEA */
1168 sched_add_before(node, res);
1169 copy_mark(node, res);
1170 be_peephole_exchange(node, res);
1174 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1176 static void peephole_ia32_Imul_split(ir_node *imul)
1178 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1179 const arch_register_t *reg;
1182 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1183 /* no memory, imm form ignore */
1186 /* we need a free register */
1187 reg = get_free_gp_reg(get_irn_irg(imul));
1191 /* fine, we can rebuild it */
1192 res = ia32_turn_back_am(imul);
1193 arch_set_irn_register(res, reg);
1197 * Replace xorps r,r and xorpd r,r by pxor r,r
1199 static void peephole_ia32_xZero(ir_node *xorn)
1201 set_irn_op(xorn, op_ia32_xPzero);
1205 * Replace 16bit sign extension from ax to eax by shorter cwtl
1207 static void peephole_ia32_Conv_I2I(ir_node *node)
1209 const arch_register_t *eax = &ia32_registers[REG_EAX];
1210 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1211 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1216 if (get_mode_size_bits(smaller_mode) != 16 ||
1217 !mode_is_signed(smaller_mode) ||
1218 eax != arch_get_irn_register(val) ||
1219 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1222 dbgi = get_irn_dbg_info(node);
1223 block = get_nodes_block(node);
1224 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1225 arch_set_irn_register(cwtl, eax);
1226 sched_add_before(node, cwtl);
1227 be_peephole_exchange(node, cwtl);
1231 * Register a peephole optimisation function.
1233 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1235 assert(op->ops.generic == NULL);
1236 op->ops.generic = (op_func)func;
1239 /* Perform peephole-optimizations. */
1240 void ia32_peephole_optimization(ir_graph *irg)
1242 /* we currently do it in 2 passes because:
1243 * Lea -> Add could be usefull as flag producer for Test later
1247 ir_clear_opcodes_generic_func();
1248 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1249 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1250 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1251 if (ia32_cg_config.use_short_sex_eax)
1252 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1253 if (ia32_cg_config.use_pxor)
1254 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1255 if (! ia32_cg_config.use_imul_mem_imm32)
1256 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1257 be_peephole_opt(irg);
1260 ir_clear_opcodes_generic_func();
1261 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1262 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1263 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1264 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1265 be_peephole_opt(irg);
1269 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1270 * all its Projs are removed as well.
1271 * @param irn The irn to be removed from schedule
1273 static inline void try_kill(ir_node *node)
1275 if (get_irn_mode(node) == mode_T) {
1276 foreach_out_edge_safe(node, edge) {
1277 ir_node *proj = get_edge_src_irn(edge);
1282 if (get_irn_n_edges(node) != 0)
1285 if (sched_is_scheduled(node)) {
1292 static void optimize_conv_store(ir_node *node)
1297 ir_mode *store_mode;
1299 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1302 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1303 pred_proj = get_irn_n(node, n_ia32_Store_val);
1304 if (is_Proj(pred_proj)) {
1305 pred = get_Proj_pred(pred_proj);
1309 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1311 if (get_ia32_op_type(pred) != ia32_Normal)
1314 /* the store only stores the lower bits, so we only need the conv
1315 * it it shrinks the mode */
1316 conv_mode = get_ia32_ls_mode(pred);
1317 store_mode = get_ia32_ls_mode(node);
1318 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1321 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Store(Conv) (%+F, %+F)\n", node, pred);
1322 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1323 if (get_irn_n_edges(pred_proj) == 0) {
1324 kill_node(pred_proj);
1325 if (pred != pred_proj)
1330 static void optimize_load_conv(ir_node *node)
1332 ir_node *pred, *predpred;
1336 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1339 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1340 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1344 predpred = get_Proj_pred(pred);
1345 if (!is_ia32_Load(predpred))
1348 /* the load is sign extending the upper bits, so we only need the conv
1349 * if it shrinks the mode */
1350 load_mode = get_ia32_ls_mode(predpred);
1351 conv_mode = get_ia32_ls_mode(node);
1352 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1355 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1356 /* change the load if it has only 1 user */
1357 if (get_irn_n_edges(pred) == 1) {
1359 if (get_mode_sign(conv_mode)) {
1360 newmode = find_signed_mode(load_mode);
1362 newmode = find_unsigned_mode(load_mode);
1364 assert(newmode != NULL);
1365 set_ia32_ls_mode(predpred, newmode);
1367 /* otherwise we have to keep the conv */
1373 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Load) (%+F, %+F)\n", node, predpred);
1374 exchange(node, pred);
1377 static void optimize_conv_conv(ir_node *node)
1379 ir_node *pred_proj, *pred, *result_conv;
1380 ir_mode *pred_mode, *conv_mode;
1384 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1387 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1388 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1389 if (is_Proj(pred_proj))
1390 pred = get_Proj_pred(pred_proj);
1394 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1397 /* we know that after a conv, the upper bits are sign extended
1398 * so we only need the 2nd conv if it shrinks the mode */
1399 conv_mode = get_ia32_ls_mode(node);
1400 conv_mode_bits = get_mode_size_bits(conv_mode);
1401 pred_mode = get_ia32_ls_mode(pred);
1402 pred_mode_bits = get_mode_size_bits(pred_mode);
1404 if (conv_mode_bits == pred_mode_bits
1405 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1406 result_conv = pred_proj;
1407 } else if (conv_mode_bits <= pred_mode_bits) {
1408 /* if 2nd conv is smaller then first conv, then we can always take the
1410 if (get_irn_n_edges(pred_proj) == 1) {
1411 result_conv = pred_proj;
1412 set_ia32_ls_mode(pred, conv_mode);
1414 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1415 if (get_mode_size_bits(conv_mode) == 8) {
1416 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1417 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1418 arch_set_irn_register_reqs_in(pred, reqs);
1421 /* we don't want to end up with 2 loads, so we better do nothing */
1422 if (get_irn_mode(pred) == mode_T) {
1426 result_conv = exact_copy(pred);
1427 set_ia32_ls_mode(result_conv, conv_mode);
1429 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1430 if (get_mode_size_bits(conv_mode) == 8) {
1431 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1432 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1433 arch_set_irn_register_reqs_in(result_conv, reqs);
1437 /* if both convs have the same sign, then we can take the smaller one */
1438 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1439 result_conv = pred_proj;
1441 /* no optimisation possible if smaller conv is sign-extend */
1442 if (mode_is_signed(pred_mode)) {
1445 /* we can take the smaller conv if it is unsigned */
1446 result_conv = pred_proj;
1450 ir_fprintf(stderr, "Optimisation warning: unoptimized ia32 Conv(Conv) (%+F, %+F)\n", node, pred);
1451 /* Some user (like Phis) won't be happy if we change the mode. */
1452 set_irn_mode(result_conv, get_irn_mode(node));
1455 exchange(node, result_conv);
1457 if (get_irn_n_edges(pred_proj) == 0) {
1458 kill_node(pred_proj);
1459 if (pred != pred_proj)
1462 optimize_conv_conv(result_conv);
1465 static void optimize_node(ir_node *node, void *env)
1469 optimize_load_conv(node);
1470 optimize_conv_store(node);
1471 optimize_conv_conv(node);
1475 * Performs conv and address mode optimization.
1477 void ia32_optimize_graph(ir_graph *irg)
1479 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1482 void ia32_init_optimize(void)
1484 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");