3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universität Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
28 #include "../benode_t.h"
29 #include "../besched_t.h"
31 #include "ia32_new_nodes.h"
32 #include "bearch_ia32_t.h"
33 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "ia32_transform.h"
35 #include "ia32_dbg_stat.h"
36 #include "ia32_util.h"
39 IA32_AM_CAND_NONE = 0,
40 IA32_AM_CAND_LEFT = 1,
41 IA32_AM_CAND_RIGHT = 2,
46 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
48 typedef int is_op_func_t(const ir_node *n);
49 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
52 * checks if a node represents the NOREG value
54 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
55 be_abi_irg_t *babi = cg->birg->abi;
56 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
57 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
59 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
60 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
65 /*************************************************
68 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
69 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
70 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
71 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
73 *************************************************/
76 * creates a unique ident by adding a number to a tag
78 * @param tag the tag string, must contain a %d if a number
81 static ident *unique_id(const char *tag)
83 static unsigned id = 0;
86 snprintf(str, sizeof(str), tag, ++id);
87 return new_id_from_str(str);
91 * Transforms a SymConst.
93 * @param mod the debug module
94 * @param block the block the new node should belong to
95 * @param node the ir SymConst node
96 * @param mode mode of the SymConst
97 * @return the created ia32 Const node
99 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
100 dbg_info *dbg = env->dbg;
101 ir_mode *mode = env->mode;
102 ir_graph *irg = env->irg;
103 ir_node *block = env->block;
106 if (mode_is_float(mode)) {
108 if (USE_SSE2(env->cg))
109 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
111 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
114 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
116 set_ia32_Const_attr(cnst, env->irn);
122 * Get a primitive type for a mode.
124 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
126 pmap_entry *e = pmap_find(types, mode);
131 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
132 res = new_type_primitive(new_id_from_str(buf), mode);
133 pmap_insert(types, mode, res);
141 * Get an entity that is initialized with a tarval
143 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
145 tarval *tv = get_Const_tarval(cnst);
146 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
151 ir_mode *mode = get_irn_mode(cnst);
152 ir_type *tp = get_Const_type(cnst);
153 if (tp == firm_unknown_type)
154 tp = get_prim_type(cg->isa->types, mode);
156 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
158 set_entity_ld_ident(res, get_entity_ident(res));
159 set_entity_visibility(res, visibility_local);
160 set_entity_variability(res, variability_constant);
161 set_entity_allocation(res, allocation_static);
163 /* we create a new entity here: It's initialization must resist on the
165 rem = current_ir_graph;
166 current_ir_graph = get_const_code_irg();
167 set_atomic_ent_value(res, new_Const_type(tv, tp));
168 current_ir_graph = rem;
170 pmap_insert(cg->isa->tv_ent, tv, res);
178 * Transforms a Const.
180 * @param mod the debug module
181 * @param block the block the new node should belong to
182 * @param node the ir Const node
183 * @param mode mode of the Const
184 * @return the created ia32 Const node
186 static ir_node *gen_Const(ia32_transform_env_t *env) {
187 ir_node *cnst, *load;
189 ir_graph *irg = env->irg;
190 ir_node *block = env->block;
191 ir_node *node = env->irn;
192 dbg_info *dbg = env->dbg;
193 ir_mode *mode = env->mode;
195 if (mode_is_float(mode)) {
197 if (! USE_SSE2(env->cg)) {
198 cnst_classify_t clss = classify_Const(node);
200 if (clss == CNST_NULL)
201 return new_rd_ia32_vfldz(dbg, irg, block, mode);
202 else if (clss == CNST_ONE)
203 return new_rd_ia32_vfld1(dbg, irg, block, mode);
205 sym.entity_p = get_entity_for_tv(env->cg, node);
208 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
209 load = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode);
210 load = new_r_Proj(irg, block, load, mode, pn_Load_res);
213 cnst = gen_SymConst(env);
214 set_Load_ptr(get_Proj_pred(load), cnst);
218 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
219 set_ia32_Const_attr(cnst, node);
225 * Transforms (all) Const's into ia32_Const and places them in the
226 * block where they are used (or in the cfg-pred Block in case of Phi's).
227 * Additionally all reference nodes are changed into mode_Is nodes.
228 * NOTE: irn must be a firm constant!
230 static void ia32_transform_const(ir_node *irn, void *env) {
231 ia32_code_gen_t *cg = env;
232 ir_node *cnst = NULL;
233 ia32_transform_env_t tenv;
237 tenv.mode = get_irn_mode(irn);
238 tenv.dbg = get_irn_dbg_info(irn);
240 DEBUG_ONLY(tenv.mod = cg->mod;)
242 /* place const either in the smallest dominator of all its users or the original block */
243 if (cg->opt & IA32_OPT_PLACECNST)
244 tenv.block = node_users_smallest_common_dominator(irn, 1);
246 tenv.block = get_nodes_block(irn);
248 switch (get_irn_opcode(irn)) {
250 cnst = gen_Const(&tenv);
253 cnst = gen_SymConst(&tenv);
256 assert(0 && "Wrong usage of ia32_transform_const!");
259 assert(cnst && "Could not create ia32 Const");
261 /* set the new ia32 const */
266 * Transform all firm consts and assure, we visit each const only once.
268 static void ia32_place_consts_walker(ir_node *irn, void *env) {
269 ia32_code_gen_t *cg = env;
271 if(!is_Const(irn) && !is_SymConst(irn))
274 ia32_transform_const(irn, cg);
278 * Replace reference modes with mode_Iu and preserve store value modes.
280 static void ia32_set_modes(ir_node *irn, void *env) {
284 /* transform all reference nodes into mode_Iu nodes */
285 if (mode_is_reference(get_irn_mode(irn))) {
286 set_irn_mode(irn, mode_Iu);
291 * Walks over the graph, transforms all firm consts into ia32 consts
292 * and places them into the "best" block.
293 * @param cg The ia32 codegenerator object
295 static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
296 irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, cg);
299 /* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
300 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
302 We need to transform the consts twice:
303 - the psi condition tree transformer needs existing constants to be ia32 constants
304 - the psi condition tree transformer inserts new firm constants which need to be transformed
306 ia32_transform_all_firm_consts(cg);
307 irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
308 ia32_transform_all_firm_consts(cg);
311 /********************************************************************************************************
312 * _____ _ _ ____ _ _ _ _ _
313 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
314 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
315 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
316 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
317 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
320 ********************************************************************************************************/
323 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
326 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
327 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
331 * Checks for potential CJmp/CJmpAM optimization candidates.
333 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
334 ir_node *cand = NULL;
335 ir_node *prev = sched_prev(irn);
337 if (is_Block(prev)) {
338 if (get_Block_n_cfgpreds(prev) == 1)
339 prev = get_Block_cfgpred(prev, 0);
344 /* The predecessor must be a ProjX. */
345 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
346 prev = get_Proj_pred(prev);
348 if (is_op_func(prev))
355 static int is_TestJmp_cand(const ir_node *irn) {
356 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
360 * Checks if two consecutive arguments of cand matches
361 * the two arguments of irn (TestJmp).
363 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
364 ir_node *in1 = get_irn_n(irn, 0);
365 ir_node *in2 = get_irn_n(irn, 1);
366 int i, n = get_irn_arity(cand);
369 for (i = 0; i < n - 1; i++) {
370 if (get_irn_n(cand, i) == in1 &&
371 get_irn_n(cand, i + 1) == in2)
379 return ia32_cnst_compare(cand, irn);
385 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
387 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
388 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
391 /* we found a possible candidate */
392 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
395 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
397 if (is_ia32_And(cand))
398 set_irn_op(irn, op_ia32_CJmpAM);
400 set_irn_op(irn, op_ia32_CJmp);
402 DB((cg->mod, LEVEL_1, "%+F\n", irn));
406 static int is_CondJmp_cand(const ir_node *irn) {
407 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
411 * Checks if the arguments of cand are the same of irn.
413 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
414 int i, n = get_irn_arity(cand);
417 for (i = 0; i < n; i++) {
418 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
425 return ia32_cnst_compare(cand, irn);
431 * Tries to replace a CondJmp by a CJmpAM
433 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
434 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
437 /* we found a possible candidate */
438 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
441 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
444 set_irn_op(irn, op_ia32_CJmpAM);
446 DB((cg->mod, LEVEL_1, "%+F\n", irn));
450 // only optimize up to 48 stores behind IncSPs
451 #define MAXPUSH_OPTIMIZE 48
454 * Tries to create pushs from IncSP,Store combinations
456 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
460 ir_node *stores[MAXPUSH_OPTIMIZE];
461 ir_node *block = get_nodes_block(irn);
462 ir_graph *irg = cg->irg;
464 ir_mode *spmode = get_irn_mode(irn);
466 memset(stores, 0, sizeof(stores));
468 assert(be_is_IncSP(irn));
470 offset = be_get_IncSP_offset(irn);
475 * We first walk the schedule after the IncSP node as long as we find
476 * suitable stores that could be transformed to a push.
477 * We save them into the stores array which is sorted by the frame offset/4
478 * attached to the node
480 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
487 // it has to be a store
488 if(!is_ia32_Store(node))
491 // it has to use our sp value
492 if(get_irn_n(node, 0) != irn)
494 // store has to be attached to NoMem
495 mem = get_irn_n(node, 3);
500 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
503 am_offs = get_ia32_am_offs(node);
504 if(am_offs == NULL) {
507 // the am_offs has to be of the form "+NUMBER"
508 if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') {
509 // we shouldn't have any cases in the compiler at the moment
510 // that produce something different from esp+XX
516 storeslot = offset / 4;
517 if(storeslot >= MAXPUSH_OPTIMIZE)
520 // storing into the same slot twice is bad (and shouldn't happen...)
521 if(stores[storeslot] != NULL)
524 // storing at half-slots is bad
528 stores[storeslot] = node;
531 curr_sp = get_irn_n(irn, 0);
533 // walk the stores in inverse order and create pushs for them
534 i = (offset / 4) - 1;
535 if(i >= MAXPUSH_OPTIMIZE) {
536 i = MAXPUSH_OPTIMIZE - 1;
539 for( ; i >= 0; --i) {
540 const ir_edge_t *edge, *next;
541 const arch_register_t *spreg;
544 ir_node *store = stores[i];
546 if(store == NULL || is_Bad(store))
549 val = get_irn_n(store, 2);
550 mem = get_irn_n(store, 3);
551 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
554 push = new_rd_ia32_Push(NULL, irg, block, curr_sp, val, mem);
555 if(get_ia32_immop_type(store) != ia32_ImmNone) {
556 copy_ia32_Immop_attr(push, store);
558 sched_add_before(irn, push);
560 // create stackpointer proj
561 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
562 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
563 sched_add_before(irn, curr_sp);
565 // rewire memprojs of the store
566 foreach_out_edge_safe(store, edge, next) {
567 ir_node *succ = get_edge_src_irn(edge);
569 assert(is_Proj(succ) && get_Proj_proj(succ) == pn_ia32_Store_M);
570 set_irn_n(succ, 0, push);
573 // we can remove the store now
574 set_irn_n(store, 0, new_Bad());
575 set_irn_n(store, 1, new_Bad());
576 set_irn_n(store, 2, new_Bad());
577 set_irn_n(store, 3, new_Bad());
583 be_set_IncSP_offset(irn, offset);
585 // can we remove the IncSP now?
587 const ir_edge_t *edge, *next;
589 foreach_out_edge_safe(irn, edge, next) {
590 ir_node *arg = get_edge_src_irn(edge);
591 int pos = get_edge_src_pos(edge);
593 set_irn_n(arg, pos, curr_sp);
596 set_irn_n(irn, 0, new_Bad());
599 set_irn_n(irn, 0, curr_sp);
604 * Tries to optimize two following IncSP.
606 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
607 ir_node *prev = be_get_IncSP_pred(irn);
608 int real_uses = get_irn_n_edges(prev);
610 if (be_is_IncSP(prev) && real_uses == 1) {
611 /* first IncSP has only one IncSP user, kill the first one */
612 int prev_offs = be_get_IncSP_offset(prev);
613 int curr_offs = be_get_IncSP_offset(irn);
615 be_set_IncSP_offset(prev, prev_offs + curr_offs);
617 /* Omit the optimized IncSP */
618 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
620 set_irn_n(prev, 0, new_Bad());
626 * Performs Peephole Optimizations.
628 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
629 ia32_code_gen_t *cg = env;
631 /* AMD CPUs want explicit compare before conditional jump */
632 if (! ARCH_AMD(cg->opt_arch)) {
633 if (is_ia32_TestJmp(irn))
634 ia32_optimize_TestJmp(irn, cg);
635 else if (is_ia32_CondJmp(irn))
636 ia32_optimize_CondJmp(irn, cg);
639 if (be_is_IncSP(irn)) {
640 // optimize_IncSP doesn't respect dependency edges yet...
641 //ia32_optimize_IncSP(irn, cg);
642 (void) ia32_optimize_IncSP;
643 ia32_create_Pushs(irn, cg);
647 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
648 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
651 /******************************************************************
653 * /\ | | | | | \/ | | |
654 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
655 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
656 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
657 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
659 ******************************************************************/
666 static int node_is_ia32_comm(const ir_node *irn) {
667 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
670 static int ia32_get_irn_n_edges(const ir_node *irn) {
671 const ir_edge_t *edge;
674 foreach_out_edge(irn, edge) {
682 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
684 * @param pred The node to be checked
685 * @param is_op_func The check-function
686 * @return 1 if conditions are fulfilled, 0 otherwise
688 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
689 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
697 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
698 * and if the predecessor is in block bl.
700 * @param bl The block
701 * @param pred The node to be checked
702 * @param is_op_func The check-function
703 * @return 1 if conditions are fulfilled, 0 otherwise
705 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
706 int (*is_op_func)(const ir_node *n))
709 pred = get_Proj_pred(pred);
710 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
719 * Checks if irn is a candidate for address calculation.
721 * - none of the operand must be a Load within the same block OR
722 * - all Loads must have more than one user OR
723 * - the irn has a frame entity (it's a former FrameAddr)
725 * @param block The block the Loads must/mustnot be in
726 * @param irn The irn to check
727 * return 1 if irn is a candidate, 0 otherwise
729 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
730 ir_node *in, *left, *right;
733 left = get_irn_n(irn, 2);
734 right = get_irn_n(irn, 3);
738 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
739 n = ia32_get_irn_n_edges(in);
740 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
745 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
746 n = ia32_get_irn_n_edges(in);
747 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
750 is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
756 * Checks if irn is a candidate for address mode.
759 * - at least one operand has to be a Load within the same block AND
760 * - the load must not have other users than the irn AND
761 * - the irn must not have a frame entity set
763 * @param cg The ia32 code generator
764 * @param h The height information of the irg
765 * @param block The block the Loads must/mustnot be in
766 * @param irn The irn to check
767 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
769 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
770 ir_node *in, *load, *other, *left, *right;
771 int n, is_cand = 0, cand;
773 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
774 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
777 left = get_irn_n(irn, 2);
778 right = get_irn_n(irn, 3);
782 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
783 n = ia32_get_irn_n_edges(in);
784 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
786 load = get_Proj_pred(in);
789 /* 8bit Loads are not supported, they cannot be used with every register */
790 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
793 /* If there is a data dependency of other irn from load: cannot use AM */
794 if (is_cand && get_nodes_block(other) == block) {
795 other = skip_Proj(other);
796 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
797 /* this could happen in loops */
798 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
802 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
806 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
807 n = ia32_get_irn_n_edges(in);
808 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
810 load = get_Proj_pred(in);
813 /* 8bit Loads are not supported, they cannot be used with every register */
814 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
817 /* If there is a data dependency of other irn from load: cannot use load */
818 if (is_cand && get_nodes_block(other) == block) {
819 other = skip_Proj(other);
820 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
821 /* this could happen in loops */
822 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
826 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
828 /* check some special cases */
829 if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
830 /* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
831 if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32)
832 cand = IA32_AM_CAND_NONE;
834 else if (is_ia32_Conv_I2I(irn)) {
835 /* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
836 if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn)))
837 cand = IA32_AM_CAND_NONE;
840 /* if the irn has a frame entity: we do not use address mode */
841 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
845 * Compares the base and index addr and the load/store entities
846 * and returns 1 if they are equal.
848 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
849 const ir_node *addr_b, const ir_node *addr_i)
851 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
852 entity *lent = get_ia32_frame_ent(load);
853 entity *sent = get_ia32_frame_ent(store);
854 ident *lid = get_ia32_am_sc(load);
855 ident *sid = get_ia32_am_sc(store);
856 char *loffs = get_ia32_am_offs(load);
857 char *soffs = get_ia32_am_offs(store);
859 /* are both entities set and equal? */
860 if (is_equal && (lent || sent))
861 is_equal = lent && sent && (lent == sent);
863 /* are address mode idents set and equal? */
864 if (is_equal && (lid || sid))
865 is_equal = lid && sid && (lid == sid);
867 /* are offsets set and equal */
868 if (is_equal && (loffs || soffs))
869 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
871 /* are the load and the store of the same mode? */
872 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
877 typedef enum _ia32_take_lea_attr {
878 IA32_LEA_ATTR_NONE = 0,
879 IA32_LEA_ATTR_BASE = (1 << 0),
880 IA32_LEA_ATTR_INDEX = (1 << 1),
881 IA32_LEA_ATTR_OFFS = (1 << 2),
882 IA32_LEA_ATTR_SCALE = (1 << 3),
883 IA32_LEA_ATTR_AMSC = (1 << 4),
884 IA32_LEA_ATTR_FENT = (1 << 5)
885 } ia32_take_lea_attr;
888 * Decides if we have to keep the LEA operand or if we can assimilate it.
890 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
891 int have_am_sc, ia32_code_gen_t *cg)
893 entity *irn_ent = get_ia32_frame_ent(irn);
894 entity *lea_ent = get_ia32_frame_ent(lea);
896 int is_noreg_base = be_is_NoReg(cg, base);
897 int is_noreg_index = be_is_NoReg(cg, index);
898 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
900 /* If the Add and the LEA both have a different frame entity set: keep */
901 if (irn_ent && lea_ent && (irn_ent != lea_ent))
902 return IA32_LEA_ATTR_NONE;
903 else if (! irn_ent && lea_ent)
904 ret_val |= IA32_LEA_ATTR_FENT;
906 /* If the Add and the LEA both have already an address mode symconst: keep */
907 if (have_am_sc && get_ia32_am_sc(lea))
908 return IA32_LEA_ATTR_NONE;
909 else if (get_ia32_am_sc(lea))
910 ret_val |= IA32_LEA_ATTR_AMSC;
912 /* Check the different base-index combinations */
914 if (! is_noreg_base && ! is_noreg_index) {
915 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
916 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
917 if (am_flav & ia32_O)
918 ret_val |= IA32_LEA_ATTR_OFFS;
920 ret_val |= IA32_LEA_ATTR_BASE;
923 return IA32_LEA_ATTR_NONE;
925 else if (! is_noreg_base && is_noreg_index) {
926 /* Base is set but index not */
928 /* Base points to LEA: assimilate everything */
929 if (am_flav & ia32_O)
930 ret_val |= IA32_LEA_ATTR_OFFS;
931 if (am_flav & ia32_S)
932 ret_val |= IA32_LEA_ATTR_SCALE;
933 if (am_flav & ia32_I)
934 ret_val |= IA32_LEA_ATTR_INDEX;
936 ret_val |= IA32_LEA_ATTR_BASE;
938 else if (am_flav & ia32_B ? 0 : 1) {
939 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
940 if (am_flav & ia32_O)
941 ret_val |= IA32_LEA_ATTR_OFFS;
942 if (am_flav & ia32_S)
943 ret_val |= IA32_LEA_ATTR_SCALE;
945 ret_val |= IA32_LEA_ATTR_INDEX;
948 return IA32_LEA_ATTR_NONE;
950 else if (is_noreg_base && ! is_noreg_index) {
951 /* Index is set but not base */
953 /* Index points to LEA: assimilate everything */
954 if (am_flav & ia32_O)
955 ret_val |= IA32_LEA_ATTR_OFFS;
956 if (am_flav & ia32_S)
957 ret_val |= IA32_LEA_ATTR_SCALE;
958 if (am_flav & ia32_B)
959 ret_val |= IA32_LEA_ATTR_BASE;
961 ret_val |= IA32_LEA_ATTR_INDEX;
963 else if (am_flav & ia32_I ? 0 : 1) {
964 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
965 if (am_flav & ia32_O)
966 ret_val |= IA32_LEA_ATTR_OFFS;
967 if (am_flav & ia32_S)
968 ret_val |= IA32_LEA_ATTR_SCALE;
970 ret_val |= IA32_LEA_ATTR_BASE;
973 return IA32_LEA_ATTR_NONE;
976 assert(0 && "There must have been set base or index");
983 * Adds res before irn into schedule if irn was scheduled.
984 * @param irn The schedule point
985 * @param res The node to be scheduled
987 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
988 if (sched_is_scheduled(irn))
989 sched_add_before(irn, res);
993 * Removes irn from schedule if it was scheduled. If irn is a mode_T node
994 * all it's Projs are removed as well.
995 * @param irn The irn to be removed from schedule
997 static INLINE void try_remove_from_sched(ir_node *irn) {
1000 if (sched_is_scheduled(irn)) {
1001 if (get_irn_mode(irn) == mode_T) {
1002 const ir_edge_t *edge;
1003 foreach_out_edge(irn, edge) {
1004 ir_node *proj = get_edge_src_irn(edge);
1005 if (sched_is_scheduled(proj)) {
1006 set_irn_n(proj, 0, new_Bad());
1012 arity = get_irn_arity(irn);
1013 for(i = 0; i < arity; ++i) {
1014 set_irn_n(irn, i, new_Bad());
1021 * Folds Add or Sub to LEA if possible
1023 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
1024 ir_graph *irg = get_irn_irg(irn);
1025 dbg_info *dbg = get_irn_dbg_info(irn);
1026 ir_node *block = get_nodes_block(irn);
1028 ir_node *shift = NULL;
1029 ir_node *lea_o = NULL;
1030 ir_node *lea = NULL;
1032 const char *offs_cnst = NULL;
1033 char *offs_lea = NULL;
1039 ident *am_sc = NULL;
1040 entity *lea_ent = NULL;
1041 ir_node *left, *right, *temp;
1042 ir_node *base, *index;
1043 int consumed_left_shift;
1044 ia32_am_flavour_t am_flav;
1045 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1047 if (is_ia32_Add(irn))
1050 left = get_irn_n(irn, 2);
1051 right = get_irn_n(irn, 3);
1053 /* "normalize" arguments in case of add with two operands */
1054 if (isadd && ! be_is_NoReg(cg, right)) {
1055 /* put LEA == ia32_am_O as right operand */
1056 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
1057 set_irn_n(irn, 2, right);
1058 set_irn_n(irn, 3, left);
1064 /* put LEA != ia32_am_O as left operand */
1065 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
1066 set_irn_n(irn, 2, right);
1067 set_irn_n(irn, 3, left);
1073 /* put SHL as left operand iff left is NOT a LEA */
1074 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
1075 set_irn_n(irn, 2, right);
1076 set_irn_n(irn, 3, left);
1089 /* check for operation with immediate */
1090 if (is_ia32_ImmConst(irn)) {
1091 DBG((mod, LEVEL_1, "\tfound op with imm const"));
1093 offs_cnst = get_ia32_cnst(irn);
1096 else if (is_ia32_ImmSymConst(irn)) {
1097 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
1101 am_sc = get_ia32_id_cnst(irn);
1102 am_sc_sign = is_ia32_am_sc_sign(irn);
1105 /* determine the operand which needs to be checked */
1106 temp = be_is_NoReg(cg, right) ? left : right;
1108 /* check if right operand is AMConst (LEA with ia32_am_O) */
1109 /* but we can only eat it up if there is no other symconst */
1110 /* because the linker won't accept two symconsts */
1111 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
1112 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
1114 offs_lea = get_ia32_am_offs(temp);
1115 am_sc = get_ia32_am_sc(temp);
1116 am_sc_sign = is_ia32_am_sc_sign(temp);
1123 else if (temp == right)
1128 /* default for add -> make right operand to index */
1131 consumed_left_shift = -1;
1133 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
1135 /* determine the operand which needs to be checked */
1137 if (is_ia32_Lea(left)) {
1139 consumed_left_shift = 0;
1142 /* check for SHL 1,2,3 */
1143 if (pred_is_specific_node(temp, is_ia32_Shl)) {
1144 temp = get_Proj_pred(temp);
1147 if (get_ia32_Immop_tarval(temp)) {
1148 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
1151 index = get_irn_n(temp, 2);
1152 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
1154 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
1164 if (! be_is_NoReg(cg, index)) {
1165 /* if we have index, but left == right -> no base */
1166 if (left == right) {
1169 else if (consumed_left_shift == 1) {
1170 /* -> base is right operand */
1171 base = (right == lea_o) ? noreg : right;
1176 /* Try to assimilate a LEA as left operand */
1177 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1178 /* check if we can assimilate the LEA */
1179 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1181 if (take_attr == IA32_LEA_ATTR_NONE) {
1182 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1185 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1186 lea = left; /* for statistics */
1188 if (take_attr & IA32_LEA_ATTR_OFFS)
1189 offs = get_ia32_am_offs(left);
1191 if (take_attr & IA32_LEA_ATTR_AMSC) {
1192 am_sc = get_ia32_am_sc(left);
1194 am_sc_sign = is_ia32_am_sc_sign(left);
1197 if (take_attr & IA32_LEA_ATTR_SCALE)
1198 scale = get_ia32_am_scale(left);
1200 if (take_attr & IA32_LEA_ATTR_BASE)
1201 base = get_irn_n(left, 0);
1203 if (take_attr & IA32_LEA_ATTR_INDEX)
1204 index = get_irn_n(left, 1);
1206 if (take_attr & IA32_LEA_ATTR_FENT)
1207 lea_ent = get_ia32_frame_ent(left);
1211 /* ok, we can create a new LEA */
1213 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1215 /* add the old offset of a previous LEA */
1217 add_ia32_am_offs(res, offs);
1220 /* add the new offset */
1223 add_ia32_am_offs(res, offs_cnst);
1226 add_ia32_am_offs(res, offs_lea);
1230 /* either lea_O-cnst, -cnst or -lea_O */
1233 add_ia32_am_offs(res, offs_lea);
1236 sub_ia32_am_offs(res, offs_cnst);
1239 sub_ia32_am_offs(res, offs_lea);
1243 /* set the address mode symconst */
1245 set_ia32_am_sc(res, am_sc);
1247 set_ia32_am_sc_sign(res);
1250 /* copy the frame entity (could be set in case of Add */
1251 /* which was a FrameAddr) */
1253 set_ia32_frame_ent(res, lea_ent);
1255 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1257 if (get_ia32_frame_ent(res))
1258 set_ia32_use_frame(res);
1261 set_ia32_am_scale(res, scale);
1263 am_flav = ia32_am_N;
1264 /* determine new am flavour */
1265 if (offs || offs_cnst || offs_lea || have_am_sc) {
1268 if (! be_is_NoReg(cg, base)) {
1271 if (! be_is_NoReg(cg, index)) {
1277 set_ia32_am_flavour(res, am_flav);
1279 set_ia32_op_type(res, ia32_AddrModeS);
1281 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1283 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1285 /* we will exchange it, report here before the Proj is created */
1286 if (shift && lea && lea_o) {
1287 try_remove_from_sched(shift);
1288 try_remove_from_sched(lea);
1289 try_remove_from_sched(lea_o);
1290 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1292 else if (shift && lea) {
1293 try_remove_from_sched(shift);
1294 try_remove_from_sched(lea);
1295 DBG_OPT_LEA3(irn, lea, shift, res);
1297 else if (shift && lea_o) {
1298 try_remove_from_sched(shift);
1299 try_remove_from_sched(lea_o);
1300 DBG_OPT_LEA3(irn, lea_o, shift, res);
1302 else if (lea && lea_o) {
1303 try_remove_from_sched(lea);
1304 try_remove_from_sched(lea_o);
1305 DBG_OPT_LEA3(irn, lea_o, lea, res);
1308 try_remove_from_sched(shift);
1309 DBG_OPT_LEA2(irn, shift, res);
1312 try_remove_from_sched(lea);
1313 DBG_OPT_LEA2(irn, lea, res);
1316 try_remove_from_sched(lea_o);
1317 DBG_OPT_LEA2(irn, lea_o, res);
1320 DBG_OPT_LEA1(irn, res);
1322 /* get the result Proj of the Add/Sub */
1323 try_add_to_sched(irn, res);
1324 try_remove_from_sched(irn);
1325 irn = ia32_get_res_proj(irn);
1327 assert(irn && "Couldn't find result proj");
1329 /* exchange the old op with the new LEA */
1338 * Merges a Load/Store node with a LEA.
1339 * @param irn The Load/Store node
1340 * @param lea The LEA
1342 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1343 entity *irn_ent = get_ia32_frame_ent(irn);
1344 entity *lea_ent = get_ia32_frame_ent(lea);
1346 /* If the irn and the LEA both have a different frame entity set: do not merge */
1347 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1349 else if (! irn_ent && lea_ent) {
1350 set_ia32_frame_ent(irn, lea_ent);
1351 set_ia32_use_frame(irn);
1354 /* get the AM attributes from the LEA */
1355 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1356 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1357 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1359 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1360 if (is_ia32_am_sc_sign(lea))
1361 set_ia32_am_sc_sign(irn);
1363 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1365 /* set base and index */
1366 set_irn_n(irn, 0, get_irn_n(lea, 0));
1367 set_irn_n(irn, 1, get_irn_n(lea, 1));
1369 try_remove_from_sched(lea);
1371 /* clear remat flag */
1372 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1374 if (is_ia32_Ld(irn))
1375 DBG_OPT_LOAD_LEA(lea, irn);
1377 DBG_OPT_STORE_LEA(lea, irn);
1382 * Sets new_right index of irn to right and new_left index to left.
1383 * Also exchange left and right
1385 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1388 set_irn_n(irn, new_right, *right);
1389 set_irn_n(irn, new_left, *left);
1395 /* this is only needed for Compares, but currently ALL nodes
1396 * have this attribute :-) */
1397 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1401 * Performs address calculation optimization (create LEAs if possible)
1403 static void optimize_lea(ir_node *irn, void *env) {
1404 ia32_code_gen_t *cg = env;
1405 ir_node *block, *noreg_gp, *left, *right;
1407 if (! is_ia32_irn(irn))
1410 /* Following cases can occur: */
1411 /* - Sub (l, imm) -> LEA [base - offset] */
1412 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1413 /* - Add (l, imm) -> LEA [base + offset] */
1414 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1415 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1416 /* - Add (l, r) -> LEA [base + index * scale] */
1417 /* with scale > 1 iff l/r == shl (1,2,3) */
1419 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1420 left = get_irn_n(irn, 2);
1421 right = get_irn_n(irn, 3);
1422 block = get_nodes_block(irn);
1423 noreg_gp = ia32_new_NoReg_gp(cg);
1425 /* Do not try to create a LEA if one of the operands is a Load. */
1426 /* check is irn is a candidate for address calculation */
1427 if (is_addr_candidate(block, irn)) {
1430 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1431 res = fold_addr(cg, irn, noreg_gp);
1434 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1436 DB((cg->mod, LEVEL_1, "not transformed\n"));
1439 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1440 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1441 /* - Store -> LEA into Store } it might be better to keep the LEA */
1442 left = get_irn_n(irn, 0);
1444 if (is_ia32_Lea(left)) {
1445 const ir_edge_t *edge, *ne;
1448 /* merge all Loads/Stores connected to this LEA with the LEA */
1449 foreach_out_edge_safe(left, edge, ne) {
1450 src = get_edge_src_irn(edge);
1452 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1453 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1454 if (! is_ia32_got_lea(src))
1455 merge_loadstore_lea(src, left);
1456 set_ia32_got_lea(src);
1465 * Checks for address mode patterns and performs the
1466 * necessary transformations.
1467 * This function is called by a walker.
1469 static void optimize_am(ir_node *irn, void *env) {
1470 ia32_am_opt_env_t *am_opt_env = env;
1471 ia32_code_gen_t *cg = am_opt_env->cg;
1472 heights_t *h = am_opt_env->h;
1473 ir_node *block, *noreg_gp, *noreg_fp;
1474 ir_node *left, *right;
1475 ir_node *store, *load, *mem_proj;
1476 ir_node *succ, *addr_b, *addr_i;
1477 int check_am_src = 0;
1478 int need_exchange_on_fail = 0;
1479 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1481 if (! is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1484 block = get_nodes_block(irn);
1485 noreg_gp = ia32_new_NoReg_gp(cg);
1486 noreg_fp = ia32_new_NoReg_fp(cg);
1488 DBG((mod, LEVEL_1, "checking for AM\n"));
1490 /* fold following patterns: */
1491 /* - op -> Load into AMop with am_Source */
1493 /* - op is am_Source capable AND */
1494 /* - the Load is only used by this op AND */
1495 /* - the Load is in the same block */
1496 /* - Store -> op -> Load into AMop with am_Dest */
1498 /* - op is am_Dest capable AND */
1499 /* - the Store uses the same address as the Load AND */
1500 /* - the Load is only used by this op AND */
1501 /* - the Load and Store are in the same block AND */
1502 /* - nobody else uses the result of the op */
1504 if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) {
1505 ia32_am_cand_t cand = is_am_candidate(cg, h, block, irn);
1506 ia32_am_cand_t orig_cand = cand;
1508 /* cand == 1: load is left; cand == 2: load is right; */
1510 if (cand == IA32_AM_CAND_NONE)
1513 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1515 left = get_irn_n(irn, 2);
1516 if (get_irn_arity(irn) == 4) {
1517 /* it's an "unary" operation */
1521 right = get_irn_n(irn, 3);
1524 /* normalize commutative ops */
1525 if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) {
1527 /* Assure that left operand is always a Load if there is one */
1528 /* because non-commutative ops can only use Dest AM if the left */
1529 /* operand is a load, so we only need to check left operand. */
1531 exchange_left_right(irn, &left, &right, 3, 2);
1532 need_exchange_on_fail = 1;
1534 /* now: load is right */
1535 cand = IA32_AM_CAND_LEFT;
1538 /* check for Store -> op -> Load */
1540 /* Store -> op -> Load optimization is only possible if supported by op */
1541 /* and if right operand is a Load */
1542 if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_LEFT))
1544 /* An address mode capable op always has a result Proj. */
1545 /* If this Proj is used by more than one other node, we don't need to */
1546 /* check further, otherwise we check for Store and remember the address, */
1547 /* the Store points to. */
1549 succ = ia32_get_res_proj(irn);
1550 assert(succ && "Couldn't find result proj");
1556 /* now check for users and Store */
1557 if (ia32_get_irn_n_edges(succ) == 1) {
1558 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1560 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1562 addr_b = get_irn_n(store, 0);
1563 addr_i = get_irn_n(store, 1);
1568 /* we found a Store as single user: Now check for Load */
1570 /* skip the Proj for easier access */
1571 load = is_Proj(right) ? (is_ia32_Load(get_Proj_pred(right)) ? get_Proj_pred(right) : NULL) : NULL;
1573 /* Extra check for commutative ops with two Loads */
1574 /* -> put the interesting Load left */
1575 if (load && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) {
1576 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1577 /* We exchange left and right, so it's easier to kill */
1578 /* the correct Load later and to handle unary operations. */
1579 exchange_left_right(irn, &left, &right, 3, 2);
1580 need_exchange_on_fail ^= 1;
1584 /* skip the Proj for easier access */
1585 load = get_Proj_pred(left);
1587 /* Compare Load and Store address */
1588 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1589 /* Left Load is from same address, so we can */
1590 /* disconnect the Load and Store here */
1592 /* set new base, index and attributes */
1593 set_irn_n(irn, 0, addr_b);
1594 set_irn_n(irn, 1, addr_i);
1595 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1596 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1597 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1598 set_ia32_op_type(irn, ia32_AddrModeD);
1599 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1600 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1602 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1603 if (is_ia32_am_sc_sign(load))
1604 set_ia32_am_sc_sign(irn);
1606 if (is_ia32_use_frame(load))
1607 set_ia32_use_frame(irn);
1609 /* connect to Load memory and disconnect Load */
1610 if (get_irn_arity(irn) == 5) {
1612 set_irn_n(irn, 4, get_irn_n(load, 2));
1613 set_irn_n(irn, 2, noreg_gp);
1617 set_irn_n(irn, 3, get_irn_n(load, 2));
1618 set_irn_n(irn, 2, noreg_gp);
1621 /* connect the memory Proj of the Store to the op */
1622 mem_proj = ia32_get_proj_for_mode(store, mode_M);
1623 set_Proj_pred(mem_proj, irn);
1624 set_Proj_proj(mem_proj, 1);
1626 /* clear remat flag */
1627 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1629 try_remove_from_sched(load);
1630 try_remove_from_sched(store);
1631 DBG_OPT_AM_D(load, store, irn);
1633 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1635 need_exchange_on_fail = 0;
1638 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1639 /* There was no store, check if we still can optimize for source address mode */
1642 } /* if (support AM Dest) */
1643 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1644 /* op doesn't support am AM Dest -> check for AM Source */
1648 /* was exchanged but optimize failed: exchange back */
1649 if (need_exchange_on_fail) {
1650 exchange_left_right(irn, &left, &right, 3, 2);
1654 need_exchange_on_fail = 0;
1656 /* normalize commutative ops */
1657 if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) {
1659 /* Assure that right operand is always a Load if there is one */
1660 /* because non-commutative ops can only use Source AM if the */
1661 /* right operand is a Load, so we only need to check the right */
1662 /* operand afterwards. */
1664 exchange_left_right(irn, &left, &right, 3, 2);
1665 need_exchange_on_fail = 1;
1667 /* now: load is left */
1668 cand = IA32_AM_CAND_RIGHT;
1671 /* optimize op -> Load iff Load is only used by this op */
1672 /* and right operand is a Load which only used by this irn */
1674 (cand & IA32_AM_CAND_RIGHT) &&
1675 (get_irn_arity(irn) == 5) &&
1676 (ia32_get_irn_n_edges(right) == 1))
1678 right = get_Proj_pred(right);
1680 addr_b = get_irn_n(right, 0);
1681 addr_i = get_irn_n(right, 1);
1683 /* set new base, index and attributes */
1684 set_irn_n(irn, 0, addr_b);
1685 set_irn_n(irn, 1, addr_i);
1686 add_ia32_am_offs(irn, get_ia32_am_offs(right));
1687 set_ia32_am_scale(irn, get_ia32_am_scale(right));
1688 set_ia32_am_flavour(irn, get_ia32_am_flavour(right));
1689 set_ia32_op_type(irn, ia32_AddrModeS);
1690 set_ia32_frame_ent(irn, get_ia32_frame_ent(right));
1691 set_ia32_ls_mode(irn, get_ia32_ls_mode(right));
1693 set_ia32_am_sc(irn, get_ia32_am_sc(right));
1694 if (is_ia32_am_sc_sign(right))
1695 set_ia32_am_sc_sign(irn);
1697 /* clear remat flag */
1698 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1700 if (is_ia32_use_frame(right))
1701 set_ia32_use_frame(irn);
1703 /* connect to Load memory */
1704 set_irn_n(irn, 4, get_irn_n(right, 2));
1706 /* this is only needed for Compares, but currently ALL nodes
1707 * have this attribute :-) */
1708 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1710 /* disconnect from Load */
1711 set_irn_n(irn, 3, noreg_gp);
1713 DBG_OPT_AM_S(right, irn);
1715 /* If Load has a memory Proj, connect it to the op */
1716 mem_proj = ia32_get_proj_for_mode(right, mode_M);
1718 set_Proj_pred(mem_proj, irn);
1719 set_Proj_proj(mem_proj, 1);
1722 try_remove_from_sched(right);
1724 DB((mod, LEVEL_1, "merged with %+F into source AM\n", right));
1727 /* was exchanged but optimize failed: exchange back */
1728 if (need_exchange_on_fail)
1729 exchange_left_right(irn, &left, &right, 3, 2);
1735 * Performs address mode optimization.
1737 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1738 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1739 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1740 edges_deactivate(cg->irg);
1741 edges_activate(cg->irg);
1744 /* no optimizations at all */
1748 /* beware: we cannot optimize LEA and AM in one run because */
1749 /* LEA optimization adds new nodes to the irg which */
1750 /* invalidates the phase data */
1752 if (cg->opt & IA32_OPT_LEA) {
1753 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1757 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1759 if (cg->opt & IA32_OPT_DOAM) {
1760 /* we need height information for am optimization */
1761 heights_t *h = heights_new(cg->irg);
1762 ia32_am_opt_env_t env;
1767 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);