2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
65 * Returns non-zero if the given node produces
68 * @param node the node to check
69 * @param pn if >= 0, the projection number of the used result
71 static int produces_zero_flag(ir_node *node, int pn)
74 const ia32_immediate_attr_t *imm_attr;
76 if (!is_ia32_irn(node))
80 if (pn != pn_ia32_res)
84 switch (get_ia32_irn_opcode(node)) {
102 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
103 assert(n_ia32_Shl_count == n_ia32_Shr_count
104 && n_ia32_Shl_count == n_ia32_Sar_count);
105 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
106 count = get_irn_n(node, n_ia32_ShlD_count);
108 count = get_irn_n(node, n_ia32_Shl_count);
110 /* when shift count is zero the flags are not affected, so we can only
111 * do this for constants != 0 */
112 if (!is_ia32_Immediate(count))
115 imm_attr = get_ia32_immediate_attr_const(count);
116 if (imm_attr->symconst != NULL)
118 if ((imm_attr->offset & 0x1f) == 0)
129 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
131 * @param node the node to change
133 * @return the new mode_T node (if the mode was changed) or node itself
135 static ir_node *turn_into_mode_t(ir_node *node)
140 const arch_register_t *reg;
142 if(get_irn_mode(node) == mode_T)
145 assert(get_irn_mode(node) == mode_Iu);
147 new_node = exact_copy(node);
148 set_irn_mode(new_node, mode_T);
150 block = get_nodes_block(new_node);
151 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
154 reg = arch_get_irn_register(arch_env, node);
155 arch_set_irn_register(arch_env, res_proj, reg);
157 be_peephole_before_exchange(node, res_proj);
158 sched_add_before(node, new_node);
160 exchange(node, res_proj);
161 be_peephole_after_exchange(res_proj);
167 * Peephole optimization for Test instructions.
168 * We can remove the Test, if a zero flags was produced which is still
171 static void peephole_ia32_Test(ir_node *node)
173 ir_node *left = get_irn_n(node, n_ia32_Test_left);
174 ir_node *right = get_irn_n(node, n_ia32_Test_right);
180 const ir_edge_t *edge;
182 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
183 && n_ia32_Test_right == n_ia32_Test8Bit_right);
185 /* we need a test for 0 */
189 block = get_nodes_block(node);
190 if(get_nodes_block(left) != block)
194 pn = get_Proj_proj(left);
195 left = get_Proj_pred(left);
198 /* happens rarely, but if it does code will panic' */
199 if (is_ia32_Unknown_GP(left))
202 /* walk schedule up and abort when we find left or some other node destroys
204 schedpoint = sched_prev(node);
205 while(schedpoint != left) {
206 schedpoint = sched_prev(schedpoint);
207 if(arch_irn_is(arch_env, schedpoint, modify_flags))
209 if(schedpoint == block)
210 panic("couldn't find left");
213 /* make sure only Lg/Eq tests are used */
214 foreach_out_edge(node, edge) {
215 ir_node *user = get_edge_src_irn(edge);
216 int pnc = get_ia32_condcode(user);
218 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
223 if(!produces_zero_flag(left, pn))
226 left = turn_into_mode_t(left);
228 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
229 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
231 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
233 assert(get_irn_mode(node) != mode_T);
235 be_peephole_before_exchange(node, flags_proj);
236 exchange(node, flags_proj);
238 be_peephole_after_exchange(flags_proj);
242 * AMD Athlon works faster when RET is not destination of
243 * conditional jump or directly preceded by other jump instruction.
244 * Can be avoided by placing a Rep prefix before the return.
246 static void peephole_ia32_Return(ir_node *node) {
247 ir_node *block, *irn;
249 if (!ia32_cg_config.use_pad_return)
252 block = get_nodes_block(node);
254 if (get_Block_n_cfgpreds(block) == 1) {
255 ir_node *pred = get_Block_cfgpred(block, 0);
258 /* The block of the return has only one predecessor,
259 which jumps directly to this block.
260 This jump will be encoded as a fall through, so we
262 However, the predecessor might be empty, so it must be
263 ensured that empty blocks are gone away ... */
268 /* check if this return is the first on the block */
269 sched_foreach_reverse_from(node, irn) {
270 switch (get_irn_opcode(irn)) {
272 /* the return node itself, ignore */
275 /* ignore the barrier, no code generated */
278 /* arg, IncSP 0 nodes might occur, ignore these */
279 if (be_get_IncSP_offset(irn) == 0)
288 /* yep, return is the first real instruction in this block */
291 /* add an rep prefix to the return */
292 ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
294 sched_add_before(node, rep);
297 /* ensure, that the 3 byte return is generated */
298 be_Return_set_emit_pop(node, 1);
302 /* only optimize up to 48 stores behind IncSPs */
303 #define MAXPUSH_OPTIMIZE 48
306 * Tries to create Push's from IncSP, Store combinations.
307 * The Stores are replaced by Push's, the IncSP is modified
308 * (possibly into IncSP 0, but not removed).
310 static void peephole_IncSP_Store_to_push(ir_node *irn)
312 int i, maxslot, inc_ofs;
314 ir_node *stores[MAXPUSH_OPTIMIZE];
320 memset(stores, 0, sizeof(stores));
322 assert(be_is_IncSP(irn));
324 inc_ofs = be_get_IncSP_offset(irn);
329 * We first walk the schedule after the IncSP node as long as we find
330 * suitable Stores that could be transformed to a Push.
331 * We save them into the stores array which is sorted by the frame offset/4
332 * attached to the node
335 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
340 /* it has to be a Store */
341 if (!is_ia32_Store(node))
344 /* it has to use our sp value */
345 if (get_irn_n(node, n_ia32_base) != irn)
347 /* Store has to be attached to NoMem */
348 mem = get_irn_n(node, n_ia32_mem);
352 /* unfortunately we can't support the full AMs possible for push at the
353 * moment. TODO: fix this */
354 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
357 offset = get_ia32_am_offs_int(node);
358 /* we should NEVER access uninitialized stack BELOW the current SP */
361 offset = inc_ofs - 4 - offset;
363 /* storing at half-slots is bad */
364 if ((offset & 3) != 0)
367 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
369 storeslot = offset >> 2;
371 /* storing into the same slot twice is bad (and shouldn't happen...) */
372 if (stores[storeslot] != NULL)
375 stores[storeslot] = node;
376 if (storeslot > maxslot)
380 curr_sp = be_get_IncSP_pred(irn);
382 /* walk through the Stores and create Pushs for them */
383 block = get_nodes_block(irn);
384 spmode = get_irn_mode(irn);
386 for (i = 0; i <= maxslot; ++i) {
387 const arch_register_t *spreg;
389 ir_node *val, *mem, *mem_proj;
390 ir_node *store = stores[i];
391 ir_node *noreg = ia32_new_NoReg_gp(cg);
396 val = get_irn_n(store, n_ia32_unary_op);
397 mem = get_irn_n(store, n_ia32_mem);
398 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
400 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
402 sched_add_before(irn, push);
404 /* create stackpointer Proj */
405 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
406 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
408 /* create memory Proj */
409 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
411 /* use the memproj now */
412 exchange(store, mem_proj);
414 /* we can remove the Store now */
420 be_set_IncSP_offset(irn, inc_ofs);
421 be_set_IncSP_pred(irn, curr_sp);
425 * Return true if a mode can be stored in the GP register set
427 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
428 if (mode == mode_fpcw)
430 if (get_mode_size_bits(mode) > 32)
432 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
436 * Tries to create Pops from Load, IncSP combinations.
437 * The Loads are replaced by Pops, the IncSP is modified
438 * (possibly into IncSP 0, but not removed).
440 static void peephole_Load_IncSP_to_pop(ir_node *irn)
442 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
443 int i, maxslot, inc_ofs, ofs;
444 ir_node *node, *pred_sp, *block;
445 ir_node *loads[MAXPUSH_OPTIMIZE];
447 unsigned regmask = 0;
448 unsigned copymask = ~0;
450 memset(loads, 0, sizeof(loads));
451 assert(be_is_IncSP(irn));
453 inc_ofs = -be_get_IncSP_offset(irn);
458 * We first walk the schedule before the IncSP node as long as we find
459 * suitable Loads that could be transformed to a Pop.
460 * We save them into the stores array which is sorted by the frame offset/4
461 * attached to the node
464 pred_sp = be_get_IncSP_pred(irn);
465 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
469 const arch_register_t *sreg, *dreg;
471 /* it has to be a Load */
472 if (!is_ia32_Load(node)) {
473 if (be_is_Copy(node)) {
474 if (!mode_needs_gp_reg(get_irn_mode(node))) {
475 /* not a GP copy, ignore */
478 dreg = arch_get_irn_register(arch_env, node);
479 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
480 if (regmask & copymask & (1 << sreg->index)) {
483 if (regmask & copymask & (1 << dreg->index)) {
486 /* we CAN skip Copies if neither the destination nor the source
487 * is not in our regmask, ie none of our future Pop will overwrite it */
488 regmask |= (1 << dreg->index) | (1 << sreg->index);
489 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
495 /* we can handle only GP loads */
496 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
499 /* it has to use our predecessor sp value */
500 if (get_irn_n(node, n_ia32_base) != pred_sp) {
501 /* it would be ok if this load does not use a Pop result,
502 * but we do not check this */
505 /* Load has to be attached to Spill-Mem */
506 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
507 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
510 /* should have NO index */
511 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
514 offset = get_ia32_am_offs_int(node);
515 /* we should NEVER access uninitialized stack BELOW the current SP */
518 /* storing at half-slots is bad */
519 if ((offset & 3) != 0)
522 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
524 /* ignore those outside the possible windows */
525 if (offset > inc_ofs - 4)
527 loadslot = offset >> 2;
529 /* loading from the same slot twice is bad (and shouldn't happen...) */
530 if (loads[loadslot] != NULL)
533 dreg = arch_get_irn_register(arch_env, node);
534 if (regmask & (1 << dreg->index)) {
535 /* this register is already used */
538 regmask |= 1 << dreg->index;
540 loads[loadslot] = node;
541 if (loadslot > maxslot)
548 /* find the first slot */
549 for (i = maxslot; i >= 0; --i) {
550 ir_node *load = loads[i];
556 ofs = inc_ofs - (maxslot + 1) * 4;
559 /* create a new IncSP if needed */
560 block = get_nodes_block(irn);
563 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
564 sched_add_before(irn, pred_sp);
567 /* walk through the Loads and create Pops for them */
568 for (++i; i <= maxslot; ++i) {
569 ir_node *load = loads[i];
571 const ir_edge_t *edge, *tmp;
572 const arch_register_t *reg;
574 mem = get_irn_n(load, n_ia32_mem);
575 reg = arch_get_irn_register(arch_env, load);
577 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
578 arch_set_irn_register(arch_env, pop, reg);
580 /* create stackpointer Proj */
581 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
582 arch_set_irn_register(arch_env, pred_sp, esp);
584 sched_add_before(irn, pop);
587 foreach_out_edge_safe(load, edge, tmp) {
588 ir_node *proj = get_edge_src_irn(edge);
590 set_Proj_pred(proj, pop);
594 /* we can remove the Load now */
598 be_set_IncSP_offset(irn, -ofs);
599 be_set_IncSP_pred(irn, pred_sp);
605 * Find a free GP register if possible, else return NULL.
607 static const arch_register_t *get_free_gp_reg(void)
611 for(i = 0; i < N_ia32_gp_REGS; ++i) {
612 const arch_register_t *reg = &ia32_gp_regs[i];
613 if(arch_register_type_is(reg, ignore))
616 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
617 return &ia32_gp_regs[i];
624 * Creates a Pop instruction before the given schedule point.
626 * @param dbgi debug info
627 * @param irg the graph
628 * @param block the block
629 * @param stack the previous stack value
630 * @param schedpoint the new node is added before this node
631 * @param reg the register to pop
633 * @return the new stack value
635 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
636 ir_node *stack, ir_node *schedpoint,
637 const arch_register_t *reg)
639 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
645 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
647 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
648 arch_set_irn_register(arch_env, stack, esp);
649 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
650 arch_set_irn_register(arch_env, val, reg);
652 sched_add_before(schedpoint, pop);
655 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
656 sched_add_before(schedpoint, keep);
662 * Creates a Push instruction before the given schedule point.
664 * @param dbgi debug info
665 * @param irg the graph
666 * @param block the block
667 * @param stack the previous stack value
668 * @param schedpoint the new node is added before this node
669 * @param reg the register to pop
671 * @return the new stack value
673 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
674 ir_node *stack, ir_node *schedpoint,
675 const arch_register_t *reg)
677 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
678 ir_node *noreg, *nomem, *push, *val;
680 val = new_rd_ia32_ProduceVal(NULL, irg, block);
681 arch_set_irn_register(arch_env, val, reg);
682 sched_add_before(schedpoint, val);
684 noreg = ia32_new_NoReg_gp(cg);
685 nomem = get_irg_no_mem(irg);
686 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
687 sched_add_before(schedpoint, push);
689 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
690 arch_set_irn_register(arch_env, stack, esp);
696 * Optimize an IncSp by replacing it with Push/Pop.
698 static void peephole_be_IncSP(ir_node *node)
700 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
701 const arch_register_t *reg;
702 ir_graph *irg = current_ir_graph;
708 /* first optimize incsp->incsp combinations */
709 node = be_peephole_IncSP_IncSP(node);
711 /* transform IncSP->Store combinations to Push where possible */
712 peephole_IncSP_Store_to_push(node);
714 /* transform Load->IncSP combinations to Pop where possible */
715 peephole_Load_IncSP_to_pop(node);
717 if (arch_get_irn_register(arch_env, node) != esp)
720 /* replace IncSP -4 by Pop freereg when possible */
721 offset = be_get_IncSP_offset(node);
722 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
723 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
724 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
725 (offset != +8 || ia32_cg_config.use_sub_esp_8))
729 /* we need a free register for pop */
730 reg = get_free_gp_reg();
734 dbgi = get_irn_dbg_info(node);
735 block = get_nodes_block(node);
736 stack = be_get_IncSP_pred(node);
738 stack = create_pop(dbgi, irg, block, stack, node, reg);
741 stack = create_pop(dbgi, irg, block, stack, node, reg);
744 dbgi = get_irn_dbg_info(node);
745 block = get_nodes_block(node);
746 stack = be_get_IncSP_pred(node);
747 reg = &ia32_gp_regs[REG_EAX];
749 stack = create_push(dbgi, irg, block, stack, node, reg);
752 stack = create_push(dbgi, irg, block, stack, node, reg);
756 be_peephole_before_exchange(node, stack);
758 exchange(node, stack);
759 be_peephole_after_exchange(stack);
763 * Peephole optimisation for ia32_Const's
765 static void peephole_ia32_Const(ir_node *node)
767 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
768 const arch_register_t *reg;
769 ir_graph *irg = current_ir_graph;
776 /* try to transform a mov 0, reg to xor reg reg */
777 if (attr->offset != 0 || attr->symconst != NULL)
779 if (ia32_cg_config.use_mov_0)
781 /* xor destroys the flags, so no-one must be using them */
782 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
785 reg = arch_get_irn_register(arch_env, node);
786 assert(be_peephole_get_reg_value(reg) == NULL);
788 /* create xor(produceval, produceval) */
789 block = get_nodes_block(node);
790 dbgi = get_irn_dbg_info(node);
791 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
792 arch_set_irn_register(arch_env, produceval, reg);
794 noreg = ia32_new_NoReg_gp(cg);
795 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
796 produceval, produceval);
797 arch_set_irn_register(arch_env, xor, reg);
799 sched_add_before(node, produceval);
800 sched_add_before(node, xor);
802 be_peephole_before_exchange(node, xor);
805 be_peephole_after_exchange(xor);
808 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
810 return node == cg->noreg_gp;
813 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
815 ir_graph *irg = current_ir_graph;
816 ir_node *start_block = get_irg_start_block(irg);
817 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
819 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
824 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
827 ir_graph *irg = get_irn_irg(node);
828 ir_node *block = get_nodes_block(node);
829 int offset = get_ia32_am_offs_int(node);
830 int sc_sign = is_ia32_am_sc_sign(node);
831 ir_entity *entity = get_ia32_am_sc(node);
834 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
835 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
839 static int is_am_one(const ir_node *node)
841 int offset = get_ia32_am_offs_int(node);
842 ir_entity *entity = get_ia32_am_sc(node);
844 return offset == 1 && entity == NULL;
847 static int is_am_minus_one(const ir_node *node)
849 int offset = get_ia32_am_offs_int(node);
850 ir_entity *entity = get_ia32_am_sc(node);
852 return offset == -1 && entity == NULL;
856 * Transforms a LEA into an Add or SHL if possible.
858 static void peephole_ia32_Lea(ir_node *node)
860 const arch_env_t *arch_env = cg->arch_env;
861 ir_graph *irg = current_ir_graph;
864 const arch_register_t *base_reg;
865 const arch_register_t *index_reg;
866 const arch_register_t *out_reg;
877 assert(is_ia32_Lea(node));
879 /* we can only do this if are allowed to globber the flags */
880 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
883 base = get_irn_n(node, n_ia32_Lea_base);
884 index = get_irn_n(node, n_ia32_Lea_index);
886 if(is_noreg(cg, base)) {
890 base_reg = arch_get_irn_register(arch_env, base);
892 if(is_noreg(cg, index)) {
896 index_reg = arch_get_irn_register(arch_env, index);
899 if(base == NULL && index == NULL) {
900 /* we shouldn't construct these in the first place... */
902 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
907 out_reg = arch_get_irn_register(arch_env, node);
908 scale = get_ia32_am_scale(node);
909 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
910 /* check if we have immediates values (frame entities should already be
911 * expressed in the offsets) */
912 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
918 /* we can transform leas where the out register is the same as either the
919 * base or index register back to an Add or Shl */
920 if(out_reg == base_reg) {
923 if(!has_immediates) {
924 ir_fprintf(stderr, "Optimisation warning: found lea which is "
929 goto make_add_immediate;
931 if(scale == 0 && !has_immediates) {
936 /* can't create an add */
938 } else if(out_reg == index_reg) {
940 if(has_immediates && scale == 0) {
942 goto make_add_immediate;
943 } else if(!has_immediates && scale > 0) {
945 op2 = create_immediate_from_int(cg, scale);
947 } else if(!has_immediates) {
949 ir_fprintf(stderr, "Optimisation warning: found lea which is "
953 } else if(scale == 0 && !has_immediates) {
958 /* can't create an add */
961 /* can't create an add */
966 if(ia32_cg_config.use_incdec) {
967 if(is_am_one(node)) {
968 dbgi = get_irn_dbg_info(node);
969 block = get_nodes_block(node);
970 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
971 arch_set_irn_register(arch_env, res, out_reg);
974 if(is_am_minus_one(node)) {
975 dbgi = get_irn_dbg_info(node);
976 block = get_nodes_block(node);
977 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
978 arch_set_irn_register(arch_env, res, out_reg);
982 op2 = create_immediate_from_am(cg, node);
985 dbgi = get_irn_dbg_info(node);
986 block = get_nodes_block(node);
987 noreg = ia32_new_NoReg_gp(cg);
989 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
990 arch_set_irn_register(arch_env, res, out_reg);
991 set_ia32_commutative(res);
995 dbgi = get_irn_dbg_info(node);
996 block = get_nodes_block(node);
997 noreg = ia32_new_NoReg_gp(cg);
999 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1000 arch_set_irn_register(arch_env, res, out_reg);
1004 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1006 /* add new ADD/SHL to schedule */
1007 DBG_OPT_LEA2ADD(node, res);
1009 /* exchange the Add and the LEA */
1010 be_peephole_before_exchange(node, res);
1011 sched_add_before(node, res);
1013 exchange(node, res);
1014 be_peephole_after_exchange(res);
1018 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1020 static void peephole_ia32_Imul_split(ir_node *imul) {
1021 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1022 const arch_register_t *reg;
1023 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
1027 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1028 /* no memory, imm form ignore */
1031 /* we need a free register */
1032 reg = get_free_gp_reg();
1036 /* fine, we can rebuild it */
1037 dbgi = get_irn_dbg_info(imul);
1038 block = get_nodes_block(imul);
1039 irg = current_ir_graph;
1040 base = get_irn_n(imul, n_ia32_IMul_base);
1041 index = get_irn_n(imul, n_ia32_IMul_index);
1042 mem = get_irn_n(imul, n_ia32_IMul_mem);
1043 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1045 /* copy all attributes */
1046 set_irn_pinned(load, get_irn_pinned(imul));
1047 set_ia32_op_type(load, ia32_AddrModeS);
1048 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1050 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1051 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1052 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1053 if (is_ia32_am_sc_sign(imul))
1054 set_ia32_am_sc_sign(load);
1055 if (is_ia32_use_frame(imul))
1056 set_ia32_use_frame(load);
1057 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1059 sched_add_before(imul, load);
1061 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1062 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1064 arch_set_irn_register(arch_env, res, reg);
1065 be_peephole_after_exchange(res);
1067 set_irn_n(imul, n_ia32_IMul_mem, mem);
1068 noreg = get_irn_n(imul, n_ia32_IMul_left);
1069 set_irn_n(imul, n_ia32_IMul_left, res);
1070 set_ia32_op_type(imul, ia32_Normal);
1074 * Replace xorps r,r and xorpd r,r by pxor r,r
1076 static void peephole_ia32_xZero(ir_node *xor) {
1077 set_irn_op(xor, op_ia32_xPzero);
1081 * Register a peephole optimisation function.
1083 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1084 assert(op->ops.generic == NULL);
1085 op->ops.generic = (op_func)func;
1088 /* Perform peephole-optimizations. */
1089 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1092 arch_env = cg->arch_env;
1094 /* register peephole optimisations */
1095 clear_irp_opcodes_generic_func();
1096 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1097 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1098 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1099 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1100 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1101 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1102 if (! ia32_cg_config.use_imul_mem_imm32)
1103 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1104 if (ia32_cg_config.use_pxor)
1105 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1107 be_peephole_opt(cg->birg);
1111 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1112 * all it's Projs are removed as well.
1113 * @param irn The irn to be removed from schedule
1115 static INLINE void try_kill(ir_node *node)
1117 if(get_irn_mode(node) == mode_T) {
1118 const ir_edge_t *edge, *next;
1119 foreach_out_edge_safe(node, edge, next) {
1120 ir_node *proj = get_edge_src_irn(edge);
1125 if(get_irn_n_edges(node) != 0)
1128 if (sched_is_scheduled(node)) {
1135 static void optimize_conv_store(ir_node *node)
1140 ir_mode *store_mode;
1142 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1145 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1146 pred_proj = get_irn_n(node, n_ia32_Store_val);
1147 if(is_Proj(pred_proj)) {
1148 pred = get_Proj_pred(pred_proj);
1152 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1154 if(get_ia32_op_type(pred) != ia32_Normal)
1157 /* the store only stores the lower bits, so we only need the conv
1158 * it it shrinks the mode */
1159 conv_mode = get_ia32_ls_mode(pred);
1160 store_mode = get_ia32_ls_mode(node);
1161 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1164 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1165 if(get_irn_n_edges(pred_proj) == 0) {
1166 be_kill_node(pred_proj);
1167 if(pred != pred_proj)
1172 static void optimize_load_conv(ir_node *node)
1174 ir_node *pred, *predpred;
1178 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1181 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1182 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1186 predpred = get_Proj_pred(pred);
1187 if(!is_ia32_Load(predpred))
1190 /* the load is sign extending the upper bits, so we only need the conv
1191 * if it shrinks the mode */
1192 load_mode = get_ia32_ls_mode(predpred);
1193 conv_mode = get_ia32_ls_mode(node);
1194 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1197 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1198 /* change the load if it has only 1 user */
1199 if(get_irn_n_edges(pred) == 1) {
1201 if(get_mode_sign(conv_mode)) {
1202 newmode = find_signed_mode(load_mode);
1204 newmode = find_unsigned_mode(load_mode);
1206 assert(newmode != NULL);
1207 set_ia32_ls_mode(predpred, newmode);
1209 /* otherwise we have to keep the conv */
1215 exchange(node, pred);
1218 static void optimize_conv_conv(ir_node *node)
1220 ir_node *pred_proj, *pred, *result_conv;
1221 ir_mode *pred_mode, *conv_mode;
1225 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1228 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1229 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1230 if(is_Proj(pred_proj))
1231 pred = get_Proj_pred(pred_proj);
1235 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1238 /* we know that after a conv, the upper bits are sign extended
1239 * so we only need the 2nd conv if it shrinks the mode */
1240 conv_mode = get_ia32_ls_mode(node);
1241 conv_mode_bits = get_mode_size_bits(conv_mode);
1242 pred_mode = get_ia32_ls_mode(pred);
1243 pred_mode_bits = get_mode_size_bits(pred_mode);
1245 if(conv_mode_bits == pred_mode_bits
1246 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1247 result_conv = pred_proj;
1248 } else if(conv_mode_bits <= pred_mode_bits) {
1249 /* if 2nd conv is smaller then first conv, then we can always take the
1251 if(get_irn_n_edges(pred_proj) == 1) {
1252 result_conv = pred_proj;
1253 set_ia32_ls_mode(pred, conv_mode);
1255 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1256 if (get_mode_size_bits(conv_mode) == 8) {
1257 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1258 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1261 /* we don't want to end up with 2 loads, so we better do nothing */
1262 if(get_irn_mode(pred) == mode_T) {
1266 result_conv = exact_copy(pred);
1267 set_ia32_ls_mode(result_conv, conv_mode);
1269 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1270 if (get_mode_size_bits(conv_mode) == 8) {
1271 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1272 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1276 /* if both convs have the same sign, then we can take the smaller one */
1277 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1278 result_conv = pred_proj;
1280 /* no optimisation possible if smaller conv is sign-extend */
1281 if(mode_is_signed(pred_mode)) {
1284 /* we can take the smaller conv if it is unsigned */
1285 result_conv = pred_proj;
1290 exchange(node, result_conv);
1292 if(get_irn_n_edges(pred_proj) == 0) {
1293 be_kill_node(pred_proj);
1294 if(pred != pred_proj)
1297 optimize_conv_conv(result_conv);
1300 static void optimize_node(ir_node *node, void *env)
1304 optimize_load_conv(node);
1305 optimize_conv_store(node);
1306 optimize_conv_conv(node);
1310 * Performs conv and address mode optimization.
1312 void ia32_optimize_graph(ia32_code_gen_t *cg)
1314 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1317 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1320 void ia32_init_optimize(void)
1322 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");