2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* happens rarely, but if it does code will panic' */
258 if (is_ia32_Unknown_GP(left))
261 /* walk schedule up and abort when we find left or some other node destroys
263 schedpoint = sched_prev(node);
264 while(schedpoint != left) {
265 schedpoint = sched_prev(schedpoint);
266 if(arch_irn_is(arch_env, schedpoint, modify_flags))
268 if(schedpoint == block)
269 panic("couldn't find left");
272 /* make sure only Lg/Eq tests are used */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 int pnc = get_ia32_condcode(user);
277 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
282 if(!produces_zero_flag(left, pn))
285 left = turn_into_mode_t(left);
287 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
288 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
290 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
292 assert(get_irn_mode(node) != mode_T);
294 be_peephole_before_exchange(node, flags_proj);
295 exchange(node, flags_proj);
297 be_peephole_after_exchange(flags_proj);
300 // only optimize up to 48 stores behind IncSPs
301 #define MAXPUSH_OPTIMIZE 48
304 * Tries to create pushs from IncSP,Store combinations
306 static void peephole_IncSP_Store_to_push(ir_node *irn)
311 ir_node *stores[MAXPUSH_OPTIMIZE];
312 ir_node *block = get_nodes_block(irn);
313 ir_graph *irg = cg->irg;
315 ir_mode *spmode = get_irn_mode(irn);
317 memset(stores, 0, sizeof(stores));
319 assert(be_is_IncSP(irn));
321 offset = be_get_IncSP_offset(irn);
326 * We first walk the schedule after the IncSP node as long as we find
327 * suitable stores that could be transformed to a push.
328 * We save them into the stores array which is sorted by the frame offset/4
329 * attached to the node
331 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
336 // it has to be a store
337 if(!is_ia32_Store(node))
340 // it has to use our sp value
341 if(get_irn_n(node, n_ia32_base) != irn)
343 // store has to be attached to NoMem
344 mem = get_irn_n(node, n_ia32_mem);
349 /* unfortunately we can't support the full AMs possible for push at the
350 * moment. TODO: fix this */
351 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
354 offset = get_ia32_am_offs_int(node);
356 storeslot = offset / 4;
357 if(storeslot >= MAXPUSH_OPTIMIZE)
360 // storing into the same slot twice is bad (and shouldn't happen...)
361 if(stores[storeslot] != NULL)
364 // storing at half-slots is bad
368 stores[storeslot] = node;
371 curr_sp = be_get_IncSP_pred(irn);
373 // walk the stores in inverse order and create pushs for them
374 i = (offset / 4) - 1;
375 if(i >= MAXPUSH_OPTIMIZE) {
376 i = MAXPUSH_OPTIMIZE - 1;
379 for( ; i >= 0; --i) {
380 const arch_register_t *spreg;
382 ir_node *val, *mem, *mem_proj;
383 ir_node *store = stores[i];
384 ir_node *noreg = ia32_new_NoReg_gp(cg);
386 if(store == NULL || is_Bad(store))
389 val = get_irn_n(store, n_ia32_unary_op);
390 mem = get_irn_n(store, n_ia32_mem);
391 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
393 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val);
395 sched_add_before(irn, push);
397 // create stackpointer proj
398 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
399 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
401 // create memory proj
402 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
404 // use the memproj now
405 exchange(store, mem_proj);
407 // we can remove the store now
413 be_set_IncSP_offset(irn, offset);
414 be_set_IncSP_pred(irn, curr_sp);
418 * Tries to optimize two following IncSP.
420 static void peephole_IncSP_IncSP(ir_node *node)
425 ir_node *pred = be_get_IncSP_pred(node);
428 if(!be_is_IncSP(pred))
431 if(get_irn_n_edges(pred) > 1)
434 pred_offs = be_get_IncSP_offset(pred);
435 curr_offs = be_get_IncSP_offset(node);
437 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
438 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
442 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
443 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
447 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
448 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
451 offs = curr_offs + pred_offs;
454 /* add pred offset to ours and remove pred IncSP */
455 be_set_IncSP_offset(node, offs);
457 predpred = be_get_IncSP_pred(pred);
458 be_peephole_before_exchange(pred, predpred);
460 /* rewire dependency edges */
461 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
462 be_set_IncSP_pred(node, predpred);
466 be_peephole_after_exchange(predpred);
469 static const arch_register_t *get_free_gp_reg(void)
473 for(i = 0; i < N_ia32_gp_REGS; ++i) {
474 const arch_register_t *reg = &ia32_gp_regs[i];
475 if(arch_register_type_is(reg, ignore))
478 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
479 return &ia32_gp_regs[i];
485 static void peephole_be_IncSP(ir_node *node)
487 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
488 const arch_register_t *reg;
499 /* first optimize incsp->incsp combinations */
500 peephole_IncSP_IncSP(node);
502 /* transform IncSP->Store combinations to Push where possible */
503 peephole_IncSP_Store_to_push(node);
505 /* replace IncSP -4 by Pop freereg when possible */
506 offset = be_get_IncSP_offset(node);
510 if(arch_get_irn_register(arch_env, node) != esp)
513 reg = get_free_gp_reg();
517 irg = current_ir_graph;
518 dbgi = get_irn_dbg_info(node);
519 block = get_nodes_block(node);
520 noreg = ia32_new_NoReg_gp(cg);
521 stack = be_get_IncSP_pred(node);
522 pop = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack);
524 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
525 arch_set_irn_register(arch_env, stack, esp);
526 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
527 arch_set_irn_register(arch_env, val, reg);
529 sched_add_before(node, pop);
531 keep = sched_next(node);
532 if(!be_is_Keep(keep)) {
535 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
536 sched_add_before(node, keep);
538 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
541 be_peephole_before_exchange(node, stack);
543 exchange(node, stack);
544 be_peephole_after_exchange(stack);
548 * Peephole optimisation for ia32_Const's
550 static void peephole_ia32_Const(ir_node *node)
552 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
553 const arch_register_t *reg;
554 ir_graph *irg = current_ir_graph;
561 /* try to transform a mov 0, reg to xor reg reg */
562 if(attr->offset != 0 || attr->symconst != NULL)
564 /* xor destroys the flags, so no-one must be using them */
565 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
568 reg = arch_get_irn_register(arch_env, node);
569 assert(be_peephole_get_reg_value(reg) == NULL);
571 /* create xor(produceval, produceval) */
572 block = get_nodes_block(node);
573 dbgi = get_irn_dbg_info(node);
574 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
575 arch_set_irn_register(arch_env, produceval, reg);
577 noreg = ia32_new_NoReg_gp(cg);
578 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
579 produceval, produceval);
580 arch_set_irn_register(arch_env, xor, reg);
582 sched_add_before(node, produceval);
583 sched_add_before(node, xor);
585 be_peephole_before_exchange(node, xor);
588 be_peephole_after_exchange(xor);
591 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
593 return node == cg->noreg_gp;
596 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
598 ir_graph *irg = current_ir_graph;
599 ir_node *start_block = get_irg_start_block(irg);
600 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
602 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
607 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
610 ir_graph *irg = get_irn_irg(node);
611 ir_node *block = get_nodes_block(node);
612 int offset = get_ia32_am_offs_int(node);
613 int sc_sign = is_ia32_am_sc_sign(node);
614 ir_entity *entity = get_ia32_am_sc(node);
617 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
618 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
622 static int is_am_one(const ir_node *node)
624 int offset = get_ia32_am_offs_int(node);
625 ir_entity *entity = get_ia32_am_sc(node);
627 return offset == 1 && entity == NULL;
630 static int is_am_minus_one(const ir_node *node)
632 int offset = get_ia32_am_offs_int(node);
633 ir_entity *entity = get_ia32_am_sc(node);
635 return offset == -1 && entity == NULL;
639 * Transforms a LEA into an Add or SHL if possible.
641 static void peephole_ia32_Lea(ir_node *node)
643 const arch_env_t *arch_env = cg->arch_env;
644 ir_graph *irg = current_ir_graph;
647 const arch_register_t *base_reg;
648 const arch_register_t *index_reg;
649 const arch_register_t *out_reg;
660 assert(is_ia32_Lea(node));
662 /* we can only do this if are allowed to globber the flags */
663 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
666 base = get_irn_n(node, n_ia32_Lea_base);
667 index = get_irn_n(node, n_ia32_Lea_index);
669 if(is_noreg(cg, base)) {
673 base_reg = arch_get_irn_register(arch_env, base);
675 if(is_noreg(cg, index)) {
679 index_reg = arch_get_irn_register(arch_env, index);
682 if(base == NULL && index == NULL) {
683 /* we shouldn't construct these in the first place... */
685 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
690 out_reg = arch_get_irn_register(arch_env, node);
691 scale = get_ia32_am_scale(node);
692 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
693 /* check if we have immediates values (frame entities should already be
694 * expressed in the offsets) */
695 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
701 /* we can transform leas where the out register is the same as either the
702 * base or index register back to an Add or Shl */
703 if(out_reg == base_reg) {
706 if(!has_immediates) {
707 ir_fprintf(stderr, "Optimisation warning: found lea which is "
712 goto make_add_immediate;
714 if(scale == 0 && !has_immediates) {
719 /* can't create an add */
721 } else if(out_reg == index_reg) {
723 if(has_immediates && scale == 0) {
725 goto make_add_immediate;
726 } else if(!has_immediates && scale > 0) {
728 op2 = create_immediate_from_int(cg, scale);
730 } else if(!has_immediates) {
732 ir_fprintf(stderr, "Optimisation warning: found lea which is "
736 } else if(scale == 0 && !has_immediates) {
741 /* can't create an add */
744 /* can't create an add */
749 if(ia32_cg_config.use_incdec) {
750 if(is_am_one(node)) {
751 dbgi = get_irn_dbg_info(node);
752 block = get_nodes_block(node);
753 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
754 arch_set_irn_register(arch_env, res, out_reg);
757 if(is_am_minus_one(node)) {
758 dbgi = get_irn_dbg_info(node);
759 block = get_nodes_block(node);
760 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
761 arch_set_irn_register(arch_env, res, out_reg);
765 op2 = create_immediate_from_am(cg, node);
768 dbgi = get_irn_dbg_info(node);
769 block = get_nodes_block(node);
770 noreg = ia32_new_NoReg_gp(cg);
772 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
773 arch_set_irn_register(arch_env, res, out_reg);
774 set_ia32_commutative(res);
778 dbgi = get_irn_dbg_info(node);
779 block = get_nodes_block(node);
780 noreg = ia32_new_NoReg_gp(cg);
782 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
783 arch_set_irn_register(arch_env, res, out_reg);
787 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
789 /* add new ADD/SHL to schedule */
790 DBG_OPT_LEA2ADD(node, res);
792 /* exchange the Add and the LEA */
793 be_peephole_before_exchange(node, res);
794 sched_add_before(node, res);
797 be_peephole_after_exchange(res);
801 * Register a peephole optimisation function.
803 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
804 assert(op->ops.generic == NULL);
805 op->ops.generic = (void*) func;
808 /* Perform peephole-optimizations. */
809 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
812 arch_env = cg->arch_env;
814 /* register peephole optimisations */
815 clear_irp_opcodes_generic_func();
816 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
817 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
818 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
819 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
820 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
821 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
823 be_peephole_opt(cg->birg);
827 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
828 * all it's Projs are removed as well.
829 * @param irn The irn to be removed from schedule
831 static INLINE void try_kill(ir_node *node)
833 if(get_irn_mode(node) == mode_T) {
834 const ir_edge_t *edge, *next;
835 foreach_out_edge_safe(node, edge, next) {
836 ir_node *proj = get_edge_src_irn(edge);
841 if(get_irn_n_edges(node) != 0)
844 if (sched_is_scheduled(node)) {
851 static void optimize_conv_store(ir_node *node)
858 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
861 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
862 pred_proj = get_irn_n(node, n_ia32_Store_val);
863 if(is_Proj(pred_proj)) {
864 pred = get_Proj_pred(pred_proj);
868 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
870 if(get_ia32_op_type(pred) != ia32_Normal)
873 /* the store only stores the lower bits, so we only need the conv
874 * it it shrinks the mode */
875 conv_mode = get_ia32_ls_mode(pred);
876 store_mode = get_ia32_ls_mode(node);
877 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
880 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
881 if(get_irn_n_edges(pred_proj) == 0) {
882 be_kill_node(pred_proj);
883 if(pred != pred_proj)
888 static void optimize_load_conv(ir_node *node)
890 ir_node *pred, *predpred;
894 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
897 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
898 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
902 predpred = get_Proj_pred(pred);
903 if(!is_ia32_Load(predpred))
906 /* the load is sign extending the upper bits, so we only need the conv
907 * if it shrinks the mode */
908 load_mode = get_ia32_ls_mode(predpred);
909 conv_mode = get_ia32_ls_mode(node);
910 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
913 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
914 /* change the load if it has only 1 user */
915 if(get_irn_n_edges(pred) == 1) {
917 if(get_mode_sign(conv_mode)) {
918 newmode = find_signed_mode(load_mode);
920 newmode = find_unsigned_mode(load_mode);
922 assert(newmode != NULL);
923 set_ia32_ls_mode(predpred, newmode);
925 /* otherwise we have to keep the conv */
931 exchange(node, pred);
934 static void optimize_conv_conv(ir_node *node)
936 ir_node *pred_proj, *pred, *result_conv;
937 ir_mode *pred_mode, *conv_mode;
941 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
944 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
945 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
946 if(is_Proj(pred_proj))
947 pred = get_Proj_pred(pred_proj);
951 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
954 /* we know that after a conv, the upper bits are sign extended
955 * so we only need the 2nd conv if it shrinks the mode */
956 conv_mode = get_ia32_ls_mode(node);
957 conv_mode_bits = get_mode_size_bits(conv_mode);
958 pred_mode = get_ia32_ls_mode(pred);
959 pred_mode_bits = get_mode_size_bits(pred_mode);
961 if(conv_mode_bits == pred_mode_bits
962 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
963 result_conv = pred_proj;
964 } else if(conv_mode_bits <= pred_mode_bits) {
965 /* if 2nd conv is smaller then first conv, then we can always take the
967 if(get_irn_n_edges(pred_proj) == 1) {
968 result_conv = pred_proj;
969 set_ia32_ls_mode(pred, conv_mode);
971 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
972 if (get_mode_size_bits(conv_mode) == 8) {
973 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
974 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
977 /* we don't want to end up with 2 loads, so we better do nothing */
978 if(get_irn_mode(pred) == mode_T) {
982 result_conv = exact_copy(pred);
983 set_ia32_ls_mode(result_conv, conv_mode);
985 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
986 if (get_mode_size_bits(conv_mode) == 8) {
987 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
988 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
992 /* if both convs have the same sign, then we can take the smaller one */
993 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
994 result_conv = pred_proj;
996 /* no optimisation possible if smaller conv is sign-extend */
997 if(mode_is_signed(pred_mode)) {
1000 /* we can take the smaller conv if it is unsigned */
1001 result_conv = pred_proj;
1006 exchange(node, result_conv);
1008 if(get_irn_n_edges(pred_proj) == 0) {
1009 be_kill_node(pred_proj);
1010 if(pred != pred_proj)
1013 optimize_conv_conv(result_conv);
1016 static void optimize_node(ir_node *node, void *env)
1020 optimize_load_conv(node);
1021 optimize_conv_store(node);
1022 optimize_conv_conv(node);
1026 * Performs conv and address mode optimization.
1028 void ia32_optimize_graph(ia32_code_gen_t *cg)
1030 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1033 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1036 void ia32_init_optimize(void)
1038 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");