2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* walk schedule up and abort when we find left or some other node destroys
259 schedpoint = sched_prev(node);
260 while(schedpoint != left) {
261 schedpoint = sched_prev(schedpoint);
262 if(arch_irn_is(arch_env, schedpoint, modify_flags))
264 if(schedpoint == block)
265 panic("couldn't find left");
268 /* make sure only Lg/Eq tests are used */
269 foreach_out_edge(node, edge) {
270 ir_node *user = get_edge_src_irn(edge);
271 int pnc = get_ia32_condcode(user);
273 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
278 if(!produces_zero_flag(left, pn))
281 left = turn_into_mode_t(left);
283 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
284 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
286 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
288 assert(get_irn_mode(node) != mode_T);
290 be_peephole_before_exchange(node, flags_proj);
291 exchange(node, flags_proj);
293 be_peephole_after_exchange(flags_proj);
296 // only optimize up to 48 stores behind IncSPs
297 #define MAXPUSH_OPTIMIZE 48
300 * Tries to create pushs from IncSP,Store combinations
302 static void peephole_IncSP_Store_to_push(ir_node *irn)
307 ir_node *stores[MAXPUSH_OPTIMIZE];
308 ir_node *block = get_nodes_block(irn);
309 ir_graph *irg = cg->irg;
311 ir_mode *spmode = get_irn_mode(irn);
313 memset(stores, 0, sizeof(stores));
315 assert(be_is_IncSP(irn));
317 offset = be_get_IncSP_offset(irn);
322 * We first walk the schedule after the IncSP node as long as we find
323 * suitable stores that could be transformed to a push.
324 * We save them into the stores array which is sorted by the frame offset/4
325 * attached to the node
327 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
332 // it has to be a store
333 if(!is_ia32_Store(node))
336 // it has to use our sp value
337 if(get_irn_n(node, n_ia32_base) != irn)
339 // store has to be attached to NoMem
340 mem = get_irn_n(node, n_ia32_mem);
345 /* unfortunately we can't support the full AMs possible for push at the
346 * moment. TODO: fix this */
347 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
350 offset = get_ia32_am_offs_int(node);
352 storeslot = offset / 4;
353 if(storeslot >= MAXPUSH_OPTIMIZE)
356 // storing into the same slot twice is bad (and shouldn't happen...)
357 if(stores[storeslot] != NULL)
360 // storing at half-slots is bad
364 stores[storeslot] = node;
367 curr_sp = be_get_IncSP_pred(irn);
369 // walk the stores in inverse order and create pushs for them
370 i = (offset / 4) - 1;
371 if(i >= MAXPUSH_OPTIMIZE) {
372 i = MAXPUSH_OPTIMIZE - 1;
375 for( ; i >= 0; --i) {
376 const arch_register_t *spreg;
378 ir_node *val, *mem, *mem_proj;
379 ir_node *store = stores[i];
380 ir_node *noreg = ia32_new_NoReg_gp(cg);
382 if(store == NULL || is_Bad(store))
385 val = get_irn_n(store, n_ia32_unary_op);
386 mem = get_irn_n(store, n_ia32_mem);
387 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
389 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val);
391 sched_add_before(irn, push);
393 // create stackpointer proj
394 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
395 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
397 // create memory proj
398 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
400 // use the memproj now
401 exchange(store, mem_proj);
403 // we can remove the store now
409 be_set_IncSP_offset(irn, offset);
410 be_set_IncSP_pred(irn, curr_sp);
414 * Tries to optimize two following IncSP.
416 static void peephole_IncSP_IncSP(ir_node *node)
421 ir_node *pred = be_get_IncSP_pred(node);
424 if(!be_is_IncSP(pred))
427 if(get_irn_n_edges(pred) > 1)
430 pred_offs = be_get_IncSP_offset(pred);
431 curr_offs = be_get_IncSP_offset(node);
433 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
434 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
438 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
439 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
443 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
444 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
447 offs = curr_offs + pred_offs;
450 /* add pred offset to ours and remove pred IncSP */
451 be_set_IncSP_offset(node, offs);
453 predpred = be_get_IncSP_pred(pred);
454 be_peephole_before_exchange(pred, predpred);
456 /* rewire dependency edges */
457 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
458 be_set_IncSP_pred(node, predpred);
462 be_peephole_after_exchange(predpred);
465 static const arch_register_t *get_free_gp_reg(void)
469 for(i = 0; i < N_ia32_gp_REGS; ++i) {
470 const arch_register_t *reg = &ia32_gp_regs[i];
471 if(arch_register_type_is(reg, ignore))
474 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
475 return &ia32_gp_regs[i];
481 static void peephole_be_IncSP(ir_node *node)
483 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
484 const arch_register_t *reg;
495 /* first optimize incsp->incsp combinations */
496 peephole_IncSP_IncSP(node);
498 /* transform IncSP->Store combinations to Push where possible */
499 peephole_IncSP_Store_to_push(node);
501 /* replace IncSP -4 by Pop freereg when possible */
502 offset = be_get_IncSP_offset(node);
506 if(arch_get_irn_register(arch_env, node) != esp)
509 reg = get_free_gp_reg();
513 irg = current_ir_graph;
514 dbgi = get_irn_dbg_info(node);
515 block = get_nodes_block(node);
516 noreg = ia32_new_NoReg_gp(cg);
517 stack = be_get_IncSP_pred(node);
518 pop = new_rd_ia32_Pop(dbgi, irg, block, noreg, noreg, new_NoMem(), stack);
520 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
521 arch_set_irn_register(arch_env, stack, esp);
522 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
523 arch_set_irn_register(arch_env, val, reg);
525 sched_add_before(node, pop);
527 keep = sched_next(node);
528 if(!be_is_Keep(keep)) {
531 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
532 sched_add_before(node, keep);
534 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
537 be_peephole_before_exchange(node, stack);
539 exchange(node, stack);
540 be_peephole_after_exchange(stack);
544 * Peephole optimisation for ia32_Const's
546 static void peephole_ia32_Const(ir_node *node)
548 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
549 const arch_register_t *reg;
550 ir_graph *irg = current_ir_graph;
557 /* try to transform a mov 0, reg to xor reg reg */
558 if(attr->offset != 0 || attr->symconst != NULL)
560 /* xor destroys the flags, so no-one must be using them */
561 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
564 reg = arch_get_irn_register(arch_env, node);
565 assert(be_peephole_get_reg_value(reg) == NULL);
567 /* create xor(produceval, produceval) */
568 block = get_nodes_block(node);
569 dbgi = get_irn_dbg_info(node);
570 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
571 arch_set_irn_register(arch_env, produceval, reg);
573 noreg = ia32_new_NoReg_gp(cg);
574 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
575 produceval, produceval);
576 arch_set_irn_register(arch_env, xor, reg);
578 sched_add_before(node, produceval);
579 sched_add_before(node, xor);
581 be_peephole_before_exchange(node, xor);
584 be_peephole_after_exchange(xor);
587 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
589 return node == cg->noreg_gp;
592 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
594 ir_graph *irg = current_ir_graph;
595 ir_node *start_block = get_irg_start_block(irg);
596 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
598 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
603 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
606 ir_graph *irg = get_irn_irg(node);
607 ir_node *block = get_nodes_block(node);
608 int offset = get_ia32_am_offs_int(node);
609 int sc_sign = is_ia32_am_sc_sign(node);
610 ir_entity *entity = get_ia32_am_sc(node);
613 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
614 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
618 static int is_am_one(const ir_node *node)
620 int offset = get_ia32_am_offs_int(node);
621 ir_entity *entity = get_ia32_am_sc(node);
623 return offset == 1 && entity == NULL;
626 static int is_am_minus_one(const ir_node *node)
628 int offset = get_ia32_am_offs_int(node);
629 ir_entity *entity = get_ia32_am_sc(node);
631 return offset == -1 && entity == NULL;
635 * Transforms a LEA into an Add or SHL if possible.
637 static void peephole_ia32_Lea(ir_node *node)
639 const arch_env_t *arch_env = cg->arch_env;
640 ir_graph *irg = current_ir_graph;
643 const arch_register_t *base_reg;
644 const arch_register_t *index_reg;
645 const arch_register_t *out_reg;
656 assert(is_ia32_Lea(node));
658 /* we can only do this if are allowed to globber the flags */
659 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
662 base = get_irn_n(node, n_ia32_Lea_base);
663 index = get_irn_n(node, n_ia32_Lea_index);
665 if(is_noreg(cg, base)) {
669 base_reg = arch_get_irn_register(arch_env, base);
671 if(is_noreg(cg, index)) {
675 index_reg = arch_get_irn_register(arch_env, index);
678 if(base == NULL && index == NULL) {
679 /* we shouldn't construct these in the first place... */
681 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
686 out_reg = arch_get_irn_register(arch_env, node);
687 scale = get_ia32_am_scale(node);
688 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
689 /* check if we have immediates values (frame entities should already be
690 * expressed in the offsets) */
691 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
697 /* we can transform leas where the out register is the same as either the
698 * base or index register back to an Add or Shl */
699 if(out_reg == base_reg) {
702 if(!has_immediates) {
703 ir_fprintf(stderr, "Optimisation warning: found lea which is "
708 goto make_add_immediate;
710 if(scale == 0 && !has_immediates) {
715 /* can't create an add */
717 } else if(out_reg == index_reg) {
719 if(has_immediates && scale == 0) {
721 goto make_add_immediate;
722 } else if(!has_immediates && scale > 0) {
724 op2 = create_immediate_from_int(cg, scale);
726 } else if(!has_immediates) {
728 ir_fprintf(stderr, "Optimisation warning: found lea which is "
732 } else if(scale == 0 && !has_immediates) {
737 /* can't create an add */
740 /* can't create an add */
745 if(ia32_cg_config.use_incdec) {
746 if(is_am_one(node)) {
747 dbgi = get_irn_dbg_info(node);
748 block = get_nodes_block(node);
749 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
750 arch_set_irn_register(arch_env, res, out_reg);
753 if(is_am_minus_one(node)) {
754 dbgi = get_irn_dbg_info(node);
755 block = get_nodes_block(node);
756 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
757 arch_set_irn_register(arch_env, res, out_reg);
761 op2 = create_immediate_from_am(cg, node);
764 dbgi = get_irn_dbg_info(node);
765 block = get_nodes_block(node);
766 noreg = ia32_new_NoReg_gp(cg);
768 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
769 arch_set_irn_register(arch_env, res, out_reg);
770 set_ia32_commutative(res);
774 dbgi = get_irn_dbg_info(node);
775 block = get_nodes_block(node);
776 noreg = ia32_new_NoReg_gp(cg);
778 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
779 arch_set_irn_register(arch_env, res, out_reg);
783 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
785 /* add new ADD/SHL to schedule */
786 DBG_OPT_LEA2ADD(node, res);
788 /* exchange the Add and the LEA */
789 be_peephole_before_exchange(node, res);
790 sched_add_before(node, res);
793 be_peephole_after_exchange(res);
797 * Register a peephole optimisation function.
799 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
800 assert(op->ops.generic == NULL);
801 op->ops.generic = (void*) func;
804 /* Perform peephole-optimizations. */
805 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
808 arch_env = cg->arch_env;
810 /* register peephole optimisations */
811 clear_irp_opcodes_generic_func();
812 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
813 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
814 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
815 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
816 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
817 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
819 be_peephole_opt(cg->birg);
823 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
824 * all it's Projs are removed as well.
825 * @param irn The irn to be removed from schedule
827 static INLINE void try_kill(ir_node *node)
829 if(get_irn_mode(node) == mode_T) {
830 const ir_edge_t *edge, *next;
831 foreach_out_edge_safe(node, edge, next) {
832 ir_node *proj = get_edge_src_irn(edge);
837 if(get_irn_n_edges(node) != 0)
840 if (sched_is_scheduled(node)) {
847 static void optimize_conv_store(ir_node *node)
854 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
857 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
858 pred_proj = get_irn_n(node, n_ia32_Store_val);
859 if(is_Proj(pred_proj)) {
860 pred = get_Proj_pred(pred_proj);
864 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
866 if(get_ia32_op_type(pred) != ia32_Normal)
869 /* the store only stores the lower bits, so we only need the conv
870 * it it shrinks the mode */
871 conv_mode = get_ia32_ls_mode(pred);
872 store_mode = get_ia32_ls_mode(node);
873 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
876 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
877 if(get_irn_n_edges(pred_proj) == 0) {
878 be_kill_node(pred_proj);
879 if(pred != pred_proj)
884 static void optimize_load_conv(ir_node *node)
886 ir_node *pred, *predpred;
890 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
893 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
894 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
898 predpred = get_Proj_pred(pred);
899 if(!is_ia32_Load(predpred))
902 /* the load is sign extending the upper bits, so we only need the conv
903 * if it shrinks the mode */
904 load_mode = get_ia32_ls_mode(predpred);
905 conv_mode = get_ia32_ls_mode(node);
906 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
909 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
910 /* change the load if it has only 1 user */
911 if(get_irn_n_edges(pred) == 1) {
913 if(get_mode_sign(conv_mode)) {
914 newmode = find_signed_mode(load_mode);
916 newmode = find_unsigned_mode(load_mode);
918 assert(newmode != NULL);
919 set_ia32_ls_mode(predpred, newmode);
921 /* otherwise we have to keep the conv */
927 exchange(node, pred);
930 static void optimize_conv_conv(ir_node *node)
932 ir_node *pred_proj, *pred, *result_conv;
933 ir_mode *pred_mode, *conv_mode;
937 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
940 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
941 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
942 if(is_Proj(pred_proj))
943 pred = get_Proj_pred(pred_proj);
947 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
950 /* we know that after a conv, the upper bits are sign extended
951 * so we only need the 2nd conv if it shrinks the mode */
952 conv_mode = get_ia32_ls_mode(node);
953 conv_mode_bits = get_mode_size_bits(conv_mode);
954 pred_mode = get_ia32_ls_mode(pred);
955 pred_mode_bits = get_mode_size_bits(pred_mode);
957 if(conv_mode_bits == pred_mode_bits
958 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
959 result_conv = pred_proj;
960 } else if(conv_mode_bits <= pred_mode_bits) {
961 /* if 2nd conv is smaller then first conv, then we can always take the
963 if(get_irn_n_edges(pred_proj) == 1) {
964 result_conv = pred_proj;
965 set_ia32_ls_mode(pred, conv_mode);
967 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
968 if (get_mode_size_bits(conv_mode) == 8) {
969 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
970 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
973 /* we don't want to end up with 2 loads, so we better do nothing */
974 if(get_irn_mode(pred) == mode_T) {
978 result_conv = exact_copy(pred);
979 set_ia32_ls_mode(result_conv, conv_mode);
981 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
982 if (get_mode_size_bits(conv_mode) == 8) {
983 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
984 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
988 /* if both convs have the same sign, then we can take the smaller one */
989 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
990 result_conv = pred_proj;
992 /* no optimisation possible if smaller conv is sign-extend */
993 if(mode_is_signed(pred_mode)) {
996 /* we can take the smaller conv if it is unsigned */
997 result_conv = pred_proj;
1002 exchange(node, result_conv);
1004 if(get_irn_n_edges(pred_proj) == 0) {
1005 be_kill_node(pred_proj);
1006 if(pred != pred_proj)
1009 optimize_conv_conv(result_conv);
1012 static void optimize_node(ir_node *node, void *env)
1016 optimize_load_conv(node);
1017 optimize_conv_store(node);
1018 optimize_conv_conv(node);
1022 * Performs conv and address mode optimization.
1024 void ia32_optimize_graph(ia32_code_gen_t *cg)
1026 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1029 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1032 void ia32_init_optimize(void)
1034 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");