3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universität Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
27 #include "../benode_t.h"
28 #include "../besched_t.h"
30 #include "ia32_new_nodes.h"
31 #include "bearch_ia32_t.h"
32 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
33 #include "ia32_transform.h"
34 #include "ia32_dbg_stat.h"
37 IA32_AM_CAND_NONE = 0,
38 IA32_AM_CAND_LEFT = 1,
39 IA32_AM_CAND_RIGHT = 2,
44 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
46 typedef int is_op_func_t(const ir_node *n);
49 * checks if a node represents the NOREG value
51 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
52 be_abi_irg_t *babi = cg->birg->abi;
53 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
54 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
56 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
57 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
62 /*************************************************
65 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
66 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
67 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
68 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
70 *************************************************/
73 * creates a unique ident by adding a number to a tag
75 * @param tag the tag string, must contain a %d if a number
78 static ident *unique_id(const char *tag)
80 static unsigned id = 0;
83 snprintf(str, sizeof(str), tag, ++id);
84 return new_id_from_str(str);
90 * Transforms a SymConst.
92 * @param mod the debug module
93 * @param block the block the new node should belong to
94 * @param node the ir SymConst node
95 * @param mode mode of the SymConst
96 * @return the created ia32 Const node
98 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
100 dbg_info *dbg = env->dbg;
101 ir_mode *mode = env->mode;
102 ir_graph *irg = env->irg;
103 ir_node *block = env->block;
105 if (mode_is_float(mode)) {
107 if (USE_SSE2(env->cg))
108 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
110 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
113 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
115 set_ia32_Const_attr(cnst, env->irn);
121 * Get a primitive type for a mode.
123 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
125 pmap_entry *e = pmap_find(types, mode);
130 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
131 res = new_type_primitive(new_id_from_str(buf), mode);
132 pmap_insert(types, mode, res);
140 * Get an entity that is initialized with a tarval
142 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
144 tarval *tv = get_Const_tarval(cnst);
145 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
150 ir_mode *mode = get_irn_mode(cnst);
151 ir_type *tp = get_Const_type(cnst);
152 if (tp == firm_unknown_type)
153 tp = get_prim_type(cg->isa->types, mode);
155 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
157 set_entity_ld_ident(res, get_entity_ident(res));
158 set_entity_visibility(res, visibility_local);
159 set_entity_variability(res, variability_constant);
160 set_entity_allocation(res, allocation_static);
162 /* we create a new entity here: It's initialization must resist on the
164 rem = current_ir_graph;
165 current_ir_graph = get_const_code_irg();
166 set_atomic_ent_value(res, new_Const_type(tv, tp));
167 current_ir_graph = rem;
169 pmap_insert(cg->isa->tv_ent, tv, res);
177 * Transforms a Const.
179 * @param mod the debug module
180 * @param block the block the new node should belong to
181 * @param node the ir Const node
182 * @param mode mode of the Const
183 * @return the created ia32 Const node
185 static ir_node *gen_Const(ia32_transform_env_t *env) {
188 ir_graph *irg = env->irg;
189 ir_node *block = env->block;
190 ir_node *node = env->irn;
191 dbg_info *dbg = env->dbg;
192 ir_mode *mode = env->mode;
194 if (mode_is_float(mode)) {
196 if (! USE_SSE2(env->cg)) {
197 cnst_classify_t clss = classify_Const(node);
199 if (clss == CNST_NULL)
200 return new_rd_ia32_vfldz(dbg, irg, block, mode);
201 else if (clss == CNST_ONE)
202 return new_rd_ia32_vfld1(dbg, irg, block, mode);
204 sym.entity_p = get_entity_for_tv(env->cg, node);
206 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
208 cnst = gen_SymConst(env);
211 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
212 set_ia32_Const_attr(cnst, node);
220 * Transforms (all) Const's into ia32_Const and places them in the
221 * block where they are used (or in the cfg-pred Block in case of Phi's).
222 * Additionally all reference nodes are changed into mode_Is nodes.
224 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
225 ia32_code_gen_t *cg = env;
226 ia32_transform_env_t tenv;
228 ir_node *pred, *cnst;
235 mode = get_irn_mode(irn);
237 /* transform all reference nodes into mode_Is nodes */
238 if (mode_is_reference(mode)) {
240 set_irn_mode(irn, mode);
244 Annotate mode of stored value to link field of the Store
245 as floating point converts might be optimized and we would
248 if (get_irn_opcode(irn) == iro_Store) {
249 set_irn_link(irn, get_irn_mode(get_Store_value(irn)));
252 tenv.block = get_nodes_block(irn);
255 DEBUG_ONLY(tenv.mod = cg->mod;)
257 /* Loop over all predecessors and check for Sym/Const nodes */
258 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
259 pred = get_irn_n(irn, i);
261 opc = get_irn_opcode(pred);
263 tenv.mode = get_irn_mode(pred);
264 tenv.dbg = get_irn_dbg_info(pred);
266 /* If it's a Phi, then we need to create the */
267 /* new Const in it's predecessor block */
269 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
272 /* put the const into the block where the original const was */
273 if (! (cg->opt & IA32_OPT_PLACECNST)) {
274 tenv.block = get_nodes_block(pred);
279 cnst = gen_Const(&tenv);
282 cnst = gen_SymConst(&tenv);
288 /* if we found a const, then set it */
290 set_irn_n(irn, i, cnst);
297 /********************************************************************************************************
298 * _____ _ _ ____ _ _ _ _ _
299 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
300 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
301 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
302 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
303 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
306 ********************************************************************************************************/
309 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
312 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
313 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
317 * Checks for potential CJmp/CJmpAM optimization candidates.
319 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
320 ir_node *cand = NULL;
321 ir_node *prev = sched_prev(irn);
323 if (is_Block(prev)) {
324 if (get_Block_n_cfgpreds(prev) == 1)
325 prev = get_Block_cfgpred(prev, 0);
330 /* The predecessor must be a ProjX. */
331 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
332 prev = get_Proj_pred(prev);
334 if (is_op_func(prev))
341 static int is_TestJmp_cand(const ir_node *irn) {
342 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
346 * Checks if two consecutive arguments of cand matches
347 * the two arguments of irn (TestJmp).
349 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
350 ir_node *in1 = get_irn_n(irn, 0);
351 ir_node *in2 = get_irn_n(irn, 1);
352 int i, n = get_irn_arity(cand);
355 for (i = 0; i < n - 1; i++) {
356 if (get_irn_n(cand, i) == in1 &&
357 get_irn_n(cand, i + 1) == in2)
365 return ia32_cnst_compare(cand, irn);
371 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
373 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
374 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
377 /* we found a possible candidate */
378 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
381 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
383 if (is_ia32_And(cand))
384 set_irn_op(irn, op_ia32_CJmpAM);
386 set_irn_op(irn, op_ia32_CJmp);
388 DB((cg->mod, LEVEL_1, "%+F\n", irn));
392 static int is_CondJmp_cand(const ir_node *irn) {
393 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
397 * Checks if the arguments of cand are the same of irn.
399 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
400 int i, n = get_irn_arity(cand);
403 for (i = 0; i < n; i++) {
404 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
411 return ia32_cnst_compare(cand, irn);
417 * Tries to replace a CondJmp by a CJmpAM
419 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
420 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
423 /* we found a possible candidate */
424 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
427 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
430 set_irn_op(irn, op_ia32_CJmpAM);
432 DB((cg->mod, LEVEL_1, "%+F\n", irn));
437 * Creates a Push from Store(IncSP(gp_reg_size))
439 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
440 ir_node *sp = get_irn_n(irn, 0);
441 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
442 const ir_edge_t *edge;
445 /* do not create push if store has already an offset assigned or base is not a IncSP */
446 if (get_ia32_am_offs(irn) || ! be_is_IncSP(sp))
449 /* do not create push if index is not NOREG */
450 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
451 &ia32_gp_regs[REG_GP_NOREG])
454 /* do not create push for floating point */
455 val = get_irn_n(irn, 2);
456 if (mode_is_float(get_irn_mode(val)))
459 /* do not create push if IncSp doesn't expand stack or expand size is different from register size */
460 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
461 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
464 /* do not create push, if there is a path (inside the block) from the push value to IncSP */
465 h = heights_new(cg->irg);
466 if (get_nodes_block(val) == get_nodes_block(sp) &&
467 heights_reachable_in_block(h, val, sp))
474 /* ok, translate into Push */
475 edge = get_irn_out_edge_first(irn);
476 old_proj_M = get_edge_src_irn(edge);
478 next = sched_next(irn);
482 bl = get_nodes_block(irn);
483 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
484 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
485 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
486 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
488 /* copy a possible constant from the store */
489 set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
490 set_ia32_immop_type(push, get_ia32_immop_type(irn));
492 /* the push must have SP out register */
493 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
495 exchange(old_proj_M, proj_M);
496 exchange(sp, proj_res);
497 sched_add_before(next, push);
498 sched_add_after(push, proj_res);
502 * Creates a Pop from IncSP(Load(sp))
504 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
505 ir_node *old_proj_M = be_get_IncSP_mem(irn);
506 ir_node *load = skip_Proj(old_proj_M);
507 ir_node *old_proj_res = NULL;
508 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
509 const ir_edge_t *edge;
510 const arch_register_t *reg, *sp;
512 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
515 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
516 &ia32_gp_regs[REG_GP_NOREG])
518 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
521 /* ok, translate into pop */
522 foreach_out_edge(load, edge) {
523 ir_node *succ = get_edge_src_irn(edge);
524 if (succ != old_proj_M) {
529 if (! old_proj_res) {
531 return; /* should not happen */
534 bl = get_nodes_block(load);
536 /* IncSP is typically scheduled after the load, so remove it first */
538 next = sched_next(old_proj_res);
539 sched_remove(old_proj_res);
542 reg = arch_get_irn_register(cg->arch_env, load);
543 sp = arch_get_irn_register(cg->arch_env, irn);
545 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
546 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
547 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
548 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
550 exchange(old_proj_M, proj_M);
551 exchange(old_proj_res, proj_res);
552 exchange(irn, proj_sp);
554 arch_set_irn_register(cg->arch_env, proj_res, reg);
555 arch_set_irn_register(cg->arch_env, proj_sp, sp);
557 sched_add_before(next, proj_sp);
558 sched_add_before(proj_sp, proj_res);
559 sched_add_before(proj_res,pop);
563 * Tries to optimize two following IncSP.
565 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
566 ir_node *prev = be_get_IncSP_pred(irn);
567 int real_uses = get_irn_n_edges(prev);
569 if (be_is_IncSP(prev) && real_uses == 1) {
570 /* first IncSP has only one IncSP user, kill the first one */
571 unsigned prev_offs = be_get_IncSP_offset(prev);
572 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
573 unsigned curr_offs = be_get_IncSP_offset(irn);
574 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
576 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
577 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
581 curr_dir = be_stack_dir_expand;
584 curr_dir = be_stack_dir_shrink;
585 be_set_IncSP_offset(prev, 0);
586 be_set_IncSP_offset(irn, (unsigned)new_ofs);
587 be_set_IncSP_direction(irn, curr_dir);
589 /* Omit the optimized IncSP */
590 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
595 * Performs Peephole Optimizations.
597 void ia32_peephole_optimization(ir_node *irn, void *env) {
598 ia32_code_gen_t *cg = env;
600 if (is_ia32_TestJmp(irn))
601 ia32_optimize_TestJmp(irn, cg);
602 else if (is_ia32_CondJmp(irn))
603 ia32_optimize_CondJmp(irn, cg);
604 /* seems to be buggy when using Pushes */
605 // else if (be_is_IncSP(irn))
606 // ia32_optimize_IncSP(irn, cg);
607 else if (is_ia32_Store(irn))
608 ia32_create_Push(irn, cg);
613 /******************************************************************
615 * /\ | | | | | \/ | | |
616 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
617 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
618 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
619 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
621 ******************************************************************/
628 static int node_is_ia32_comm(const ir_node *irn) {
629 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
632 static int ia32_get_irn_n_edges(const ir_node *irn) {
633 const ir_edge_t *edge;
636 foreach_out_edge(irn, edge) {
644 * Returns the first mode_M Proj connected to irn.
646 static ir_node *get_mem_proj(const ir_node *irn) {
647 const ir_edge_t *edge;
650 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
652 foreach_out_edge(irn, edge) {
653 src = get_edge_src_irn(edge);
655 assert(is_Proj(src) && "Proj expected");
657 if (get_irn_mode(src) == mode_M)
665 * Returns the first Proj with mode != mode_M connected to irn.
667 static ir_node *get_res_proj(const ir_node *irn) {
668 const ir_edge_t *edge;
671 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
673 foreach_out_edge(irn, edge) {
674 src = get_edge_src_irn(edge);
676 assert(is_Proj(src) && "Proj expected");
678 if (get_irn_mode(src) != mode_M)
686 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
688 * @param pred The node to be checked
689 * @param is_op_func The check-function
690 * @return 1 if conditions are fulfilled, 0 otherwise
692 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
693 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
701 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
702 * and if the predecessor is in block bl.
704 * @param bl The block
705 * @param pred The node to be checked
706 * @param is_op_func The check-function
707 * @return 1 if conditions are fulfilled, 0 otherwise
709 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
710 int (*is_op_func)(const ir_node *n))
713 pred = get_Proj_pred(pred);
714 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
723 * Checks if irn is a candidate for address calculation.
725 * - none of the operand must be a Load within the same block OR
726 * - all Loads must have more than one user OR
727 * - the irn has a frame entity (it's a former FrameAddr)
729 * @param block The block the Loads must/mustnot be in
730 * @param irn The irn to check
731 * return 1 if irn is a candidate, 0 otherwise
733 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
734 ir_node *in, *left, *right;
737 left = get_irn_n(irn, 2);
738 right = get_irn_n(irn, 3);
742 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
743 n = ia32_get_irn_n_edges(in);
744 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
749 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
750 n = ia32_get_irn_n_edges(in);
751 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
754 is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
760 * Checks if irn is a candidate for address mode.
763 * - at least one operand has to be a Load within the same block AND
764 * - the load must not have other users than the irn AND
765 * - the irn must not have a frame entity set
767 * @param cg The ia32 code generator
768 * @param h The height information of the irg
769 * @param block The block the Loads must/mustnot be in
770 * @param irn The irn to check
771 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
773 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
774 ir_node *in, *load, *other, *left, *right;
775 int n, is_cand = 0, cand;
777 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn))
780 left = get_irn_n(irn, 2);
781 right = get_irn_n(irn, 3);
785 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
786 n = ia32_get_irn_n_edges(in);
787 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
789 load = get_Proj_pred(in);
792 /* If there is a data dependency of other irn from load: cannot use AM */
793 if (get_nodes_block(other) == block) {
794 other = skip_Proj(other);
795 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
799 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
803 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
804 n = ia32_get_irn_n_edges(in);
805 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
807 load = get_Proj_pred(in);
810 /* If there is a data dependency of other irn from load: cannot use load */
811 if (get_nodes_block(other) == block) {
812 other = skip_Proj(other);
813 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
817 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
819 /* check some special cases */
820 if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
821 /* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
822 if (get_mode_size_bits(get_ia32_tgt_mode(irn)) != 32)
823 cand = IA32_AM_CAND_NONE;
825 else if (is_ia32_Conv_I2I(irn)) {
826 /* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
827 if (get_mode_size_bits(get_ia32_src_mode(irn)) > get_mode_size_bits(get_ia32_tgt_mode(irn)))
828 cand = IA32_AM_CAND_NONE;
831 /* if the irn has a frame entity: we do not use address mode */
832 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
836 * Compares the base and index addr and the load/store entities
837 * and returns 1 if they are equal.
839 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
840 const ir_node *addr_b, const ir_node *addr_i)
842 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
843 entity *lent = get_ia32_frame_ent(load);
844 entity *sent = get_ia32_frame_ent(store);
845 ident *lid = get_ia32_am_sc(load);
846 ident *sid = get_ia32_am_sc(store);
847 char *loffs = get_ia32_am_offs(load);
848 char *soffs = get_ia32_am_offs(store);
850 /* are both entities set and equal? */
851 if (is_equal && (lent || sent))
852 is_equal = lent && sent && (lent == sent);
854 /* are address mode idents set and equal? */
855 if (is_equal && (lid || sid))
856 is_equal = lid && sid && (lid == sid);
858 /* are offsets set and equal */
859 if (is_equal && (loffs || soffs))
860 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
862 /* are the load and the store of the same mode? */
863 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
868 typedef enum _ia32_take_lea_attr {
869 IA32_LEA_ATTR_NONE = 0,
870 IA32_LEA_ATTR_BASE = (1 << 0),
871 IA32_LEA_ATTR_INDEX = (1 << 1),
872 IA32_LEA_ATTR_OFFS = (1 << 2),
873 IA32_LEA_ATTR_SCALE = (1 << 3),
874 IA32_LEA_ATTR_AMSC = (1 << 4),
875 IA32_LEA_ATTR_FENT = (1 << 5)
876 } ia32_take_lea_attr;
879 * Decides if we have to keep the LEA operand or if we can assimilate it.
881 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
882 int have_am_sc, ia32_code_gen_t *cg)
884 ir_node *lea_base = get_irn_n(lea, 0);
885 ir_node *lea_idx = get_irn_n(lea, 1);
886 entity *irn_ent = get_ia32_frame_ent(irn);
887 entity *lea_ent = get_ia32_frame_ent(lea);
889 int is_noreg_base = be_is_NoReg(cg, base);
890 int is_noreg_index = be_is_NoReg(cg, index);
891 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
893 /* If the Add and the LEA both have a different frame entity set: keep */
894 if (irn_ent && lea_ent && (irn_ent != lea_ent))
895 return IA32_LEA_ATTR_NONE;
896 else if (! irn_ent && lea_ent)
897 ret_val |= IA32_LEA_ATTR_FENT;
899 /* If the Add and the LEA both have already an address mode symconst: keep */
900 if (have_am_sc && get_ia32_am_sc(lea))
901 return IA32_LEA_ATTR_NONE;
902 else if (get_ia32_am_sc(lea))
903 ret_val |= IA32_LEA_ATTR_AMSC;
905 /* Check the different base-index combinations */
907 if (! is_noreg_base && ! is_noreg_index) {
908 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
909 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
910 if (am_flav & ia32_O)
911 ret_val |= IA32_LEA_ATTR_OFFS;
913 ret_val |= IA32_LEA_ATTR_BASE;
916 return IA32_LEA_ATTR_NONE;
918 else if (! is_noreg_base && is_noreg_index) {
919 /* Base is set but index not */
921 /* Base points to LEA: assimilate everything */
922 if (am_flav & ia32_O)
923 ret_val |= IA32_LEA_ATTR_OFFS;
924 if (am_flav & ia32_S)
925 ret_val |= IA32_LEA_ATTR_SCALE;
926 if (am_flav & ia32_I)
927 ret_val |= IA32_LEA_ATTR_INDEX;
929 ret_val |= IA32_LEA_ATTR_BASE;
931 else if (am_flav & ia32_B ? 0 : 1) {
932 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
933 if (am_flav & ia32_O)
934 ret_val |= IA32_LEA_ATTR_OFFS;
935 if (am_flav & ia32_S)
936 ret_val |= IA32_LEA_ATTR_SCALE;
938 ret_val |= IA32_LEA_ATTR_INDEX;
941 return IA32_LEA_ATTR_NONE;
943 else if (is_noreg_base && ! is_noreg_index) {
944 /* Index is set but not base */
946 /* Index points to LEA: assimilate everything */
947 if (am_flav & ia32_O)
948 ret_val |= IA32_LEA_ATTR_OFFS;
949 if (am_flav & ia32_S)
950 ret_val |= IA32_LEA_ATTR_SCALE;
951 if (am_flav & ia32_B)
952 ret_val |= IA32_LEA_ATTR_BASE;
954 ret_val |= IA32_LEA_ATTR_INDEX;
956 else if (am_flav & ia32_I ? 0 : 1) {
957 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
958 if (am_flav & ia32_O)
959 ret_val |= IA32_LEA_ATTR_OFFS;
960 if (am_flav & ia32_S)
961 ret_val |= IA32_LEA_ATTR_SCALE;
963 ret_val |= IA32_LEA_ATTR_BASE;
966 return IA32_LEA_ATTR_NONE;
969 assert(0 && "There must have been set base or index");
977 * Folds Add or Sub to LEA if possible
979 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
980 ir_graph *irg = get_irn_irg(irn);
981 dbg_info *dbg = get_irn_dbg_info(irn);
982 ir_node *block = get_nodes_block(irn);
984 ir_node *shift = NULL;
985 ir_node *lea_o = NULL;
988 const char *offs_cnst = NULL;
989 char *offs_lea = NULL;
996 entity *lea_ent = NULL;
997 ir_node *left, *right, *temp;
998 ir_node *base, *index;
999 ia32_am_flavour_t am_flav;
1000 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1002 if (is_ia32_Add(irn))
1005 left = get_irn_n(irn, 2);
1006 right = get_irn_n(irn, 3);
1008 /* "normalize" arguments in case of add with two operands */
1009 if (isadd && ! be_is_NoReg(cg, right)) {
1010 /* put LEA == ia32_am_O as right operand */
1011 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
1012 set_irn_n(irn, 2, right);
1013 set_irn_n(irn, 3, left);
1019 /* put LEA != ia32_am_O as left operand */
1020 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
1021 set_irn_n(irn, 2, right);
1022 set_irn_n(irn, 3, left);
1028 /* put SHL as left operand iff left is NOT a LEA */
1029 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
1030 set_irn_n(irn, 2, right);
1031 set_irn_n(irn, 3, left);
1044 /* check for operation with immediate */
1045 if (is_ia32_ImmConst(irn)) {
1046 DBG((mod, LEVEL_1, "\tfound op with imm const"));
1048 offs_cnst = get_ia32_cnst(irn);
1051 else if (is_ia32_ImmSymConst(irn)) {
1052 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
1056 am_sc = get_ia32_id_cnst(irn);
1057 am_sc_sign = is_ia32_am_sc_sign(irn);
1060 /* determine the operand which needs to be checked */
1061 temp = be_is_NoReg(cg, right) ? left : right;
1063 /* check if right operand is AMConst (LEA with ia32_am_O) */
1064 /* but we can only eat it up if there is no other symconst */
1065 /* because the linker won't accept two symconsts */
1066 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
1067 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
1069 offs_lea = get_ia32_am_offs(temp);
1070 am_sc = get_ia32_am_sc(temp);
1071 am_sc_sign = is_ia32_am_sc_sign(temp);
1081 /* default for add -> make right operand to index */
1085 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
1087 /* determine the operand which needs to be checked */
1089 if (is_ia32_Lea(left)) {
1093 /* check for SHL 1,2,3 */
1094 if (pred_is_specific_node(temp, is_ia32_Shl)) {
1095 temp = get_Proj_pred(temp);
1098 if (get_ia32_Immop_tarval(temp)) {
1099 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
1102 index = get_irn_n(temp, 2);
1104 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
1114 if (! be_is_NoReg(cg, index)) {
1115 /* if we have index, but left == right -> no base */
1116 if (left == right) {
1119 else if (! is_ia32_Lea(left) && (index != right)) {
1120 /* index != right -> we found a good Shl */
1121 /* left != LEA -> this Shl was the left operand */
1122 /* -> base is right operand */
1123 base = (right == lea_o) ? noreg : right;
1128 /* Try to assimilate a LEA as left operand */
1129 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1130 /* check if we can assimilate the LEA */
1131 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1133 if (take_attr == IA32_LEA_ATTR_NONE) {
1134 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1137 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1138 lea = left; /* for statistics */
1140 if (take_attr & IA32_LEA_ATTR_OFFS)
1141 offs = get_ia32_am_offs(left);
1143 if (take_attr & IA32_LEA_ATTR_AMSC) {
1144 am_sc = get_ia32_am_sc(left);
1146 am_sc_sign = is_ia32_am_sc_sign(left);
1149 if (take_attr & IA32_LEA_ATTR_SCALE)
1150 scale = get_ia32_am_scale(left);
1152 if (take_attr & IA32_LEA_ATTR_BASE)
1153 base = get_irn_n(left, 0);
1155 if (take_attr & IA32_LEA_ATTR_INDEX)
1156 index = get_irn_n(left, 1);
1158 if (take_attr & IA32_LEA_ATTR_FENT)
1159 lea_ent = get_ia32_frame_ent(left);
1163 /* ok, we can create a new LEA */
1165 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1167 /* add the old offset of a previous LEA */
1169 add_ia32_am_offs(res, offs);
1172 /* add the new offset */
1175 add_ia32_am_offs(res, offs_cnst);
1178 add_ia32_am_offs(res, offs_lea);
1182 /* either lea_O-cnst, -cnst or -lea_O */
1185 add_ia32_am_offs(res, offs_lea);
1188 sub_ia32_am_offs(res, offs_cnst);
1191 sub_ia32_am_offs(res, offs_lea);
1195 /* set the address mode symconst */
1197 set_ia32_am_sc(res, am_sc);
1199 set_ia32_am_sc_sign(res);
1202 /* copy the frame entity (could be set in case of Add */
1203 /* which was a FrameAddr) */
1205 set_ia32_frame_ent(res, lea_ent);
1207 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1209 if (get_ia32_frame_ent(res))
1210 set_ia32_use_frame(res);
1213 set_ia32_am_scale(res, scale);
1215 am_flav = ia32_am_N;
1216 /* determine new am flavour */
1217 if (offs || offs_cnst || offs_lea || have_am_sc) {
1220 if (! be_is_NoReg(cg, base)) {
1223 if (! be_is_NoReg(cg, index)) {
1229 set_ia32_am_flavour(res, am_flav);
1231 set_ia32_op_type(res, ia32_AddrModeS);
1233 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1235 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1237 /* we will exchange it, report here before the Proj is created */
1238 if (shift && lea && lea_o)
1239 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1240 else if (shift && lea)
1241 DBG_OPT_LEA3(irn, lea, shift, res);
1242 else if (shift && lea_o)
1243 DBG_OPT_LEA3(irn, lea_o, shift, res);
1244 else if (lea && lea_o)
1245 DBG_OPT_LEA3(irn, lea_o, lea, res);
1247 DBG_OPT_LEA2(irn, shift, res);
1249 DBG_OPT_LEA2(irn, lea, res);
1251 DBG_OPT_LEA2(irn, lea_o, res);
1253 DBG_OPT_LEA1(irn, res);
1255 /* get the result Proj of the Add/Sub */
1256 irn = get_res_proj(irn);
1258 assert(irn && "Couldn't find result proj");
1260 /* exchange the old op with the new LEA */
1269 * Merges a Load/Store node with a LEA.
1270 * @param irn The Load/Store node
1271 * @param lea The LEA
1273 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1274 entity *irn_ent = get_ia32_frame_ent(irn);
1275 entity *lea_ent = get_ia32_frame_ent(lea);
1277 /* If the irn and the LEA both have a different frame entity set: do not merge */
1278 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1280 else if (! irn_ent && lea_ent) {
1281 set_ia32_frame_ent(irn, lea_ent);
1282 set_ia32_use_frame(irn);
1285 /* get the AM attributes from the LEA */
1286 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1287 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1288 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1290 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1291 if (is_ia32_am_sc_sign(lea))
1292 set_ia32_am_sc_sign(irn);
1294 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1296 /* set base and index */
1297 set_irn_n(irn, 0, get_irn_n(lea, 0));
1298 set_irn_n(irn, 1, get_irn_n(lea, 1));
1300 /* clear remat flag */
1301 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1303 if (is_ia32_Ld(irn))
1304 DBG_OPT_LOAD_LEA(lea, irn);
1306 DBG_OPT_STORE_LEA(lea, irn);
1311 * Sets new_right index of irn to right and new_left index to left.
1312 * Also exchange left and right
1314 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1317 set_irn_n(irn, new_right, *right);
1318 set_irn_n(irn, new_left, *left);
1324 /* this is only needed for Compares, but currently ALL nodes
1325 * have this attribute :-) */
1326 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1330 * Performs address calculation optimization (create LEAs if possible)
1332 static void optimize_lea(ir_node *irn, void *env) {
1333 ia32_code_gen_t *cg = env;
1334 ir_node *block, *noreg_gp, *left, *right;
1336 if (! is_ia32_irn(irn))
1339 /* Following cases can occur: */
1340 /* - Sub (l, imm) -> LEA [base - offset] */
1341 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1342 /* - Add (l, imm) -> LEA [base + offset] */
1343 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1344 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1345 /* - Add (l, r) -> LEA [base + index * scale] */
1346 /* with scale > 1 iff l/r == shl (1,2,3) */
1348 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1349 left = get_irn_n(irn, 2);
1350 right = get_irn_n(irn, 3);
1351 block = get_nodes_block(irn);
1352 noreg_gp = ia32_new_NoReg_gp(cg);
1354 /* Do not try to create a LEA if one of the operands is a Load. */
1355 /* check is irn is a candidate for address calculation */
1356 if (is_addr_candidate(block, irn)) {
1359 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1360 res = fold_addr(cg, irn, noreg_gp);
1363 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1365 DB((cg->mod, LEVEL_1, "not transformed\n"));
1368 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1369 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1370 /* - Store -> LEA into Store } it might be better to keep the LEA */
1371 left = get_irn_n(irn, 0);
1373 if (is_ia32_Lea(left)) {
1374 const ir_edge_t *edge, *ne;
1377 /* merge all Loads/Stores connected to this LEA with the LEA */
1378 foreach_out_edge_safe(left, edge, ne) {
1379 src = get_edge_src_irn(edge);
1381 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1382 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1383 if (! is_ia32_got_lea(src))
1384 merge_loadstore_lea(src, left);
1385 set_ia32_got_lea(src);
1394 * Checks for address mode patterns and performs the
1395 * necessary transformations.
1396 * This function is called by a walker.
1398 static void optimize_am(ir_node *irn, void *env) {
1399 ia32_am_opt_env_t *am_opt_env = env;
1400 ia32_code_gen_t *cg = am_opt_env->cg;
1401 heights_t *h = am_opt_env->h;
1402 ir_node *block, *noreg_gp, *noreg_fp;
1403 ir_node *left, *right;
1404 ir_node *store, *load, *mem_proj;
1405 ir_node *succ, *addr_b, *addr_i;
1406 int check_am_src = 0;
1407 int need_exchange_on_fail = 0;
1408 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1410 if (! is_ia32_irn(irn))
1413 block = get_nodes_block(irn);
1414 noreg_gp = ia32_new_NoReg_gp(cg);
1415 noreg_fp = ia32_new_NoReg_fp(cg);
1417 DBG((mod, LEVEL_1, "checking for AM\n"));
1419 /* fold following patterns: */
1420 /* - op -> Load into AMop with am_Source */
1422 /* - op is am_Source capable AND */
1423 /* - the Load is only used by this op AND */
1424 /* - the Load is in the same block */
1425 /* - Store -> op -> Load into AMop with am_Dest */
1427 /* - op is am_Dest capable AND */
1428 /* - the Store uses the same address as the Load AND */
1429 /* - the Load is only used by this op AND */
1430 /* - the Load and Store are in the same block AND */
1431 /* - nobody else uses the result of the op */
1433 if ((get_ia32_am_support(irn) != ia32_am_None) && ! is_ia32_Lea(irn)) {
1434 ia32_am_cand_t cand = is_am_candidate(cg, h, block, irn);
1435 ia32_am_cand_t orig_cand = cand;
1437 /* cand == 1: load is left; cand == 2: load is right; */
1439 if (cand == IA32_AM_CAND_NONE)
1442 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1444 left = get_irn_n(irn, 2);
1445 if (get_irn_arity(irn) == 4) {
1446 /* it's an "unary" operation */
1450 right = get_irn_n(irn, 3);
1453 /* normalize commutative ops */
1454 if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_LEFT)) {
1456 /* Assure that right operand is always a Load if there is one */
1457 /* because non-commutative ops can only use Dest AM if the right */
1458 /* operand is a load, so we only need to check right operand. */
1460 exchange_left_right(irn, &left, &right, 3, 2);
1461 need_exchange_on_fail = 1;
1463 /* now: load is right */
1464 cand = IA32_AM_CAND_RIGHT;
1467 /* check for Store -> op -> Load */
1469 /* Store -> op -> Load optimization is only possible if supported by op */
1470 /* and if right operand is a Load */
1471 if ((get_ia32_am_support(irn) & ia32_am_Dest) && (cand & IA32_AM_CAND_RIGHT))
1473 /* An address mode capable op always has a result Proj. */
1474 /* If this Proj is used by more than one other node, we don't need to */
1475 /* check further, otherwise we check for Store and remember the address, */
1476 /* the Store points to. */
1478 succ = get_res_proj(irn);
1479 assert(succ && "Couldn't find result proj");
1485 /* now check for users and Store */
1486 if (ia32_get_irn_n_edges(succ) == 1) {
1487 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1489 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1491 addr_b = get_irn_n(store, 0);
1492 addr_i = get_irn_n(store, 1);
1497 /* we found a Store as single user: Now check for Load */
1499 /* Extra check for commutative ops with two Loads */
1500 /* -> put the interesting Load right */
1501 if (node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_BOTH)) {
1502 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1503 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1505 /* We exchange left and right, so it's easier to kill */
1506 /* the correct Load later and to handle unary operations. */
1507 exchange_left_right(irn, &left, &right, 3, 2);
1508 need_exchange_on_fail ^= 1;
1512 /* skip the Proj for easier access */
1513 load = get_Proj_pred(right);
1515 /* Compare Load and Store address */
1516 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1517 /* Right Load is from same address, so we can */
1518 /* disconnect the Load and Store here */
1520 /* set new base, index and attributes */
1521 set_irn_n(irn, 0, addr_b);
1522 set_irn_n(irn, 1, addr_i);
1523 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1524 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1525 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1526 set_ia32_op_type(irn, ia32_AddrModeD);
1527 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1528 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1530 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1531 if (is_ia32_am_sc_sign(load))
1532 set_ia32_am_sc_sign(irn);
1534 if (is_ia32_use_frame(load))
1535 set_ia32_use_frame(irn);
1537 /* connect to Load memory and disconnect Load */
1538 if (get_irn_arity(irn) == 5) {
1540 set_irn_n(irn, 4, get_irn_n(load, 2));
1541 set_irn_n(irn, 3, noreg_gp);
1545 set_irn_n(irn, 3, get_irn_n(load, 2));
1546 set_irn_n(irn, 2, noreg_gp);
1549 /* connect the memory Proj of the Store to the op */
1550 mem_proj = get_mem_proj(store);
1551 set_Proj_pred(mem_proj, irn);
1552 set_Proj_proj(mem_proj, 1);
1554 /* clear remat flag */
1555 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1557 DBG_OPT_AM_D(load, store, irn);
1559 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1561 need_exchange_on_fail = 0;
1564 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1565 /* There was no store, check if we still can optimize for source address mode */
1568 } /* if (support AM Dest) */
1569 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1570 /* op doesn't support am AM Dest -> check for AM Source */
1574 /* was exchanged but optimize failed: exchange back */
1575 if (need_exchange_on_fail) {
1576 exchange_left_right(irn, &left, &right, 3, 2);
1580 need_exchange_on_fail = 0;
1582 /* normalize commutative ops */
1583 if (check_am_src && node_is_ia32_comm(irn) && (cand == IA32_AM_CAND_RIGHT)) {
1585 /* Assure that left operand is always a Load if there is one */
1586 /* because non-commutative ops can only use Source AM if the */
1587 /* left operand is a Load, so we only need to check the left */
1588 /* operand afterwards. */
1590 exchange_left_right(irn, &left, &right, 3, 2);
1591 need_exchange_on_fail = 1;
1593 /* now: load is left */
1594 cand = IA32_AM_CAND_LEFT;
1597 /* optimize op -> Load iff Load is only used by this op */
1598 /* and left operand is a Load which only used by this irn */
1600 (cand & IA32_AM_CAND_LEFT) &&
1601 (ia32_get_irn_n_edges(left) == 1))
1603 left = get_Proj_pred(left);
1605 addr_b = get_irn_n(left, 0);
1606 addr_i = get_irn_n(left, 1);
1608 /* set new base, index and attributes */
1609 set_irn_n(irn, 0, addr_b);
1610 set_irn_n(irn, 1, addr_i);
1611 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1612 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1613 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1614 set_ia32_op_type(irn, ia32_AddrModeS);
1615 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1616 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1618 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1619 if (is_ia32_am_sc_sign(left))
1620 set_ia32_am_sc_sign(irn);
1622 /* clear remat flag */
1623 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1625 if (is_ia32_use_frame(left))
1626 set_ia32_use_frame(irn);
1628 /* connect to Load memory */
1629 if (get_irn_arity(irn) == 5) {
1631 set_irn_n(irn, 4, get_irn_n(left, 2));
1633 /* this is only needed for Compares, but currently ALL nodes
1634 * have this attribute :-) */
1635 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1637 /* disconnect from Load */
1638 /* (make second op -> first, set second in to noreg) */
1639 set_irn_n(irn, 2, get_irn_n(irn, 3));
1640 set_irn_n(irn, 3, noreg_gp);
1644 set_irn_n(irn, 3, get_irn_n(left, 2));
1646 /* disconnect from Load */
1647 set_irn_n(irn, 2, noreg_gp);
1650 DBG_OPT_AM_S(left, irn);
1652 /* If Load has a memory Proj, connect it to the op */
1653 mem_proj = get_mem_proj(left);
1655 set_Proj_pred(mem_proj, irn);
1656 set_Proj_proj(mem_proj, 1);
1659 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
1662 /* was exchanged but optimize failed: exchange back */
1663 if (need_exchange_on_fail)
1664 exchange_left_right(irn, &left, &right, 3, 2);
1670 * Performs address mode optimization.
1672 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1673 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1674 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1675 edges_deactivate(cg->irg);
1676 edges_activate(cg->irg);
1679 /* no optimizations at all */
1683 /* beware: we cannot optimize LEA and AM in one run because */
1684 /* LEA optimization adds new nodes to the irg which */
1685 /* invalidates the phase data */
1687 if (cg->opt & IA32_OPT_LEA) {
1688 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1691 if (cg->opt & IA32_OPT_DOAM) {
1692 /* we need height information for am optimization */
1693 heights_t *h = heights_new(cg->irg);
1694 ia32_am_opt_env_t env;
1699 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);