8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
23 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
25 typedef int is_op_func_t(const ir_node *n);
28 * checks if a node represents the NOREG value
30 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
31 be_abi_irg_t *babi = cg->birg->abi;
32 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
33 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
35 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
36 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
41 /*************************************************
44 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
45 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
46 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
47 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
49 *************************************************/
52 * creates a unique ident by adding a number to a tag
54 * @param tag the tag string, must contain a %d if a number
57 static ident *unique_id(const char *tag)
59 static unsigned id = 0;
62 snprintf(str, sizeof(str), tag, ++id);
63 return new_id_from_str(str);
69 * Transforms a SymConst.
71 * @param mod the debug module
72 * @param block the block the new node should belong to
73 * @param node the ir SymConst node
74 * @param mode mode of the SymConst
75 * @return the created ia32 Const node
77 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
79 dbg_info *dbg = env->dbg;
80 ir_mode *mode = env->mode;
81 ir_graph *irg = env->irg;
82 ir_node *block = env->block;
84 if (mode_is_float(mode)) {
85 if (USE_SSE2(env->cg))
86 cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
88 cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
91 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
93 set_ia32_Const_attr(cnst, env->irn);
98 * Get a primitive type for a mode.
100 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
102 pmap_entry *e = pmap_find(types, mode);
107 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
108 res = new_type_primitive(new_id_from_str(buf), mode);
109 pmap_insert(types, mode, res);
117 * Get an entity that is initialized with a tarval
119 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
121 tarval *tv = get_Const_tarval(cnst);
122 pmap_entry *e = pmap_find(cg->tv_ent, tv);
127 ir_mode *mode = get_irn_mode(cnst);
128 ir_type *tp = get_Const_type(cnst);
129 if (tp == firm_unknown_type)
130 tp = get_prim_type(cg->types, mode);
132 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
134 set_entity_ld_ident(res, get_entity_ident(res));
135 set_entity_visibility(res, visibility_local);
136 set_entity_variability(res, variability_constant);
137 set_entity_allocation(res, allocation_static);
139 /* we create a new entity here: It's initialization must resist on the
141 rem = current_ir_graph;
142 current_ir_graph = get_const_code_irg();
143 set_atomic_ent_value(res, new_Const_type(tv, tp));
144 current_ir_graph = rem;
152 * Transforms a Const.
154 * @param mod the debug module
155 * @param block the block the new node should belong to
156 * @param node the ir Const node
157 * @param mode mode of the Const
158 * @return the created ia32 Const node
160 static ir_node *gen_Const(ia32_transform_env_t *env) {
163 ir_graph *irg = env->irg;
164 ir_node *block = env->block;
165 ir_node *node = env->irn;
166 dbg_info *dbg = env->dbg;
167 ir_mode *mode = env->mode;
169 if (mode_is_float(mode)) {
170 if (! USE_SSE2(env->cg)) {
171 cnst_classify_t clss = classify_Const(node);
173 if (clss == CNST_NULL)
174 return new_rd_ia32_vfldz(dbg, irg, block, mode);
175 else if (clss == CNST_ONE)
176 return new_rd_ia32_vfld1(dbg, irg, block, mode);
178 sym.entity_p = get_entity_for_tv(env->cg, node);
180 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
182 cnst = gen_SymConst(env);
185 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
186 set_ia32_Const_attr(cnst, node);
194 * Transforms (all) Const's into ia32_Const and places them in the
195 * block where they are used (or in the cfg-pred Block in case of Phi's).
196 * Additionally all reference nodes are changed into mode_Is nodes.
198 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
199 ia32_code_gen_t *cg = env;
200 ia32_transform_env_t tenv;
202 ir_node *pred, *cnst;
209 mode = get_irn_mode(irn);
211 /* transform all reference nodes into mode_Is nodes */
212 if (mode_is_reference(mode)) {
214 set_irn_mode(irn, mode);
217 tenv.block = get_nodes_block(irn);
220 DEBUG_ONLY(tenv.mod = cg->mod;)
222 /* Loop over all predecessors and check for Sym/Const nodes */
223 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
224 pred = get_irn_n(irn, i);
226 opc = get_irn_opcode(pred);
228 tenv.mode = get_irn_mode(pred);
229 tenv.dbg = get_irn_dbg_info(pred);
231 /* If it's a Phi, then we need to create the */
232 /* new Const in it's predecessor block */
234 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
237 /* put the const into the block where the original const was */
238 if (! cg->opt.placecnst) {
239 tenv.block = get_nodes_block(pred);
244 cnst = gen_Const(&tenv);
247 cnst = gen_SymConst(&tenv);
253 /* if we found a const, then set it */
255 set_irn_n(irn, i, cnst);
262 /********************************************************************************************************
263 * _____ _ _ ____ _ _ _ _ _
264 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
265 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
266 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
267 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
268 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
271 ********************************************************************************************************/
274 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
277 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
278 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
282 * Checks for potential CJmp/CJmpAM optimization candidates.
284 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
285 ir_node *cand = NULL;
286 ir_node *prev = sched_prev(irn);
288 if (is_Block(prev)) {
289 if (get_Block_n_cfgpreds(prev) == 1)
290 prev = get_Block_cfgpred(prev, 0);
295 /* The predecessor must be a ProjX. */
296 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
297 prev = get_Proj_pred(prev);
299 if (is_op_func(prev))
306 static int is_TestJmp_cand(const ir_node *irn) {
307 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
311 * Checks if two consecutive arguments of cand matches
312 * the two arguments of irn (TestJmp).
314 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
315 ir_node *in1 = get_irn_n(irn, 0);
316 ir_node *in2 = get_irn_n(irn, 1);
317 int i, n = get_irn_arity(cand);
320 for (i = 0; i < n - 1; i++) {
321 if (get_irn_n(cand, i) == in1 &&
322 get_irn_n(cand, i + 1) == in2)
330 return ia32_cnst_compare(cand, irn);
336 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
338 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
339 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
342 /* we found a possible candidate */
343 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
346 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
348 if (is_ia32_And(cand))
349 set_irn_op(irn, op_ia32_CJmpAM);
351 set_irn_op(irn, op_ia32_CJmp);
353 DB((cg->mod, LEVEL_1, "%+F\n", irn));
357 static int is_CondJmp_cand(const ir_node *irn) {
358 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
362 * Checks if the arguments of cand are the same of irn.
364 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
365 int i, n = get_irn_arity(cand);
368 for (i = 0; i < n; i++) {
369 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
376 return ia32_cnst_compare(cand, irn);
382 * Tries to replace a CondJmp by a CJmpAM
384 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
385 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
388 /* we found a possible candidate */
389 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
392 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
394 set_irn_op(irn, op_ia32_CJmp);
396 DB((cg->mod, LEVEL_1, "%+F\n", irn));
401 * Tries to optimize two following IncSP.
403 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
404 ir_node *prev = be_get_IncSP_pred(irn);
405 int real_uses = get_irn_n_edges(prev);
407 if (real_uses != 1) {
409 This is a hack that should be removed if be_abi_fix_stack_nodes()
410 is fixed. Currently it leaves some IncSP's outside the chain ...
411 The previous IncSp is NOT our prev, but directly scheduled before ...
412 Impossible in a bug-free implementation :-)
414 prev = sched_prev(irn);
418 if (be_is_IncSP(prev) && real_uses == 1) {
419 /* first IncSP has only one IncSP user, kill the first one */
420 unsigned prev_offs = be_get_IncSP_offset(prev);
421 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
422 unsigned curr_offs = be_get_IncSP_offset(irn);
423 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
425 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
426 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
430 curr_dir = be_stack_dir_expand;
433 curr_dir = be_stack_dir_shrink;
434 be_set_IncSP_offset(prev, 0);
435 be_set_IncSP_offset(irn, (unsigned)new_ofs);
436 be_set_IncSP_direction(irn, curr_dir);
441 * Performs Peephole Optimizations.
443 void ia32_peephole_optimization(ir_node *irn, void *env) {
444 ia32_code_gen_t *cg = env;
446 if (is_ia32_TestJmp(irn))
447 ia32_optimize_TestJmp(irn, cg);
448 else if (is_ia32_CondJmp(irn))
449 ia32_optimize_CondJmp(irn, cg);
450 else if (be_is_IncSP(irn))
451 ia32_optimize_IncSP(irn, cg);
456 /******************************************************************
458 * /\ | | | | | \/ | | |
459 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
460 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
461 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
462 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
464 ******************************************************************/
466 static int node_is_ia32_comm(const ir_node *irn) {
467 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
470 static int ia32_get_irn_n_edges(const ir_node *irn) {
471 const ir_edge_t *edge;
474 foreach_out_edge(irn, edge) {
482 * Returns the first mode_M Proj connected to irn.
484 static ir_node *get_mem_proj(const ir_node *irn) {
485 const ir_edge_t *edge;
488 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
490 foreach_out_edge(irn, edge) {
491 src = get_edge_src_irn(edge);
493 assert(is_Proj(src) && "Proj expected");
495 if (get_irn_mode(src) == mode_M)
503 * Returns the first Proj with mode != mode_M connected to irn.
505 static ir_node *get_res_proj(const ir_node *irn) {
506 const ir_edge_t *edge;
509 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
511 foreach_out_edge(irn, edge) {
512 src = get_edge_src_irn(edge);
514 assert(is_Proj(src) && "Proj expected");
516 if (get_irn_mode(src) != mode_M)
524 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
526 * @param pred The node to be checked
527 * @param is_op_func The check-function
528 * @return 1 if conditions are fulfilled, 0 otherwise
530 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
531 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
539 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
540 * and if the predecessor is in block bl.
542 * @param bl The block
543 * @param pred The node to be checked
544 * @param is_op_func The check-function
545 * @return 1 if conditions are fulfilled, 0 otherwise
547 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
548 int (*is_op_func)(const ir_node *n))
551 pred = get_Proj_pred(pred);
552 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
563 * Checks if irn is a candidate for address calculation or address mode.
565 * address calculation (AC):
566 * - none of the operand must be a Load within the same block OR
567 * - all Loads must have more than one user OR
568 * - the irn has a frame entity (it's a former FrameAddr)
571 * - at least one operand has to be a Load within the same block AND
572 * - the load must not have other users than the irn AND
573 * - the irn must not have a frame entity set
575 * @param block The block the Loads must/not be in
576 * @param irn The irn to check
577 * @param check_addr 1 if to check for address calculation, 0 otherwise
578 * return 1 if irn is a candidate for AC or AM, 0 otherwise
580 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
582 int n, is_cand = check_addr;
584 in = get_irn_n(irn, 2);
586 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
587 n = ia32_get_irn_n_edges(in);
588 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
591 in = get_irn_n(irn, 3);
593 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
594 n = ia32_get_irn_n_edges(in);
595 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
598 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
604 * Compares the base and index addr and the load/store entities
605 * and returns 1 if they are equal.
607 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
608 const ir_node *addr_b, const ir_node *addr_i)
610 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
611 entity *lent = get_ia32_frame_ent(load);
612 entity *sent = get_ia32_frame_ent(store);
613 ident *lid = get_ia32_am_sc(load);
614 ident *sid = get_ia32_am_sc(store);
615 char *loffs = get_ia32_am_offs(load);
616 char *soffs = get_ia32_am_offs(store);
618 /* are both entities set and equal? */
619 if (is_equal && (lent || sent))
620 is_equal = lent && sent && (lent == sent);
622 /* are address mode idents set and equal? */
623 if (is_equal && (lid || sid))
624 is_equal = lid && sid && (lid == sid);
626 /* are offsets set and equal */
627 if (is_equal && (loffs || soffs))
628 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
630 /* are the load and the store of the same mode? */
631 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
639 * Folds Add or Sub to LEA if possible
641 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
642 ir_graph *irg = get_irn_irg(irn);
643 dbg_info *dbg = get_irn_dbg_info(irn);
644 ir_node *block = get_nodes_block(irn);
647 const char *offs_cnst = NULL;
648 char *offs_lea = NULL;
655 ir_node *left, *right, *temp;
656 ir_node *base, *index;
657 ia32_am_flavour_t am_flav;
658 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
660 if (is_ia32_Add(irn))
663 left = get_irn_n(irn, 2);
664 right = get_irn_n(irn, 3);
666 /* "normalize" arguments in case of add with two operands */
667 if (isadd && ! be_is_NoReg(cg, right)) {
668 /* put LEA == ia32_am_O as right operand */
669 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
670 set_irn_n(irn, 2, right);
671 set_irn_n(irn, 3, left);
677 /* put LEA != ia32_am_O as left operand */
678 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
679 set_irn_n(irn, 2, right);
680 set_irn_n(irn, 3, left);
686 /* put SHL as left operand iff left is NOT a LEA */
687 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
688 set_irn_n(irn, 2, right);
689 set_irn_n(irn, 3, left);
702 /* check for operation with immediate */
703 if (is_ia32_ImmConst(irn)) {
704 DBG((mod, LEVEL_1, "\tfound op with imm const"));
706 offs_cnst = get_ia32_cnst(irn);
709 else if (is_ia32_ImmSymConst(irn)) {
710 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
714 am_sc = get_ia32_id_cnst(irn);
715 am_sc_sign = is_ia32_am_sc_sign(irn);
718 /* determine the operand which needs to be checked */
719 if (be_is_NoReg(cg, right)) {
726 /* check if right operand is AMConst (LEA with ia32_am_O) */
727 /* but we can only eat it up if there is no other symconst */
728 /* because the linker won't accept two symconsts */
729 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
730 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
732 offs_lea = get_ia32_am_offs(temp);
733 am_sc = get_ia32_am_sc(temp);
734 am_sc_sign = is_ia32_am_sc_sign(temp);
740 /* default for add -> make right operand to index */
744 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
746 /* determine the operand which needs to be checked */
748 if (is_ia32_Lea(left)) {
752 /* check for SHL 1,2,3 */
753 if (pred_is_specific_node(temp, is_ia32_Shl)) {
754 temp = get_Proj_pred(temp);
756 if (get_ia32_Immop_tarval(temp)) {
757 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
760 index = get_irn_n(temp, 2);
762 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
768 if (! be_is_NoReg(cg, index)) {
769 /* if we have index, but left == right -> no base */
773 else if (! is_ia32_Lea(left) && (index != right)) {
774 /* index != right -> we found a good Shl */
775 /* left != LEA -> this Shl was the left operand */
776 /* -> base is right operand */
782 /* Try to assimilate a LEA as left operand */
783 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
784 am_flav = get_ia32_am_flavour(left);
786 /* If we have an Add with a real right operand (not NoReg) and */
787 /* the LEA contains already an index calculation then we create */
789 /* If the LEA contains already a frame_entity then we also */
790 /* create a new one otherwise we would loose it. */
791 if ((isadd && !be_is_NoReg(cg, index) && (am_flav & ia32_am_I)) || /* no new LEA if index already set */
792 get_ia32_frame_ent(left) || /* no new LEA if stack access */
793 (have_am_sc && get_ia32_am_sc(left))) /* no new LEA if AM symconst already present */
795 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
798 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
799 offs = get_ia32_am_offs(left);
800 am_sc = have_am_sc ? am_sc : get_ia32_am_sc(left);
801 have_am_sc = am_sc ? 1 : 0;
802 am_sc_sign = is_ia32_am_sc_sign(left);
803 base = get_irn_n(left, 0);
804 index = get_irn_n(left, 1);
805 scale = get_ia32_am_scale(left);
809 /* ok, we can create a new LEA */
811 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
813 /* add the old offset of a previous LEA */
815 add_ia32_am_offs(res, offs);
818 /* add the new offset */
821 add_ia32_am_offs(res, offs_cnst);
824 add_ia32_am_offs(res, offs_lea);
828 /* either lea_O-cnst, -cnst or -lea_O */
831 add_ia32_am_offs(res, offs_lea);
834 sub_ia32_am_offs(res, offs_cnst);
837 sub_ia32_am_offs(res, offs_lea);
841 /* set the address mode symconst */
843 set_ia32_am_sc(res, am_sc);
845 set_ia32_am_sc_sign(res);
848 /* copy the frame entity (could be set in case of Add */
849 /* which was a FrameAddr) */
850 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
852 if (is_ia32_use_frame(irn))
853 set_ia32_use_frame(res);
856 set_ia32_am_scale(res, scale);
859 /* determine new am flavour */
860 if (offs || offs_cnst || offs_lea) {
863 if (! be_is_NoReg(cg, base)) {
866 if (! be_is_NoReg(cg, index)) {
872 set_ia32_am_flavour(res, am_flav);
874 set_ia32_op_type(res, ia32_AddrModeS);
876 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
878 /* get the result Proj of the Add/Sub */
879 irn = get_res_proj(irn);
881 assert(irn && "Couldn't find result proj");
883 /* exchange the old op with the new LEA */
891 * Optimizes a pattern around irn to address mode if possible.
893 void ia32_optimize_am(ir_node *irn, void *env) {
894 ia32_code_gen_t *cg = env;
898 ir_node *block, *noreg_gp, *noreg_fp;
899 ir_node *left, *right, *temp;
900 ir_node *store, *load, *mem_proj;
901 ir_node *succ, *addr_b, *addr_i;
902 int check_am_src = 0;
903 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
905 if (! is_ia32_irn(irn))
908 dbg = get_irn_dbg_info(irn);
909 mode = get_irn_mode(irn);
910 block = get_nodes_block(irn);
911 noreg_gp = ia32_new_NoReg_gp(cg);
912 noreg_fp = ia32_new_NoReg_fp(cg);
914 DBG((mod, LEVEL_1, "checking for AM\n"));
916 /* 1st part: check for address calculations and transform the into Lea */
918 /* Following cases can occur: */
919 /* - Sub (l, imm) -> LEA [base - offset] */
920 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
921 /* - Add (l, imm) -> LEA [base + offset] */
922 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
923 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
924 /* - Add (l, r) -> LEA [base + index * scale] */
925 /* with scale > 1 iff l/r == shl (1,2,3) */
927 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
928 left = get_irn_n(irn, 2);
929 right = get_irn_n(irn, 3);
931 /* Do not try to create a LEA if one of the operands is a Load. */
932 /* check is irn is a candidate for address calculation */
933 if (is_candidate(block, irn, 1)) {
934 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
935 res = fold_addr(cg, irn, noreg_gp);
938 DB((mod, LEVEL_1, "transformed into %+F\n", res));
940 DB((mod, LEVEL_1, "not transformed\n"));
944 /* 2nd part: fold following patterns: */
945 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
946 /* - Store -> LEA into Store } it might be better to keep the LEA */
947 /* - op -> Load into AMop with am_Source */
949 /* - op is am_Source capable AND */
950 /* - the Load is only used by this op AND */
951 /* - the Load is in the same block */
952 /* - Store -> op -> Load into AMop with am_Dest */
954 /* - op is am_Dest capable AND */
955 /* - the Store uses the same address as the Load AND */
956 /* - the Load is only used by this op AND */
957 /* - the Load and Store are in the same block AND */
958 /* - nobody else uses the result of the op */
960 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
961 /* 1st: check for Load/Store -> LEA */
962 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
963 left = get_irn_n(irn, 0);
965 if (is_ia32_Lea(left)) {
966 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
968 /* get the AM attributes from the LEA */
969 add_ia32_am_offs(irn, get_ia32_am_offs(left));
970 set_ia32_am_scale(irn, get_ia32_am_scale(left));
971 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
973 set_ia32_am_sc(irn, get_ia32_am_sc(left));
974 if (is_ia32_am_sc_sign(left))
975 set_ia32_am_sc_sign(irn);
977 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
979 /* set base and index */
980 set_irn_n(irn, 0, get_irn_n(left, 0));
981 set_irn_n(irn, 1, get_irn_n(left, 1));
983 /* clear remat flag */
984 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
987 /* check if the node is an address mode candidate */
988 else if (is_candidate(block, irn, 0)) {
989 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
991 left = get_irn_n(irn, 2);
992 if (get_irn_arity(irn) == 4) {
993 /* it's an "unary" operation */
997 right = get_irn_n(irn, 3);
1000 /* normalize commutative ops */
1001 if (node_is_ia32_comm(irn)) {
1002 /* Assure that right operand is always a Load if there is one */
1003 /* because non-commutative ops can only use Dest AM if the right */
1004 /* operand is a load, so we only need to check right operand. */
1005 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1007 set_irn_n(irn, 2, right);
1008 set_irn_n(irn, 3, left);
1016 /* check for Store -> op -> Load */
1018 /* Store -> op -> Load optimization is only possible if supported by op */
1019 /* and if right operand is a Load */
1020 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1021 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1024 /* An address mode capable op always has a result Proj. */
1025 /* If this Proj is used by more than one other node, we don't need to */
1026 /* check further, otherwise we check for Store and remember the address, */
1027 /* the Store points to. */
1029 succ = get_res_proj(irn);
1030 assert(succ && "Couldn't find result proj");
1036 /* now check for users and Store */
1037 if (ia32_get_irn_n_edges(succ) == 1) {
1038 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1040 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
1042 addr_b = get_irn_n(store, 0);
1044 /* Could be that the Store is connected to the address */
1045 /* calculating LEA while the Load is already transformed. */
1046 if (is_ia32_Lea(addr_b)) {
1048 addr_b = get_irn_n(succ, 0);
1049 addr_i = get_irn_n(succ, 1);
1058 /* we found a Store as single user: Now check for Load */
1060 /* Extra check for commutative ops with two Loads */
1061 /* -> put the interesting Load right */
1062 if (node_is_ia32_comm(irn) &&
1063 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1065 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1066 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1068 /* We exchange left and right, so it's easier to kill */
1069 /* the correct Load later and to handle unary operations. */
1070 set_irn_n(irn, 2, right);
1071 set_irn_n(irn, 3, left);
1079 /* skip the Proj for easier access */
1080 load = get_Proj_pred(right);
1082 /* Compare Load and Store address */
1083 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1084 /* Right Load is from same address, so we can */
1085 /* disconnect the Load and Store here */
1087 /* set new base, index and attributes */
1088 set_irn_n(irn, 0, addr_b);
1089 set_irn_n(irn, 1, addr_i);
1090 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1091 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1092 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1093 set_ia32_op_type(irn, ia32_AddrModeD);
1094 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1095 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1097 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1098 if (is_ia32_am_sc_sign(load))
1099 set_ia32_am_sc_sign(irn);
1101 if (is_ia32_use_frame(load))
1102 set_ia32_use_frame(irn);
1104 /* connect to Load memory and disconnect Load */
1105 if (get_irn_arity(irn) == 5) {
1107 set_irn_n(irn, 4, get_irn_n(load, 2));
1108 set_irn_n(irn, 3, noreg_gp);
1112 set_irn_n(irn, 3, get_irn_n(load, 2));
1113 set_irn_n(irn, 2, noreg_gp);
1116 /* connect the memory Proj of the Store to the op */
1117 mem_proj = get_mem_proj(store);
1118 set_Proj_pred(mem_proj, irn);
1119 set_Proj_proj(mem_proj, 1);
1121 /* clear remat flag */
1122 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1124 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1127 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1128 /* There was no store, check if we still can optimize for source address mode */
1131 } /* if (support AM Dest) */
1132 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1133 /* op doesn't support am AM Dest -> check for AM Source */
1137 /* normalize commutative ops */
1138 if (node_is_ia32_comm(irn)) {
1139 /* Assure that left operand is always a Load if there is one */
1140 /* because non-commutative ops can only use Source AM if the */
1141 /* left operand is a Load, so we only need to check the left */
1142 /* operand afterwards. */
1143 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1144 set_irn_n(irn, 2, right);
1145 set_irn_n(irn, 3, left);
1153 /* optimize op -> Load iff Load is only used by this op */
1154 /* and left operand is a Load which only used by this irn */
1156 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1157 (ia32_get_irn_n_edges(left) == 1))
1159 left = get_Proj_pred(left);
1161 addr_b = get_irn_n(left, 0);
1162 addr_i = get_irn_n(left, 1);
1164 /* set new base, index and attributes */
1165 set_irn_n(irn, 0, addr_b);
1166 set_irn_n(irn, 1, addr_i);
1167 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1168 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1169 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1170 set_ia32_op_type(irn, ia32_AddrModeS);
1171 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1172 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1174 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1175 if (is_ia32_am_sc_sign(left))
1176 set_ia32_am_sc_sign(irn);
1178 /* clear remat flag */
1179 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1181 if (is_ia32_use_frame(left))
1182 set_ia32_use_frame(irn);
1184 /* connect to Load memory */
1185 if (get_irn_arity(irn) == 5) {
1187 set_irn_n(irn, 4, get_irn_n(left, 2));
1191 set_irn_n(irn, 3, get_irn_n(left, 2));
1194 /* disconnect from Load */
1195 set_irn_n(irn, 2, noreg_gp);
1197 /* If Load has a memory Proj, connect it to the op */
1198 mem_proj = get_mem_proj(left);
1200 set_Proj_pred(mem_proj, irn);
1201 set_Proj_proj(mem_proj, 1);
1204 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));