2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
45 #include "../benode.h"
46 #include "../besched.h"
47 #include "../bepeephole.h"
49 #include "ia32_new_nodes.h"
50 #include "ia32_optimize.h"
51 #include "bearch_ia32_t.h"
52 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_common_transform.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static void copy_mark(const ir_node *old, ir_node *newn)
62 if (is_ia32_is_reload(old))
63 set_ia32_is_reload(newn);
64 if (is_ia32_is_spill(old))
65 set_ia32_is_spill(newn);
66 if (is_ia32_is_remat(old))
67 set_ia32_is_remat(newn);
70 typedef enum produces_flag_t {
77 * Return which usable flag the given node produces
79 * @param node the node to check
80 * @param pn the projection number of the used result
82 static produces_flag_t produces_test_flag(ir_node *node, int pn)
85 const ia32_immediate_attr_t *imm_attr;
87 if (!is_ia32_irn(node))
88 return produces_no_flag;
90 switch (get_ia32_irn_opcode(node)) {
105 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
106 count = get_irn_n(node, n_ia32_ShlD_count);
107 goto check_shift_amount;
112 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
113 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
114 count = get_irn_n(node, n_ia32_Shl_count);
116 /* when shift count is zero the flags are not affected, so we can only
117 * do this for constants != 0 */
118 if (!is_ia32_Immediate(count))
119 return produces_no_flag;
121 imm_attr = get_ia32_immediate_attr_const(count);
122 if (imm_attr->symconst != NULL)
123 return produces_no_flag;
124 if ((imm_attr->offset & 0x1f) == 0)
125 return produces_no_flag;
129 return pn == pn_ia32_Mul_res_high ?
130 produces_flag_carry : produces_no_flag;
133 return produces_no_flag;
136 return pn == pn_ia32_res ?
137 produces_flag_zero : produces_no_flag;
141 * Replace Cmp(x, 0) by a Test(x, x)
143 static void peephole_ia32_Cmp(ir_node *const node)
147 ia32_immediate_attr_t const *imm;
153 ia32_attr_t const *attr;
156 arch_register_t const *reg;
157 ir_edge_t const *edge;
158 ir_edge_t const *tmp;
160 if (get_ia32_op_type(node) != ia32_Normal)
163 right = get_irn_n(node, n_ia32_Cmp_right);
164 if (!is_ia32_Immediate(right))
167 imm = get_ia32_immediate_attr_const(right);
168 if (imm->symconst != NULL || imm->offset != 0)
171 dbgi = get_irn_dbg_info(node);
172 irg = get_irn_irg(node);
173 block = get_nodes_block(node);
174 noreg = ia32_new_NoReg_gp(irg);
175 nomem = get_irg_no_mem(current_ir_graph);
176 op = get_irn_n(node, n_ia32_Cmp_left);
177 attr = get_ia32_attr(node);
178 ins_permuted = attr->data.ins_permuted;
180 if (is_ia32_Cmp(node)) {
181 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
182 op, op, ins_permuted);
184 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
185 op, op, ins_permuted);
187 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
189 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
190 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
192 foreach_out_edge_safe(node, edge, tmp) {
193 ir_node *const user = get_edge_src_irn(edge);
196 exchange(user, test);
199 sched_add_before(node, test);
200 copy_mark(node, test);
201 be_peephole_exchange(node, test);
205 * Peephole optimization for Test instructions.
206 * - Remove the Test, if an appropriate flag was produced which is still live
207 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
209 static void peephole_ia32_Test(ir_node *node)
211 ir_node *left = get_irn_n(node, n_ia32_Test_left);
212 ir_node *right = get_irn_n(node, n_ia32_Test_right);
214 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
215 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
217 if (left == right) { /* we need a test for 0 */
218 ir_node *block = get_nodes_block(node);
219 int pn = pn_ia32_res;
224 const ir_edge_t *edge;
226 if (get_nodes_block(left) != block)
230 pn = get_Proj_proj(op);
231 op = get_Proj_pred(op);
234 /* walk schedule up and abort when we find left or some other node
235 * destroys the flags */
238 schedpoint = sched_prev(schedpoint);
239 if (schedpoint == op)
241 if (arch_irn_is(schedpoint, modify_flags))
243 if (schedpoint == block)
244 panic("couldn't find left");
247 /* make sure only Lg/Eq tests are used */
248 foreach_out_edge(node, edge) {
249 ir_node *user = get_edge_src_irn(edge);
250 ia32_condition_code_t cc = get_ia32_condcode(user);
252 if (cc != ia32_cc_equal && cc != ia32_cc_not_equal) {
257 switch (produces_test_flag(op, pn)) {
258 case produces_flag_zero:
261 case produces_flag_carry:
262 foreach_out_edge(node, edge) {
263 ir_node *user = get_edge_src_irn(edge);
264 ia32_condition_code_t cc = get_ia32_condcode(user);
267 case ia32_cc_equal: cc = ia32_cc_above_equal; break; /* CF = 0 */
268 case ia32_cc_not_equal: cc = ia32_cc_below; break; /* CF = 1 */
269 default: panic("unexpected pn");
271 set_ia32_condcode(user, cc);
279 if (get_irn_mode(op) != mode_T) {
280 set_irn_mode(op, mode_T);
282 /* If there are other users, reroute them to result proj */
283 if (get_irn_n_edges(op) != 2) {
284 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
286 edges_reroute(op, res);
287 /* Reattach the result proj to left */
288 set_Proj_pred(res, op);
291 if (get_irn_n_edges(left) == 2)
295 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
296 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
297 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
299 assert(get_irn_mode(node) != mode_T);
301 be_peephole_exchange(node, flags_proj);
302 } else if (is_ia32_Immediate(right)) {
303 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
306 /* A test with a symconst is rather strange, but better safe than sorry */
307 if (imm->symconst != NULL)
310 offset = imm->offset;
311 if (get_ia32_op_type(node) == ia32_AddrModeS) {
312 ia32_attr_t *const attr = get_ia32_attr(node);
314 if ((offset & 0xFFFFFF00) == 0) {
315 /* attr->am_offs += 0; */
316 } else if ((offset & 0xFFFF00FF) == 0) {
317 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
318 set_irn_n(node, n_ia32_Test_right, imm);
320 } else if ((offset & 0xFF00FFFF) == 0) {
321 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
322 set_irn_n(node, n_ia32_Test_right, imm);
324 } else if ((offset & 0x00FFFFFF) == 0) {
325 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
326 set_irn_n(node, n_ia32_Test_right, imm);
331 } else if (offset < 256) {
332 arch_register_t const* const reg = arch_get_irn_register(left);
334 if (reg != &ia32_registers[REG_EAX] &&
335 reg != &ia32_registers[REG_EBX] &&
336 reg != &ia32_registers[REG_ECX] &&
337 reg != &ia32_registers[REG_EDX]) {
344 /* Technically we should build a Test8Bit because of the register
345 * constraints, but nobody changes registers at this point anymore. */
346 set_ia32_ls_mode(node, mode_Bu);
351 * AMD Athlon works faster when RET is not destination of
352 * conditional jump or directly preceded by other jump instruction.
353 * Can be avoided by placing a Rep prefix before the return.
355 static void peephole_ia32_Return(ir_node *node)
357 ir_node *block, *irn;
359 if (!ia32_cg_config.use_pad_return)
362 block = get_nodes_block(node);
364 /* check if this return is the first on the block */
365 sched_foreach_reverse_from(node, irn) {
366 switch (get_irn_opcode(irn)) {
368 /* the return node itself, ignore */
372 /* ignore no code generated */
375 /* arg, IncSP 0 nodes might occur, ignore these */
376 if (be_get_IncSP_offset(irn) == 0)
386 /* ensure, that the 3 byte return is generated */
387 be_Return_set_emit_pop(node, 1);
390 /* only optimize up to 48 stores behind IncSPs */
391 #define MAXPUSH_OPTIMIZE 48
394 * Tries to create Push's from IncSP, Store combinations.
395 * The Stores are replaced by Push's, the IncSP is modified
396 * (possibly into IncSP 0, but not removed).
398 static void peephole_IncSP_Store_to_push(ir_node *irn)
404 ir_node *stores[MAXPUSH_OPTIMIZE];
409 ir_node *first_push = NULL;
410 ir_edge_t const *edge;
411 ir_edge_t const *next;
413 memset(stores, 0, sizeof(stores));
415 assert(be_is_IncSP(irn));
417 inc_ofs = be_get_IncSP_offset(irn);
422 * We first walk the schedule after the IncSP node as long as we find
423 * suitable Stores that could be transformed to a Push.
424 * We save them into the stores array which is sorted by the frame offset/4
425 * attached to the node
428 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
433 /* it has to be a Store */
434 if (!is_ia32_Store(node))
437 /* it has to use our sp value */
438 if (get_irn_n(node, n_ia32_base) != irn)
440 /* Store has to be attached to NoMem */
441 mem = get_irn_n(node, n_ia32_mem);
445 /* unfortunately we can't support the full AMs possible for push at the
446 * moment. TODO: fix this */
447 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
450 offset = get_ia32_am_offs_int(node);
451 /* we should NEVER access uninitialized stack BELOW the current SP */
454 /* storing at half-slots is bad */
455 if ((offset & 3) != 0)
458 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
460 storeslot = offset >> 2;
462 /* storing into the same slot twice is bad (and shouldn't happen...) */
463 if (stores[storeslot] != NULL)
466 stores[storeslot] = node;
467 if (storeslot > maxslot)
473 for (i = -1; i < maxslot; ++i) {
474 if (stores[i + 1] == NULL)
478 /* walk through the Stores and create Pushs for them */
479 block = get_nodes_block(irn);
480 spmode = get_irn_mode(irn);
481 irg = get_irn_irg(irn);
482 for (; i >= 0; --i) {
483 const arch_register_t *spreg;
485 ir_node *val, *mem, *mem_proj;
486 ir_node *store = stores[i];
487 ir_node *noreg = ia32_new_NoReg_gp(irg);
489 val = get_irn_n(store, n_ia32_unary_op);
490 mem = get_irn_n(store, n_ia32_mem);
491 spreg = arch_get_irn_register(curr_sp);
493 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
494 copy_mark(store, push);
496 if (first_push == NULL)
499 sched_add_after(skip_Proj(curr_sp), push);
501 /* create stackpointer Proj */
502 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
503 arch_set_irn_register(curr_sp, spreg);
505 /* create memory Proj */
506 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
508 /* use the memproj now */
509 be_peephole_exchange(store, mem_proj);
514 foreach_out_edge_safe(irn, edge, next) {
515 ir_node *const src = get_edge_src_irn(edge);
516 int const pos = get_edge_src_pos(edge);
518 if (src == first_push)
521 set_irn_n(src, pos, curr_sp);
524 be_set_IncSP_offset(irn, inc_ofs);
529 * Creates a Push instruction before the given schedule point.
531 * @param dbgi debug info
532 * @param block the block
533 * @param stack the previous stack value
534 * @param schedpoint the new node is added before this node
535 * @param reg the register to pop
537 * @return the new stack value
539 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
540 ir_node *stack, ir_node *schedpoint)
542 const arch_register_t *esp = &ia32_registers[REG_ESP];
544 ir_node *val = ia32_new_NoReg_gp(cg);
545 ir_node *noreg = ia32_new_NoReg_gp(cg);
546 ir_graph *irg = get_irn_irg(block);
547 ir_node *nomem = new_r_NoMem(irg);
548 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
549 sched_add_before(schedpoint, push);
551 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
552 arch_set_irn_register(stack, esp);
557 static void peephole_store_incsp(ir_node *store)
568 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
569 if (!be_is_IncSP(am_base)
570 || get_nodes_block(am_base) != get_nodes_block(store))
572 mem = get_irn_n(store, n_ia32_Store_mem);
573 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
577 int incsp_offset = be_get_IncSP_offset(am_base);
578 if (incsp_offset <= 0)
581 /* we have to be at offset 0 */
582 int my_offset = get_ia32_am_offs_int(store);
583 if (my_offset != 0) {
584 /* TODO here: find out whether there is a store with offset 0 before
585 * us and whether we can move it down to our place */
588 ir_mode *ls_mode = get_ia32_ls_mode(store);
589 int my_store_size = get_mode_size_bytes(ls_mode);
591 if (my_offset + my_store_size > incsp_offset)
594 /* correctness checking:
595 - noone else must write to that stackslot
596 (because after translation incsp won't allocate it anymore)
598 sched_foreach_reverse_from(store, node) {
604 /* make sure noone else can use the space on the stack */
605 arity = get_irn_arity(node);
606 for (i = 0; i < arity; ++i) {
607 ir_node *pred = get_irn_n(node, i);
611 if (i == n_ia32_base &&
612 (get_ia32_op_type(node) == ia32_AddrModeS
613 || get_ia32_op_type(node) == ia32_AddrModeD)) {
614 int node_offset = get_ia32_am_offs_int(node);
615 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
616 int node_size = get_mode_size_bytes(node_ls_mode);
617 /* overlapping with our position? abort */
618 if (node_offset < my_offset + my_store_size
619 && node_offset + node_size >= my_offset)
621 /* otherwise it's fine */
625 /* strange use of esp: abort */
630 /* all ok, change to push */
631 dbgi = get_irn_dbg_info(store);
632 block = get_nodes_block(store);
633 noreg = ia32_new_NoReg_gp(cg);
634 val = get_irn_n(store, n_ia32_Store_val);
636 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
638 create_push(dbgi, current_ir_graph, block, am_base, store);
643 * Return true if a mode can be stored in the GP register set
645 static inline int mode_needs_gp_reg(ir_mode *mode)
647 if (mode == ia32_mode_fpcw)
649 if (get_mode_size_bits(mode) > 32)
651 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
655 * Tries to create Pops from Load, IncSP combinations.
656 * The Loads are replaced by Pops, the IncSP is modified
657 * (possibly into IncSP 0, but not removed).
659 static void peephole_Load_IncSP_to_pop(ir_node *irn)
661 const arch_register_t *esp = &ia32_registers[REG_ESP];
662 int i, maxslot, inc_ofs, ofs;
663 ir_node *node, *pred_sp, *block;
664 ir_node *loads[MAXPUSH_OPTIMIZE];
666 unsigned regmask = 0;
667 unsigned copymask = ~0;
669 memset(loads, 0, sizeof(loads));
670 assert(be_is_IncSP(irn));
672 inc_ofs = -be_get_IncSP_offset(irn);
677 * We first walk the schedule before the IncSP node as long as we find
678 * suitable Loads that could be transformed to a Pop.
679 * We save them into the stores array which is sorted by the frame offset/4
680 * attached to the node
683 pred_sp = be_get_IncSP_pred(irn);
684 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
687 const arch_register_t *sreg, *dreg;
689 /* it has to be a Load */
690 if (!is_ia32_Load(node)) {
691 if (be_is_Copy(node)) {
692 if (!mode_needs_gp_reg(get_irn_mode(node))) {
693 /* not a GP copy, ignore */
696 dreg = arch_get_irn_register(node);
697 sreg = arch_get_irn_register(be_get_Copy_op(node));
698 if (regmask & copymask & (1 << sreg->index)) {
701 if (regmask & copymask & (1 << dreg->index)) {
704 /* we CAN skip Copies if neither the destination nor the source
705 * is not in our regmask, ie none of our future Pop will overwrite it */
706 regmask |= (1 << dreg->index) | (1 << sreg->index);
707 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
713 /* we can handle only GP loads */
714 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
717 /* it has to use our predecessor sp value */
718 if (get_irn_n(node, n_ia32_base) != pred_sp) {
719 /* it would be ok if this load does not use a Pop result,
720 * but we do not check this */
724 /* should have NO index */
725 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
728 offset = get_ia32_am_offs_int(node);
729 /* we should NEVER access uninitialized stack BELOW the current SP */
732 /* storing at half-slots is bad */
733 if ((offset & 3) != 0)
736 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
738 /* ignore those outside the possible windows */
739 if (offset > inc_ofs - 4)
741 loadslot = offset >> 2;
743 /* loading from the same slot twice is bad (and shouldn't happen...) */
744 if (loads[loadslot] != NULL)
747 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
748 if (regmask & (1 << dreg->index)) {
749 /* this register is already used */
752 regmask |= 1 << dreg->index;
754 loads[loadslot] = node;
755 if (loadslot > maxslot)
762 /* find the first slot */
763 for (i = maxslot; i >= 0; --i) {
764 ir_node *load = loads[i];
770 ofs = inc_ofs - (maxslot + 1) * 4;
773 /* create a new IncSP if needed */
774 block = get_nodes_block(irn);
775 irg = get_irn_irg(irn);
777 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
778 sched_add_before(irn, pred_sp);
781 /* walk through the Loads and create Pops for them */
782 for (++i; i <= maxslot; ++i) {
783 ir_node *load = loads[i];
785 const ir_edge_t *edge, *tmp;
786 const arch_register_t *reg;
788 mem = get_irn_n(load, n_ia32_mem);
789 reg = arch_irn_get_register(load, pn_ia32_Load_res);
791 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
792 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
794 copy_mark(load, pop);
796 /* create stackpointer Proj */
797 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
798 arch_set_irn_register(pred_sp, esp);
800 sched_add_before(irn, pop);
803 foreach_out_edge_safe(load, edge, tmp) {
804 ir_node *proj = get_edge_src_irn(edge);
806 set_Proj_pred(proj, pop);
809 /* we can remove the Load now */
814 be_set_IncSP_offset(irn, -ofs);
815 be_set_IncSP_pred(irn, pred_sp);
820 * Find a free GP register if possible, else return NULL.
822 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
824 be_irg_t *birg = be_birg_from_irg(irg);
827 for (i = 0; i < N_ia32_gp_REGS; ++i) {
828 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
829 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
832 if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
840 * Creates a Pop instruction before the given schedule point.
842 * @param dbgi debug info
843 * @param block the block
844 * @param stack the previous stack value
845 * @param schedpoint the new node is added before this node
846 * @param reg the register to pop
848 * @return the new stack value
850 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
851 ir_node *stack, ir_node *schedpoint,
852 const arch_register_t *reg)
854 const arch_register_t *esp = &ia32_registers[REG_ESP];
855 ir_graph *irg = get_irn_irg(block);
861 pop = new_bd_ia32_Pop(dbgi, block, new_r_NoMem(irg), stack);
863 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
864 arch_set_irn_register(stack, esp);
865 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
866 arch_set_irn_register(val, reg);
868 sched_add_before(schedpoint, pop);
871 keep = be_new_Keep(block, 1, in);
872 sched_add_before(schedpoint, keep);
878 * Optimize an IncSp by replacing it with Push/Pop.
880 static void peephole_be_IncSP(ir_node *node)
882 const arch_register_t *esp = &ia32_registers[REG_ESP];
883 const arch_register_t *reg;
889 /* first optimize incsp->incsp combinations */
890 node = be_peephole_IncSP_IncSP(node);
892 /* transform IncSP->Store combinations to Push where possible */
893 peephole_IncSP_Store_to_push(node);
895 /* transform Load->IncSP combinations to Pop where possible */
896 peephole_Load_IncSP_to_pop(node);
898 if (arch_get_irn_register(node) != esp)
901 /* replace IncSP -4 by Pop freereg when possible */
902 offset = be_get_IncSP_offset(node);
903 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
904 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
905 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
906 (offset != +8 || ia32_cg_config.use_sub_esp_8))
910 /* we need a free register for pop */
911 reg = get_free_gp_reg(get_irn_irg(node));
915 dbgi = get_irn_dbg_info(node);
916 block = get_nodes_block(node);
917 stack = be_get_IncSP_pred(node);
919 stack = create_pop(dbgi, block, stack, node, reg);
922 stack = create_pop(dbgi, block, stack, node, reg);
925 dbgi = get_irn_dbg_info(node);
926 block = get_nodes_block(node);
927 stack = be_get_IncSP_pred(node);
928 stack = new_bd_ia32_PushEax(dbgi, block, stack);
929 arch_set_irn_register(stack, esp);
930 sched_add_before(node, stack);
933 stack = new_bd_ia32_PushEax(dbgi, block, stack);
934 arch_set_irn_register(stack, esp);
935 sched_add_before(node, stack);
939 be_peephole_exchange(node, stack);
943 * Peephole optimisation for ia32_Const's
945 static void peephole_ia32_Const(ir_node *node)
947 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
948 const arch_register_t *reg;
953 /* try to transform a mov 0, reg to xor reg reg */
954 if (attr->offset != 0 || attr->symconst != NULL)
956 if (ia32_cg_config.use_mov_0)
958 /* xor destroys the flags, so no-one must be using them */
959 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
962 reg = arch_get_irn_register(node);
963 assert(be_peephole_get_reg_value(reg) == NULL);
965 /* create xor(produceval, produceval) */
966 block = get_nodes_block(node);
967 dbgi = get_irn_dbg_info(node);
968 xorn = new_bd_ia32_Xor0(dbgi, block);
969 arch_set_irn_register(xorn, reg);
971 sched_add_before(node, xorn);
973 copy_mark(node, xorn);
974 be_peephole_exchange(node, xorn);
977 static inline int is_noreg(const ir_node *node)
979 return is_ia32_NoReg_GP(node);
982 ir_node *ia32_immediate_from_long(long val)
984 ir_graph *irg = current_ir_graph;
985 ir_node *start_block = get_irg_start_block(irg);
987 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
988 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
993 static ir_node *create_immediate_from_am(const ir_node *node)
995 ir_node *block = get_nodes_block(node);
996 int offset = get_ia32_am_offs_int(node);
997 int sc_sign = is_ia32_am_sc_sign(node);
998 const ia32_attr_t *attr = get_ia32_attr_const(node);
999 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1000 ir_entity *entity = get_ia32_am_sc(node);
1003 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1005 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1009 static int is_am_one(const ir_node *node)
1011 int offset = get_ia32_am_offs_int(node);
1012 ir_entity *entity = get_ia32_am_sc(node);
1014 return offset == 1 && entity == NULL;
1017 static int is_am_minus_one(const ir_node *node)
1019 int offset = get_ia32_am_offs_int(node);
1020 ir_entity *entity = get_ia32_am_sc(node);
1022 return offset == -1 && entity == NULL;
1026 * Transforms a LEA into an Add or SHL if possible.
1028 static void peephole_ia32_Lea(ir_node *node)
1033 const arch_register_t *base_reg;
1034 const arch_register_t *index_reg;
1035 const arch_register_t *out_reg;
1046 assert(is_ia32_Lea(node));
1048 /* we can only do this if it is allowed to clobber the flags */
1049 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
1052 base = get_irn_n(node, n_ia32_Lea_base);
1053 index = get_irn_n(node, n_ia32_Lea_index);
1055 if (is_noreg(base)) {
1059 base_reg = arch_get_irn_register(base);
1061 if (is_noreg(index)) {
1065 index_reg = arch_get_irn_register(index);
1068 if (base == NULL && index == NULL) {
1069 /* we shouldn't construct these in the first place... */
1070 #ifdef DEBUG_libfirm
1071 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1076 out_reg = arch_get_irn_register(node);
1077 scale = get_ia32_am_scale(node);
1078 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1079 /* check if we have immediates values (frame entities should already be
1080 * expressed in the offsets) */
1081 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1087 /* we can transform leas where the out register is the same as either the
1088 * base or index register back to an Add or Shl */
1089 if (out_reg == base_reg) {
1090 if (index == NULL) {
1091 #ifdef DEBUG_libfirm
1092 if (!has_immediates) {
1093 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1098 goto make_add_immediate;
1100 if (scale == 0 && !has_immediates) {
1105 /* can't create an add */
1107 } else if (out_reg == index_reg) {
1109 if (has_immediates && scale == 0) {
1111 goto make_add_immediate;
1112 } else if (!has_immediates && scale > 0) {
1114 op2 = ia32_immediate_from_long(scale);
1116 } else if (!has_immediates) {
1117 #ifdef DEBUG_libfirm
1118 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1122 } else if (scale == 0 && !has_immediates) {
1127 /* can't create an add */
1130 /* can't create an add */
1135 if (ia32_cg_config.use_incdec) {
1136 if (is_am_one(node)) {
1137 dbgi = get_irn_dbg_info(node);
1138 block = get_nodes_block(node);
1139 res = new_bd_ia32_Inc(dbgi, block, op1);
1140 arch_set_irn_register(res, out_reg);
1143 if (is_am_minus_one(node)) {
1144 dbgi = get_irn_dbg_info(node);
1145 block = get_nodes_block(node);
1146 res = new_bd_ia32_Dec(dbgi, block, op1);
1147 arch_set_irn_register(res, out_reg);
1151 op2 = create_immediate_from_am(node);
1154 dbgi = get_irn_dbg_info(node);
1155 block = get_nodes_block(node);
1156 irg = get_irn_irg(node);
1157 noreg = ia32_new_NoReg_gp(irg);
1158 nomem = new_r_NoMem(irg);
1159 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1160 arch_set_irn_register(res, out_reg);
1161 set_ia32_commutative(res);
1165 dbgi = get_irn_dbg_info(node);
1166 block = get_nodes_block(node);
1167 irg = get_irn_irg(node);
1168 noreg = ia32_new_NoReg_gp(irg);
1169 nomem = new_r_NoMem(irg);
1170 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1171 arch_set_irn_register(res, out_reg);
1175 SET_IA32_ORIG_NODE(res, node);
1177 /* add new ADD/SHL to schedule */
1178 DBG_OPT_LEA2ADD(node, res);
1180 /* exchange the Add and the LEA */
1181 sched_add_before(node, res);
1182 copy_mark(node, res);
1183 be_peephole_exchange(node, res);
1187 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1189 static void peephole_ia32_Imul_split(ir_node *imul)
1191 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1192 const arch_register_t *reg;
1195 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1196 /* no memory, imm form ignore */
1199 /* we need a free register */
1200 reg = get_free_gp_reg(get_irn_irg(imul));
1204 /* fine, we can rebuild it */
1205 res = ia32_turn_back_am(imul);
1206 arch_set_irn_register(res, reg);
1210 * Replace xorps r,r and xorpd r,r by pxor r,r
1212 static void peephole_ia32_xZero(ir_node *xorn)
1214 set_irn_op(xorn, op_ia32_xPzero);
1218 * Replace 16bit sign extension from ax to eax by shorter cwtl
1220 static void peephole_ia32_Conv_I2I(ir_node *node)
1222 const arch_register_t *eax = &ia32_registers[REG_EAX];
1223 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1224 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1229 if (get_mode_size_bits(smaller_mode) != 16 ||
1230 !mode_is_signed(smaller_mode) ||
1231 eax != arch_get_irn_register(val) ||
1232 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1235 dbgi = get_irn_dbg_info(node);
1236 block = get_nodes_block(node);
1237 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1238 arch_set_irn_register(cwtl, eax);
1239 sched_add_before(node, cwtl);
1240 be_peephole_exchange(node, cwtl);
1244 * Register a peephole optimisation function.
1246 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1248 assert(op->ops.generic == NULL);
1249 op->ops.generic = (op_func)func;
1252 /* Perform peephole-optimizations. */
1253 void ia32_peephole_optimization(ir_graph *irg)
1255 /* register peephole optimisations */
1256 clear_irp_opcodes_generic_func();
1257 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1258 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1259 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1260 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1261 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1262 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1263 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1264 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1265 if (! ia32_cg_config.use_imul_mem_imm32)
1266 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1267 if (ia32_cg_config.use_pxor)
1268 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1269 if (ia32_cg_config.use_short_sex_eax)
1270 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1272 be_peephole_opt(irg);
1276 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1277 * all its Projs are removed as well.
1278 * @param irn The irn to be removed from schedule
1280 static inline void try_kill(ir_node *node)
1282 if (get_irn_mode(node) == mode_T) {
1283 const ir_edge_t *edge, *next;
1284 foreach_out_edge_safe(node, edge, next) {
1285 ir_node *proj = get_edge_src_irn(edge);
1290 if (get_irn_n_edges(node) != 0)
1293 if (sched_is_scheduled(node)) {
1300 static void optimize_conv_store(ir_node *node)
1305 ir_mode *store_mode;
1307 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1310 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1311 pred_proj = get_irn_n(node, n_ia32_Store_val);
1312 if (is_Proj(pred_proj)) {
1313 pred = get_Proj_pred(pred_proj);
1317 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1319 if (get_ia32_op_type(pred) != ia32_Normal)
1322 /* the store only stores the lower bits, so we only need the conv
1323 * it it shrinks the mode */
1324 conv_mode = get_ia32_ls_mode(pred);
1325 store_mode = get_ia32_ls_mode(node);
1326 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1329 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1330 if (get_irn_n_edges(pred_proj) == 0) {
1331 kill_node(pred_proj);
1332 if (pred != pred_proj)
1337 static void optimize_load_conv(ir_node *node)
1339 ir_node *pred, *predpred;
1343 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1346 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1347 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1351 predpred = get_Proj_pred(pred);
1352 if (!is_ia32_Load(predpred))
1355 /* the load is sign extending the upper bits, so we only need the conv
1356 * if it shrinks the mode */
1357 load_mode = get_ia32_ls_mode(predpred);
1358 conv_mode = get_ia32_ls_mode(node);
1359 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1362 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1363 /* change the load if it has only 1 user */
1364 if (get_irn_n_edges(pred) == 1) {
1366 if (get_mode_sign(conv_mode)) {
1367 newmode = find_signed_mode(load_mode);
1369 newmode = find_unsigned_mode(load_mode);
1371 assert(newmode != NULL);
1372 set_ia32_ls_mode(predpred, newmode);
1374 /* otherwise we have to keep the conv */
1380 exchange(node, pred);
1383 static void optimize_conv_conv(ir_node *node)
1385 ir_node *pred_proj, *pred, *result_conv;
1386 ir_mode *pred_mode, *conv_mode;
1390 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1393 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1394 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1395 if (is_Proj(pred_proj))
1396 pred = get_Proj_pred(pred_proj);
1400 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1403 /* we know that after a conv, the upper bits are sign extended
1404 * so we only need the 2nd conv if it shrinks the mode */
1405 conv_mode = get_ia32_ls_mode(node);
1406 conv_mode_bits = get_mode_size_bits(conv_mode);
1407 pred_mode = get_ia32_ls_mode(pred);
1408 pred_mode_bits = get_mode_size_bits(pred_mode);
1410 if (conv_mode_bits == pred_mode_bits
1411 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1412 result_conv = pred_proj;
1413 } else if (conv_mode_bits <= pred_mode_bits) {
1414 /* if 2nd conv is smaller then first conv, then we can always take the
1416 if (get_irn_n_edges(pred_proj) == 1) {
1417 result_conv = pred_proj;
1418 set_ia32_ls_mode(pred, conv_mode);
1420 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1421 if (get_mode_size_bits(conv_mode) == 8) {
1422 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1423 arch_set_in_register_reqs(pred,
1424 arch_get_in_register_reqs(node));
1427 /* we don't want to end up with 2 loads, so we better do nothing */
1428 if (get_irn_mode(pred) == mode_T) {
1432 result_conv = exact_copy(pred);
1433 set_ia32_ls_mode(result_conv, conv_mode);
1435 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1436 if (get_mode_size_bits(conv_mode) == 8) {
1437 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1438 arch_set_in_register_reqs(result_conv,
1439 arch_get_in_register_reqs(node));
1443 /* if both convs have the same sign, then we can take the smaller one */
1444 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1445 result_conv = pred_proj;
1447 /* no optimisation possible if smaller conv is sign-extend */
1448 if (mode_is_signed(pred_mode)) {
1451 /* we can take the smaller conv if it is unsigned */
1452 result_conv = pred_proj;
1456 /* Some user (like Phis) won't be happy if we change the mode. */
1457 set_irn_mode(result_conv, get_irn_mode(node));
1460 exchange(node, result_conv);
1462 if (get_irn_n_edges(pred_proj) == 0) {
1463 kill_node(pred_proj);
1464 if (pred != pred_proj)
1467 optimize_conv_conv(result_conv);
1470 static void optimize_node(ir_node *node, void *env)
1474 optimize_load_conv(node);
1475 optimize_conv_store(node);
1476 optimize_conv_conv(node);
1480 * Performs conv and address mode optimization.
1482 void ia32_optimize_graph(ir_graph *irg)
1484 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1487 void ia32_init_optimize(void)
1489 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");