nsz Git - libfirm/blob - ir/be/ia32/ia32_optimize.c

   1 #ifdef HAVE_CONFIG_H
   2 #include "config.h"
   3 #endif
   4
   5 #include "irnode.h"
   6 #include "irprog_t.h"
   7 #include "ircons.h"
   8 #include "firm_types.h"
   9 #include "iredges.h"
  10 #include "tv.h"
  11 #include "irgmod.h"
  12
  13 #include "../benode_t.h"
  14
  15 #include "ia32_new_nodes.h"
  16 #include "bearch_ia32_t.h"
  17
  18 #undef is_NoMem
  19 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
  20
  21 /**
  22  * creates a unique ident by adding a number to a tag
  23  *
  24  * @param tag   the tag string, must contain a %d if a number
  25  *              should be added
  26  */
  27 static ident *unique_id(const char *tag)
  28 {
  29         static unsigned id = 0;
  30         char str[256];
  31
  32         snprintf(str, sizeof(str), tag, ++id);
  33         return new_id_from_str(str);
  34 }
  35
  36
  37
  38 /**
  39  * Transforms a SymConst.
  40  *
  41  * @param mod     the debug module
  42  * @param block   the block the new node should belong to
  43  * @param node    the ir SymConst node
  44  * @param mode    mode of the SymConst
  45  * @return the created ia32 Const node
  46  */
  47 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
  48         ir_node  *cnst;
  49         dbg_info *dbg   = env->dbg;
  50         ir_mode  *mode  = env->mode;
  51         ir_graph *irg   = env->irg;
  52         ir_node  *block = env->block;
  53
  54         cnst = new_rd_ia32_Const(dbg, irg, block, mode);
  55         set_ia32_Const_attr(cnst, env->irn);
  56         return cnst;
  57 }
  58
  59 /**
  60  * Get a primitive type for a mode.
  61  */
  62 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
  63 {
  64         pmap_entry *e = pmap_find(types, mode);
  65         ir_type *res;
  66
  67         if (! e) {
  68                 char buf[64];
  69                 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
  70                 res = new_type_primitive(new_id_from_str(buf), mode);
  71                 pmap_insert(types, mode, res);
  72         }
  73         else
  74                 res = e->value;
  75         return res;
  76 }
  77
  78 /**
  79  * Get an entity that is initialized with a tarval
  80  */
  81 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
  82 {
  83         tarval *tv    = get_Const_tarval(cnst);
  84         pmap_entry *e = pmap_find(cg->tv_ent, tv);
  85         entity *res;
  86         ir_graph *rem;
  87
  88         if (! e) {
  89                 ir_mode *mode = get_irn_mode(cnst);
  90                 ir_type *tp = get_Const_type(cnst);
  91                 if (tp == firm_unknown_type)
  92                         tp = get_prim_type(cg->types, mode);
  93
  94                 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
  95
  96                 set_entity_ld_ident(res, get_entity_ident(res));
  97                 set_entity_visibility(res, visibility_local);
  98                 set_entity_variability(res, variability_constant);
  99                 set_entity_allocation(res, allocation_static);
 100
 101                  /* we create a new entity here: It's initialization must resist on the
 102                     const code irg */
 103                 rem = current_ir_graph;
 104                 current_ir_graph = get_const_code_irg();
 105                 set_atomic_ent_value(res, new_Const_type(tv, tp));
 106                 current_ir_graph = rem;
 107         }
 108         else
 109                 res = e->value;
 110         return res;
 111 }
 112
 113 /**
 114  * Transforms a Const.
 115  *
 116  * @param mod     the debug module
 117  * @param block   the block the new node should belong to
 118  * @param node    the ir Const node
 119  * @param mode    mode of the Const
 120  * @return the created ia32 Const node
 121  */
 122 static ir_node *gen_Const(ia32_transform_env_t *env) {
 123         ir_node *cnst;
 124         symconst_symbol sym;
 125         ir_graph *irg   = env->irg;
 126         ir_node  *block = env->block;
 127         ir_node  *node  = env->irn;
 128         dbg_info *dbg   = env->dbg;
 129         ir_mode  *mode  = env->mode;
 130
 131         if (mode_is_float(mode)) {
 132                 sym.entity_p = get_entity_for_tv(env->cg, node);
 133
 134                 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
 135                 env->irn = cnst;
 136                 cnst = gen_SymConst(env);
 137         }
 138         else {
 139                 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
 140                 set_ia32_Const_attr(cnst, node);
 141         }
 142         return cnst;
 143 }
 144
 145
 146
 147 /**
 148  * Transforms (all) Const's into ia32_Const and places them in the
 149  * block where they are used (or in the cfg-pred Block in case of Phi's)
 150  */
 151 void ia32_place_consts(ir_node *irn, void *env) {
 152         ia32_code_gen_t      *cg = env;
 153         ia32_transform_env_t  tenv;
 154         ir_mode              *mode;
 155         ir_node              *pred, *cnst;
 156         int                   i;
 157         opcode                opc;
 158
 159         if (is_Block(irn))
 160                 return;
 161
 162         mode = get_irn_mode(irn);
 163
 164         tenv.arch_env = cg->arch_env;
 165         tenv.block    = get_nodes_block(irn);
 166         tenv.cg       = cg;
 167         tenv.irg      = cg->irg;
 168         tenv.mod      = cg->mod;
 169
 170         /* Loop over all predecessors and check for Sym/Const nodes */
 171         for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
 172                 pred      = get_irn_n(irn, i);
 173                 cnst      = NULL;
 174                 opc       = get_irn_opcode(pred);
 175                 tenv.irn  = pred;
 176                 tenv.mode = get_irn_mode(pred);
 177                 tenv.dbg  = get_irn_dbg_info(pred);
 178
 179                 /* If it's a Phi, then we need to create the */
 180                 /* new Const in it's predecessor block       */
 181                 if (is_Phi(irn)) {
 182                         tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
 183                 }
 184
 185                 switch (opc) {
 186                         case iro_Const:
 187                                 cnst = gen_Const(&tenv);
 188                                 break;
 189                         case iro_SymConst:
 190                                 cnst = gen_SymConst(&tenv);
 191                                 break;
 192                         default:
 193                                 break;
 194                 }
 195
 196                 /* if we found a const, then set it */
 197                 if (cnst) {
 198                         set_irn_n(irn, i, cnst);
 199                 }
 200         }
 201 }
 202
 203
 204 /******************************************************************
 205  *              _     _                   __  __           _
 206  *     /\      | |   | |                 |  \/  |         | |
 207  *    /  \   __| | __| |_ __ ___  ___ ___| \  / | ___   __| | ___
 208  *   / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
 209  *  / ____ \ (_| | (_| | | |  __/\__ \__ \ |  | | (_) | (_| |  __/
 210  * /_/    \_\__,_|\__,_|_|  \___||___/___/_|  |_|\___/ \__,_|\___|
 211  *
 212  ******************************************************************/
 213
 214 static int node_is_comm(const ir_node *irn) {
 215         if (is_ia32_Add(irn)  ||
 216                 is_ia32_fAdd(irn) ||
 217                 is_ia32_Mul(irn)  ||
 218                 is_ia32_Mulh(irn) ||
 219                 is_ia32_fMul(irn) ||
 220                 is_ia32_And(irn)  ||
 221                 is_ia32_fAnd(irn) ||
 222                 is_ia32_Or(irn)   ||
 223                 is_ia32_fOr(irn)  ||
 224                 is_ia32_Eor(irn)  ||
 225                 is_ia32_fEor(irn) ||
 226                 is_ia32_Min(irn)  ||
 227                 is_ia32_fMin(irn) ||
 228                 is_ia32_Max(irn)  ||
 229                 is_ia32_fMax(irn))
 230         {
 231                 return 1;
 232         }
 233
 234         return 0;
 235 }
 236
 237 /**
 238  * Returns the first mode_M Proj connected to irn.
 239  */
 240 static ir_node *get_mem_proj(const ir_node *irn) {
 241         const ir_edge_t *edge;
 242         ir_node         *src;
 243
 244         assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
 245
 246         foreach_out_edge(irn, edge) {
 247                 src = get_edge_src_irn(edge);
 248
 249                 assert(is_Proj(src) && "Proj expected");
 250
 251                 if (get_irn_mode(src) == mode_M)
 252                         return src;
 253         }
 254
 255         return NULL;
 256 }
 257
 258 /**
 259  * Determines if irn is a Proj and if is_op_func returns true for it's predecessor.
 260  */
 261 static int pred_is_specific_node(const ir_node *irn, int (*is_op_func)(const ir_node *n)) {
 262         if (is_Proj(irn) && is_op_func(get_Proj_pred(irn))) {
 263                 return 1;
 264         }
 265
 266         return 0;
 267 }
 268
 269 /**
 270  * Folds Add or Sub to LEA if possible
 271  */
 272 static ir_node *fold_addr(ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
 273         ir_graph *irg      = get_irn_irg(irn);
 274         ir_mode  *mode     = get_irn_mode(irn);
 275         dbg_info *dbg      = get_irn_dbg_info(irn);
 276         ir_node  *block    = get_nodes_block(irn);
 277         ir_node  *res      = irn;
 278         char     *offs     = NULL;
 279         char     *new_offs = NULL;
 280         int       scale    = 0;
 281         int       isadd    = 0;
 282         int       dolea    = 0;
 283         ir_node  *left, *right, *temp;
 284         ir_node  *base, *index;
 285         ia32_am_flavour_t am_flav;
 286
 287         if (is_ia32_Add(irn))
 288                 isadd = 1;
 289
 290         left  = get_irn_n(irn, 2);
 291         right = get_irn_n(irn, 3);
 292
 293         /* "normalize" arguments in case of add */
 294         if  (isadd) {
 295                 /* put LEA == ia32_am_O as right operand */
 296                 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
 297                         temp  = left;
 298                         left  = right;
 299                         right = temp;
 300                 }
 301
 302                 /* put LEA != ia32_am_O as left operand */
 303                 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
 304                         temp  = left;
 305                         left  = right;
 306                         right = temp;
 307                 }
 308
 309                 /* put SHL as right operand */
 310                 if (pred_is_specific_node(left, is_ia32_Shl)) {
 311                         temp  = left;
 312                         left  = right;
 313                         right = temp;
 314                 }
 315         }
 316
 317         /* Left operand could already be a LEA */
 318         if (is_ia32_Lea(left)) {
 319                 DBG((mod, LEVEL_1, "\tgot LEA as left operand\n"));
 320
 321                 base  = get_irn_n(left, 0);
 322                 index = get_irn_n(left, 1);
 323                 offs  = get_ia32_am_offs(left);
 324                 scale = get_ia32_am_scale(left);
 325         }
 326         else {
 327                 base  = left;
 328                 index = noreg;
 329                 offs  = NULL;
 330                 scale = 0;
 331
 332         }
 333
 334         /* check if operand is either const or right operand is AMConst (LEA with ia32_am_O) */
 335         if (get_ia32_cnst(irn)) {
 336                 DBG((mod, LEVEL_1, "\tfound op with imm"));
 337
 338                 new_offs = get_ia32_cnst(irn);
 339                 dolea    = 1;
 340         }
 341         else if (is_ia32_Lea(right) && get_ia32_am_flavour(right) == ia32_am_O) {
 342                 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
 343
 344                 new_offs = get_ia32_am_offs(right);
 345                 dolea    = 1;
 346         }
 347         /* we can only get an additional index if there isn't already one */
 348         else if (isadd && be_is_NoReg(index)) {
 349                 /* default for add -> make right operand to index */
 350                 index = right;
 351                 dolea = 1;
 352
 353                 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
 354                 /* check for SHL 1,2,3 */
 355                 if (pred_is_specific_node(right, is_ia32_Shl)) {
 356                         temp = get_Proj_pred(right);
 357
 358                         if (get_ia32_Immop_tarval(temp)) {
 359                                 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
 360
 361                                 if (scale <= 3) {
 362                                         index = get_irn_n(temp, 2);
 363
 364                                         DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
 365                                 }
 366                         }
 367                 }
 368         }
 369
 370         /* ok, we can create a new LEA */
 371         if (dolea) {
 372                 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode);
 373
 374                 /* add the old offset of a previous LEA */
 375                 if (offs) {
 376                         add_ia32_am_offs(res, offs);
 377                 }
 378
 379                 /* add the new offset */
 380                 if (isadd) {
 381                         if (new_offs) {
 382                                 add_ia32_am_offs(res, new_offs);
 383                         }
 384                 }
 385                 else {
 386                         sub_ia32_am_offs(res, new_offs);
 387                 }
 388
 389                 /* set scale */
 390                 set_ia32_am_scale(res, scale);
 391
 392                 am_flav = ia32_am_N;
 393                 /* determine new am flavour */
 394                 if (offs || new_offs) {
 395                         am_flav |= ia32_O;
 396                 }
 397                 if (! be_is_NoReg(base)) {
 398                         am_flav |= ia32_B;
 399                 }
 400                 if (! be_is_NoReg(index)) {
 401                         am_flav |= ia32_I;
 402                 }
 403                 if (scale > 0) {
 404                         am_flav |= ia32_S;
 405                 }
 406                 set_ia32_am_flavour(res, am_flav);
 407
 408                 set_ia32_op_type(res, ia32_AddrModeS);
 409
 410                 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
 411
 412                 /* exchange the old op with the new LEA */
 413                 exchange(irn, res);
 414         }
 415
 416         return res;
 417 }
 418
 419 /**
 420  * Optimizes a pattern around irn to address mode if possible.
 421  */
 422 void ia32_optimize_am(ir_node *irn, void *env) {
 423         ia32_code_gen_t   *cg  = env;
 424         ir_graph          *irg = cg->irg;
 425         firm_dbg_module_t *mod = cg->mod;
 426         ir_node           *res = irn;
 427         dbg_info          *dbg;
 428         ir_mode           *mode;
 429         ir_node           *block, *noreg_gp, *noreg_fp;
 430         ir_node           *left, *right, *temp;
 431         ir_node           *store, *mem_proj;
 432         ir_node           *succ, *addr_b, *addr_i;
 433         int                check_am_src = 0;
 434
 435         if (! is_ia32_irn(irn))
 436                 return;
 437
 438         dbg      = get_irn_dbg_info(irn);
 439         mode     = get_irn_mode(irn);
 440         block    = get_nodes_block(irn);
 441         noreg_gp = ia32_new_NoReg_gp(cg);
 442         noreg_fp = ia32_new_NoReg_fp(cg);
 443
 444         DBG((mod, LEVEL_1, "checking for AM\n"));
 445
 446         /* 1st part: check for address calculations and transform the into Lea */
 447
 448         /* Following cases can occur: */
 449         /* - Sub (l, imm) -> LEA [base - offset] */
 450         /* - Sub (l, r == LEA with ia32_am_O)   -> LEA [base - offset] */
 451         /* - Add (l, imm) -> LEA [base + offset] */
 452         /* - Add (l, r == LEA with ia32_am_O)  -> LEA [base + offset] */
 453         /* - Add (l == LEA with ia32_am_O, r)  -> LEA [base + offset] */
 454         /* - Add (l, r) -> LEA [base + index * scale] */
 455         /*              with scale > 1 iff l/r == shl (1,2,3) */
 456
 457         if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
 458                 left  = get_irn_n(irn, 2);
 459                 right = get_irn_n(irn, 3);
 460
 461             /* Do not try to create a LEA if one of the operands is a Load. */
 462                 if (! pred_is_specific_node(left,  is_ia32_Load)  &&
 463                         ! pred_is_specific_node(right, is_ia32_Load))
 464                 {
 465                         res = fold_addr(irn, mod, noreg_gp);
 466                 }
 467         }
 468
 469         /* 2nd part: fold following patterns:
 470         /* - Load  -> LEA into Load  } TODO: If the LEA is used by more than one Load/Store */
 471         /* - Store -> LEA into Store }       it might be better to keep the LEA             */
 472         /* - op -> Load into AMop with am_Source
 473         /*   conditions:                */
 474         /*     - op is am_Source capable AND   */
 475         /*     - the Load is only used by this op AND */
 476         /*     - the Load is in the same block */
 477         /* - Store -> op -> Load  into AMop with am_Dest  */
 478         /*   conditions:                */
 479         /*     - op is am_Dest capable AND   */
 480         /*     - the Store uses the same address as the Load AND */
 481         /*     - the Load is only used by this op AND */
 482         /*     - the Load and Store are in the same block AND  */
 483         /*     - nobody else uses the result of the op */
 484
 485         if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
 486                 /* 1st: check for Load/Store -> LEA   */
 487                 if (is_ia32_Load(irn)  || is_ia32_fLoad(irn) ||
 488                         is_ia32_Store(irn) || is_ia32_fStore(irn))
 489                 {
 490                         left = get_irn_n(irn, 0);
 491
 492                         if (is_ia32_Lea(left)) {
 493                                 /* get the AM attributes from the LEA */
 494                                 add_ia32_am_offs(irn, get_ia32_am_offs(left));
 495                                 set_ia32_am_scale(irn, get_ia32_am_scale(left));
 496                                 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 497                                 set_ia32_op_type(irn, get_ia32_op_type(left));
 498
 499                                 /* set base and index */
 500                                 set_irn_n(irn, 0, get_irn_n(left, 0));
 501                                 set_irn_n(irn, 1, get_irn_n(left, 1));
 502                         }
 503                 }
 504                 /* check if at least one operand is a Load */
 505                 else if (pred_is_specific_node(get_irn_n(irn, 2), is_ia32_Load)  ||
 506                                  pred_is_specific_node(get_irn_n(irn, 2), is_ia32_fLoad) ||
 507                                  pred_is_specific_node(get_irn_n(irn, 3), is_ia32_Load)  ||
 508                                  pred_is_specific_node(get_irn_n(irn, 3), is_ia32_fLoad))
 509                 {
 510
 511                         /* normalize commutative ops */
 512                         if (node_is_comm(irn)) {
 513                                 left  = get_irn_n(irn, 2);
 514                                 right = get_irn_n(irn, 3);
 515
 516                                 /* assure that Left operand is always a Load if there is one */
 517                                 if (pred_is_specific_node(right, is_ia32_Load) ||
 518                                         pred_is_specific_node(right, is_ia32_fLoad))
 519                                 {
 520                                         set_irn_n(irn, 2, right);
 521                                         set_irn_n(irn, 3, left);
 522
 523                                         temp  = left;
 524                                         left  = right;
 525                                         right = temp;
 526                                 }
 527                         }
 528
 529                         /* check for Store -> op -> Load */
 530
 531                         /* Store -> op -> Load optimization is only possible if supported by op */
 532                         if (get_ia32_am_support(irn) & ia32_am_Dest) {
 533
 534                                 /* An address mode capable op always has a result Proj.                  */
 535                                 /* If this Proj is used by more than one other node, we don't need to    */
 536                                 /* check further, otherwise we check for Store and remember the address, */
 537                                 /* the Store points to. */
 538
 539                                 succ = get_edge_src_irn(get_irn_out_edge_first(irn));
 540                                 assert(is_Proj(succ) && "successor of AM node is not Proj");
 541
 542                                 if (get_Proj_proj(succ) != 0) {
 543                                         succ = get_edge_src_irn(get_irn_out_edge_next(irn, get_irn_out_edge_first(irn)));
 544                                         assert(is_Proj(succ) && "successor of AM node is not Proj");
 545                                         assert(get_Proj_proj(succ) == 0 && "Couldn't find result proj");
 546                                 }
 547
 548                                 addr_b = NULL;
 549                                 addr_i = NULL;
 550                                 store  = NULL;
 551
 552                                 /* now check for users and Store */
 553                                 if (get_irn_n_edges(succ) == 1) {
 554                                         succ = get_edge_src_irn(get_irn_out_edge_first(succ));
 555
 556                                         if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
 557                                                 store  = succ;
 558                                                 addr_b = get_irn_n(store, 0);
 559
 560                                                 /* Could be that the Store is connected to the address    */
 561                                                 /* calculating LEA while the Load is already transformed. */
 562                                                 if (is_ia32_Lea(addr_b)) {
 563                                                         succ   = addr_b;
 564                                                         addr_b = get_irn_n(succ, 0);
 565                                                         addr_i = get_irn_n(succ, 1);
 566                                                 }
 567                                                 else {
 568                                                         addr_i = noreg_gp;
 569                                                 }
 570                                         }
 571                                 }
 572
 573                                 if (store) {
 574                                         /* we found a Store as single user: Now check for Load */
 575                                         left  = get_irn_n(irn, 2);
 576                                         right = get_irn_n(irn, 3);
 577
 578                                         /* Could be that the right operand is also a Load, so we make */
 579                                         /* sure that the "interesting" Load is always the left one    */
 580
 581                                         /* right != NoMem means, we have a "binary" operation */
 582                                         if (! is_NoMem(right) &&
 583                                                 (pred_is_specific_node(right, is_ia32_Load) ||
 584                                                  pred_is_specific_node(right, is_ia32_fLoad)))
 585                                         {
 586                                                 if ((addr_b == get_irn_n(get_Proj_pred(right), 0)) &&
 587                                                         (addr_i == get_irn_n(get_Proj_pred(right), 1)))
 588                                                 {
 589                                                         /* We exchange left and right, so it's easier to kill     */
 590                                                         /* the correct Load later and to handle unary operations. */
 591                                                         set_irn_n(irn, 2, right);
 592                                                         set_irn_n(irn, 3, left);
 593
 594                                                         temp  = left;
 595                                                         left  = right;
 596                                                         right = temp;
 597                                                 }
 598                                         }
 599
 600                                         /* skip the Proj for easier access */
 601                                         left  = get_Proj_pred(left);
 602
 603                                         /* Compare Load and Store address */
 604                                         if ((addr_b == get_irn_n(left, 0)) && (addr_i == get_irn_n(left, 1)))
 605                                         {
 606                                                 /* Left Load is from same address, so we can */
 607                                                 /* disconnect the Load and Store here        */
 608
 609                                                 /* set new base, index and attributes */
 610                                                 set_irn_n(irn, 0, addr_b);
 611                                                 set_irn_n(irn, 1, addr_i);
 612                                                 add_ia32_am_offs(irn, get_ia32_am_offs(left));
 613                                                 set_ia32_am_scale(irn, get_ia32_am_scale(left));
 614                                                 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 615                                                 set_ia32_op_type(irn, ia32_AddrModeD);
 616
 617                                                 /* connect to Load memory */
 618                                                 if (get_irn_arity(irn) == 5) {
 619                                                         /* binary AMop */
 620                                                         set_irn_n(irn, 4, get_irn_n(left, 2));
 621                                                 }
 622                                                 else {
 623                                                         /* unary AMop */
 624                                                         set_irn_n(irn, 3, get_irn_n(left, 2));
 625                                                 }
 626
 627                                                 /* disconnect from Load */
 628                                                 set_irn_n(irn, 2, noreg_gp);
 629
 630                                                 /* connect the memory Proj of the Store to the op */
 631                                                 mem_proj = get_mem_proj(store);
 632                                                 set_Proj_pred(mem_proj, irn);
 633                                                 set_Proj_proj(mem_proj, 1);
 634                                         }
 635                                 } /* if (store) */
 636                                 else if (get_ia32_am_support(irn) & ia32_am_Source) {
 637                                         /* There was no store, check if we still can optimize for source address mode */
 638                                         check_am_src = 1;
 639                                 }
 640                         } /* if (support AM Dest) */
 641                         else {
 642                                 /* op doesn't support am AM Dest -> check for AM Source */
 643                                 check_am_src = 1;
 644                         }
 645
 646                         /* optimize op -> Load iff Load is only used by this op */
 647                         if (check_am_src) {
 648                                 left = get_irn_n(irn, 2);
 649
 650                                 if (get_irn_n_edges(left) == 1) {
 651                                         left = get_Proj_pred(left);
 652
 653                                         addr_b = get_irn_n(left, 0);
 654                                         addr_i = get_irn_n(left, 1);
 655
 656                                         /* set new base, index and attributes */
 657                                         set_irn_n(irn, 0, addr_b);
 658                                         set_irn_n(irn, 1, addr_i);
 659                                         add_ia32_am_offs(irn, get_ia32_am_offs(left));
 660                                         set_ia32_am_scale(irn, get_ia32_am_scale(left));
 661                                         set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
 662                                         set_ia32_op_type(irn, ia32_AddrModeS);
 663
 664                                         /* connect to Load memory */
 665                                         if (get_irn_arity(irn) == 5) {
 666                                                 /* binary AMop */
 667                                                 set_irn_n(irn, 4, get_irn_n(left, 2));
 668                                         }
 669                                         else {
 670                                                 /* unary AMop */
 671                                                 set_irn_n(irn, 3, get_irn_n(left, 2));
 672                                         }
 673
 674                                         /* disconnect from Load */
 675                                         set_irn_n(irn, 2, noreg_gp);
 676
 677                                         /* If Load has a memory Proj, connect it to the op */
 678                                         mem_proj = get_mem_proj(left);
 679                                         if (mem_proj) {
 680                                                 set_Proj_pred(mem_proj, irn);
 681                                                 set_Proj_proj(mem_proj, 1);
 682                                         }
 683                                 }
 684                         }
 685                 }
 686         }
 687 }