3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universitaet Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
28 #include "../benode_t.h"
29 #include "../besched_t.h"
31 #include "ia32_new_nodes.h"
32 #include "bearch_ia32_t.h"
33 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "ia32_transform.h"
35 #include "ia32_dbg_stat.h"
36 #include "ia32_util.h"
41 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
42 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
43 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
44 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
47 typedef int is_op_func_t(const ir_node *n);
48 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
51 * checks if a node represents the NOREG value
53 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
54 be_abi_irg_t *babi = cg->birg->abi;
55 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
56 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
58 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
59 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
64 /*************************************************
67 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
68 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
69 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
70 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
72 *************************************************/
75 * creates a unique ident by adding a number to a tag
77 * @param tag the tag string, must contain a %d if a number
80 static ident *unique_id(const char *tag)
82 static unsigned id = 0;
85 snprintf(str, sizeof(str), tag, ++id);
86 return new_id_from_str(str);
90 * Transforms a SymConst.
92 * @param mod the debug module
93 * @param block the block the new node should belong to
94 * @param node the ir SymConst node
95 * @param mode mode of the SymConst
96 * @return the created ia32 Const node
98 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
99 dbg_info *dbg = env->dbg;
100 ir_mode *mode = env->mode;
101 ir_graph *irg = env->irg;
102 ir_node *block = env->block;
105 if (mode_is_float(mode)) {
107 if (USE_SSE2(env->cg))
108 cnst = new_rd_ia32_xConst(dbg, irg, block, mode);
110 cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
113 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
115 set_ia32_Const_attr(cnst, env->irn);
121 * Get a primitive type for a mode.
123 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
125 pmap_entry *e = pmap_find(types, mode);
130 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
131 res = new_type_primitive(new_id_from_str(buf), mode);
132 pmap_insert(types, mode, res);
140 * Get an entity that is initialized with a tarval
142 static ir_entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
144 tarval *tv = get_Const_tarval(cnst);
145 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
150 ir_mode *mode = get_irn_mode(cnst);
151 ir_type *tp = get_Const_type(cnst);
152 if (tp == firm_unknown_type)
153 tp = get_prim_type(cg->isa->types, mode);
155 res = new_entity(get_glob_type(), unique_id(".LC%u"), tp);
157 set_entity_ld_ident(res, get_entity_ident(res));
158 set_entity_visibility(res, visibility_local);
159 set_entity_variability(res, variability_constant);
160 set_entity_allocation(res, allocation_static);
162 /* we create a new entity here: It's initialization must resist on the
164 rem = current_ir_graph;
165 current_ir_graph = get_const_code_irg();
166 set_atomic_ent_value(res, new_Const_type(tv, tp));
167 current_ir_graph = rem;
169 pmap_insert(cg->isa->tv_ent, tv, res);
177 * Transforms a Const.
179 * @param mod the debug module
180 * @param block the block the new node should belong to
181 * @param node the ir Const node
182 * @param mode mode of the Const
183 * @return the created ia32 Const node
185 static ir_node *gen_Const(ia32_transform_env_t *env) {
186 ir_node *cnst, *load;
188 ir_graph *irg = env->irg;
189 ir_node *block = env->block;
190 ir_node *node = env->irn;
191 dbg_info *dbg = env->dbg;
192 ir_mode *mode = env->mode;
193 ir_node *start_block = get_irg_start_block(irg);
195 if (mode_is_float(mode)) {
197 if (! USE_SSE2(env->cg)) {
198 cnst_classify_t clss = classify_Const(node);
200 if (clss == CNST_NULL)
201 return new_rd_ia32_vfldz(dbg, irg, block, mode);
202 else if (clss == CNST_ONE)
203 return new_rd_ia32_vfld1(dbg, irg, block, mode);
205 sym.entity_p = get_entity_for_tv(env->cg, node);
208 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
209 load = new_r_Load(irg, block, get_irg_no_mem(irg), cnst, mode);
210 load = new_r_Proj(irg, block, load, mode, pn_Load_res);
213 cnst = gen_SymConst(env);
215 if (start_block == block)
216 add_irn_dep(cnst, be_abi_get_start_barrier(env->cg->birg->abi));
218 set_Load_ptr(get_Proj_pred(load), cnst);
222 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
224 if (start_block == block)
225 add_irn_dep(cnst, be_abi_get_start_barrier(env->cg->birg->abi));
227 set_ia32_Const_attr(cnst, node);
234 * Transforms (all) Const's into ia32_Const and places them in the
235 * block where they are used (or in the cfg-pred Block in case of Phi's).
236 * Additionally all reference nodes are changed into mode_Is nodes.
237 * NOTE: irn must be a firm constant!
239 static void ia32_transform_const(ir_node *irn, void *env) {
240 ia32_code_gen_t *cg = env;
241 ir_node *cnst = NULL;
242 ia32_transform_env_t tenv;
246 tenv.mode = get_irn_mode(irn);
247 tenv.dbg = get_irn_dbg_info(irn);
249 DEBUG_ONLY(tenv.mod = cg->mod;)
252 /* place const either in the smallest dominator of all its users or the original block */
253 if (cg->opt & IA32_OPT_PLACECNST)
254 tenv.block = node_users_smallest_common_dominator(irn, 1);
256 tenv.block = get_nodes_block(irn);
258 /* Actually, there is no real sense in placing */
259 /* the Consts in the successor of the start block. */
261 ir_node *afterstart = NULL;
262 ir_node *startblock = get_irg_start_block(tenv.irg);
263 const ir_edge_t *edge;
265 foreach_block_succ(startblock, edge) {
266 ir_node *block = get_edge_src_irn(edge);
267 if (block != startblock) {
272 assert(afterstart != NULL);
273 tenv.block = afterstart;
277 switch (get_irn_opcode(irn)) {
279 cnst = gen_Const(&tenv);
282 cnst = gen_SymConst(&tenv);
285 assert(0 && "Wrong usage of ia32_transform_const!");
288 assert(cnst && "Could not create ia32 Const");
290 /* set the new ia32 const */
295 * Transform all firm consts and assure, we visit each const only once.
297 static void ia32_place_consts_walker(ir_node *irn, void *env) {
298 ia32_code_gen_t *cg = env;
300 if (! is_Const(irn) && ! is_SymConst(irn))
303 ia32_transform_const(irn, cg);
307 * Replace reference modes with mode_Iu and preserve store value modes.
309 static void ia32_set_modes(ir_node *irn, void *env) {
313 /* transform all reference nodes into mode_Iu nodes */
314 if (mode_is_reference(get_irn_mode(irn))) {
315 set_irn_mode(irn, mode_Iu);
320 * Walks over the graph, transforms all firm consts into ia32 consts
321 * and places them into the "best" block.
322 * @param cg The ia32 codegenerator object
324 static void ia32_transform_all_firm_consts(ia32_code_gen_t *cg) {
325 irg_walk_graph(cg->irg, NULL, ia32_place_consts_walker, cg);
328 /* Place all consts and change pointer arithmetics into unsigned integer arithmetics. */
329 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
331 We need to transform the consts twice:
332 - the psi condition tree transformer needs existing constants to be ia32 constants
333 - the psi condition tree transformer inserts new firm constants which need to be transformed
335 ia32_transform_all_firm_consts(cg);
336 irg_walk_graph(cg->irg, ia32_set_modes, ia32_transform_psi_cond_tree, cg);
337 ia32_transform_all_firm_consts(cg);
340 /********************************************************************************************************
341 * _____ _ _ ____ _ _ _ _ _
342 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
343 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
344 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
345 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
346 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
349 ********************************************************************************************************/
352 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
355 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
356 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
360 * Checks for potential CJmp/CJmpAM optimization candidates.
362 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
363 ir_node *cand = NULL;
364 ir_node *prev = sched_prev(irn);
366 if (is_Block(prev)) {
367 if (get_Block_n_cfgpreds(prev) == 1)
368 prev = get_Block_cfgpred(prev, 0);
373 /* The predecessor must be a ProjX. */
374 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
375 prev = get_Proj_pred(prev);
377 if (is_op_func(prev))
384 static int is_TestJmp_cand(const ir_node *irn) {
385 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
389 * Checks if two consecutive arguments of cand matches
390 * the two arguments of irn (TestJmp).
392 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
393 ir_node *in1 = get_irn_n(irn, 0);
394 ir_node *in2 = get_irn_n(irn, 1);
395 int i, n = get_irn_arity(cand);
398 for (i = 0; i < n - 1; i++) {
399 if (get_irn_n(cand, i) == in1 &&
400 get_irn_n(cand, i + 1) == in2)
408 return ia32_cnst_compare(cand, irn);
414 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
416 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
417 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
420 /* we found a possible candidate */
421 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
424 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
426 if (is_ia32_And(cand))
427 set_irn_op(irn, op_ia32_CJmpAM);
429 set_irn_op(irn, op_ia32_CJmp);
431 DB((cg->mod, LEVEL_1, "%+F\n", irn));
435 static int is_CondJmp_cand(const ir_node *irn) {
436 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
440 * Checks if the arguments of cand are the same of irn.
442 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
443 int i, n = get_irn_arity(cand);
446 for (i = 0; i < n; i++) {
447 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
454 return ia32_cnst_compare(cand, irn);
460 * Tries to replace a CondJmp by a CJmpAM
462 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
463 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
466 /* we found a possible candidate */
467 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
470 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
473 set_irn_op(irn, op_ia32_CJmpAM);
475 DB((cg->mod, LEVEL_1, "%+F\n", irn));
479 // only optimize up to 48 stores behind IncSPs
480 #define MAXPUSH_OPTIMIZE 48
483 * Tries to create pushs from IncSP,Store combinations
485 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
489 ir_node *stores[MAXPUSH_OPTIMIZE];
490 ir_node *block = get_nodes_block(irn);
491 ir_graph *irg = cg->irg;
493 ir_mode *spmode = get_irn_mode(irn);
495 memset(stores, 0, sizeof(stores));
497 assert(be_is_IncSP(irn));
499 offset = be_get_IncSP_offset(irn);
504 * We first walk the schedule after the IncSP node as long as we find
505 * suitable stores that could be transformed to a push.
506 * We save them into the stores array which is sorted by the frame offset/4
507 * attached to the node
509 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
516 // it has to be a store
517 if(!is_ia32_Store(node))
520 // it has to use our sp value
521 if(get_irn_n(node, 0) != irn)
523 // store has to be attached to NoMem
524 mem = get_irn_n(node, 3);
529 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
532 am_offs = get_ia32_am_offs(node);
533 if(am_offs == NULL) {
536 // the am_offs has to be of the form "+NUMBER"
537 if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') {
538 // we shouldn't have any cases in the compiler at the moment
539 // that produce something different from esp+XX
545 storeslot = offset / 4;
546 if(storeslot >= MAXPUSH_OPTIMIZE)
549 // storing into the same slot twice is bad (and shouldn't happen...)
550 if(stores[storeslot] != NULL)
553 // storing at half-slots is bad
557 stores[storeslot] = node;
560 curr_sp = get_irn_n(irn, 0);
562 // walk the stores in inverse order and create pushs for them
563 i = (offset / 4) - 1;
564 if(i >= MAXPUSH_OPTIMIZE) {
565 i = MAXPUSH_OPTIMIZE - 1;
568 for( ; i >= 0; --i) {
569 const arch_register_t *spreg;
572 ir_node *store = stores[i];
573 ir_node *noreg = ia32_new_NoReg_gp(cg);
575 if(store == NULL || is_Bad(store))
578 val = get_irn_n(store, 2);
579 mem = get_irn_n(store, 3);
580 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
583 push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
584 if(get_ia32_immop_type(store) != ia32_ImmNone) {
585 copy_ia32_Immop_attr(push, store);
587 sched_add_before(irn, push);
589 // create stackpointer proj
590 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
591 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
592 sched_add_before(irn, curr_sp);
595 edges_reroute(store, push, irg);
597 // we can remove the store now
598 set_irn_n(store, 0, new_Bad());
599 set_irn_n(store, 1, new_Bad());
600 set_irn_n(store, 2, new_Bad());
601 set_irn_n(store, 3, new_Bad());
607 be_set_IncSP_offset(irn, offset);
609 // can we remove the IncSP now?
611 const ir_edge_t *edge, *next;
613 foreach_out_edge_safe(irn, edge, next) {
614 ir_node *arg = get_edge_src_irn(edge);
615 int pos = get_edge_src_pos(edge);
617 set_irn_n(arg, pos, curr_sp);
620 set_irn_n(irn, 0, new_Bad());
623 set_irn_n(irn, 0, curr_sp);
628 * Tries to optimize two following IncSP.
630 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
631 ir_node *prev = be_get_IncSP_pred(irn);
632 int real_uses = get_irn_n_edges(prev);
634 if (be_is_IncSP(prev) && real_uses == 1) {
635 /* first IncSP has only one IncSP user, kill the first one */
636 int prev_offs = be_get_IncSP_offset(prev);
637 int curr_offs = be_get_IncSP_offset(irn);
639 be_set_IncSP_offset(prev, prev_offs + curr_offs);
641 /* Omit the optimized IncSP */
642 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
644 set_irn_n(prev, 0, new_Bad());
650 * Performs Peephole Optimizations.
652 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
653 ia32_code_gen_t *cg = env;
655 /* AMD CPUs want explicit compare before conditional jump */
656 if (! ARCH_AMD(cg->opt_arch)) {
657 if (is_ia32_TestJmp(irn))
658 ia32_optimize_TestJmp(irn, cg);
659 else if (is_ia32_CondJmp(irn))
660 ia32_optimize_CondJmp(irn, cg);
663 if (be_is_IncSP(irn)) {
664 // optimize_IncSP doesn't respect dependency edges yet...
665 //ia32_optimize_IncSP(irn, cg);
666 (void) ia32_optimize_IncSP;
667 if (cg->opt & IA32_OPT_PUSHARGS)
668 ia32_create_Pushs(irn, cg);
672 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
673 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
676 /******************************************************************
678 * /\ | | | | | \/ | | |
679 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
680 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
681 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
682 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
684 ******************************************************************/
691 static int node_is_ia32_comm(const ir_node *irn) {
692 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
695 static int ia32_get_irn_n_edges(const ir_node *irn) {
696 const ir_edge_t *edge;
699 foreach_out_edge(irn, edge) {
707 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
709 * @param pred The node to be checked
710 * @param is_op_func The check-function
711 * @return 1 if conditions are fulfilled, 0 otherwise
713 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
714 return is_op_func(pred);
718 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
719 * and if the predecessor is in block bl.
721 * @param bl The block
722 * @param pred The node to be checked
723 * @param is_op_func The check-function
724 * @return 1 if conditions are fulfilled, 0 otherwise
726 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
727 int (*is_op_func)(const ir_node *n))
730 pred = get_Proj_pred(pred);
731 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
740 * Checks if irn is a candidate for address calculation.
742 * - none of the operand must be a Load within the same block OR
743 * - all Loads must have more than one user OR
744 * - the irn has a frame entity (it's a former FrameAddr)
746 * @param block The block the Loads must/mustnot be in
747 * @param irn The irn to check
748 * return 1 if irn is a candidate, 0 otherwise
750 static int is_addr_candidate(const ir_node *block, const ir_node *irn) {
751 ir_node *in, *left, *right;
754 left = get_irn_n(irn, 2);
755 right = get_irn_n(irn, 3);
759 #ifndef AGGRESSIVE_AM
760 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
761 n = ia32_get_irn_n_edges(in);
762 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
767 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
768 n = ia32_get_irn_n_edges(in);
769 is_cand = (n == 1) ? 0 : is_cand; /* load with only one user: don't create LEA */
775 is_cand = get_ia32_frame_ent(irn) ? 1 : is_cand;
781 * Checks if irn is a candidate for address mode.
784 * - at least one operand has to be a Load within the same block AND
785 * - the load must not have other users than the irn AND
786 * - the irn must not have a frame entity set
788 * @param cg The ia32 code generator
789 * @param h The height information of the irg
790 * @param block The block the Loads must/mustnot be in
791 * @param irn The irn to check
792 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
794 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
795 ir_node *in, *load, *other, *left, *right;
796 int is_cand = 0, cand;
798 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
799 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
802 left = get_irn_n(irn, 2);
803 if(get_irn_arity(irn) == 5) {
805 right = get_irn_n(irn, 3);
808 assert(get_irn_arity(irn) == 4);
814 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
815 #ifndef AGGRESSIVE_AM
817 n = ia32_get_irn_n_edges(in);
818 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
823 load = get_Proj_pred(in);
826 /* 8bit Loads are not supported (for binary ops),
827 * they cannot be used with every register */
828 if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
829 assert(get_irn_arity(irn) == 5);
833 /* If there is a data dependency of other irn from load: cannot use AM */
834 if (is_cand && get_nodes_block(other) == block) {
835 other = skip_Proj(other);
836 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
837 /* this could happen in loops */
838 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
842 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
846 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
847 #ifndef AGGRESSIVE_AM
849 n = ia32_get_irn_n_edges(in);
850 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
855 load = get_Proj_pred(in);
858 /* 8bit Loads are not supported, they cannot be used with every register */
859 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
862 /* If there is a data dependency of other irn from load: cannot use load */
863 if (is_cand && get_nodes_block(other) == block) {
864 other = skip_Proj(other);
865 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
866 /* this could happen in loops */
867 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
871 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
873 /* check some special cases */
874 if (USE_SSE2(cg) && is_ia32_Conv_I2FP(irn)) {
875 const ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
876 /* SSE Conv I -> FP cvtsi2s(s|d) can only load 32 bit values */
877 if (get_mode_size_bits(tgt_mode) != 32)
878 cand = IA32_AM_CAND_NONE;
880 else if (is_ia32_Conv_I2I(irn)) {
881 const ir_mode *src_mode = get_ia32_Conv_src_mode(irn);
882 const ir_mode *tgt_mode = get_ia32_Conv_tgt_mode(irn);
883 /* we cannot load an N bit value and implicitly convert it into an M bit value if N > M */
884 if (get_mode_size_bits(src_mode) > get_mode_size_bits(tgt_mode))
885 cand = IA32_AM_CAND_NONE;
888 /* if the irn has a frame entity: we do not use address mode */
889 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
893 * Compares the base and index addr and the load/store entities
894 * and returns 1 if they are equal.
896 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
897 const ir_node *addr_b, const ir_node *addr_i)
899 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
900 ir_entity *lent = get_ia32_frame_ent(load);
901 ir_entity *sent = get_ia32_frame_ent(store);
902 ident *lid = get_ia32_am_sc(load);
903 ident *sid = get_ia32_am_sc(store);
904 char *loffs = get_ia32_am_offs(load);
905 char *soffs = get_ia32_am_offs(store);
907 /* are both entities set and equal? */
908 if (is_equal && (lent || sent))
909 is_equal = lent && sent && (lent == sent);
911 /* are address mode idents set and equal? */
912 if (is_equal && (lid || sid))
913 is_equal = lid && sid && (lid == sid);
915 /* are offsets set and equal */
916 if (is_equal && (loffs || soffs))
917 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
919 /* are the load and the store of the same mode? */
920 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
925 typedef enum _ia32_take_lea_attr {
926 IA32_LEA_ATTR_NONE = 0,
927 IA32_LEA_ATTR_BASE = (1 << 0),
928 IA32_LEA_ATTR_INDEX = (1 << 1),
929 IA32_LEA_ATTR_OFFS = (1 << 2),
930 IA32_LEA_ATTR_SCALE = (1 << 3),
931 IA32_LEA_ATTR_AMSC = (1 << 4),
932 IA32_LEA_ATTR_FENT = (1 << 5)
933 } ia32_take_lea_attr;
936 * Decides if we have to keep the LEA operand or if we can assimilate it.
938 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
939 int have_am_sc, ia32_code_gen_t *cg)
941 ir_entity *irn_ent = get_ia32_frame_ent(irn);
942 ir_entity *lea_ent = get_ia32_frame_ent(lea);
944 int is_noreg_base = be_is_NoReg(cg, base);
945 int is_noreg_index = be_is_NoReg(cg, index);
946 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
948 /* If the Add and the LEA both have a different frame entity set: keep */
949 if (irn_ent && lea_ent && (irn_ent != lea_ent))
950 return IA32_LEA_ATTR_NONE;
951 else if (! irn_ent && lea_ent)
952 ret_val |= IA32_LEA_ATTR_FENT;
954 /* If the Add and the LEA both have already an address mode symconst: keep */
955 if (have_am_sc && get_ia32_am_sc(lea))
956 return IA32_LEA_ATTR_NONE;
957 else if (get_ia32_am_sc(lea))
958 ret_val |= IA32_LEA_ATTR_AMSC;
960 /* Check the different base-index combinations */
962 if (! is_noreg_base && ! is_noreg_index) {
963 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
964 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
965 if (am_flav & ia32_O)
966 ret_val |= IA32_LEA_ATTR_OFFS;
968 ret_val |= IA32_LEA_ATTR_BASE;
971 return IA32_LEA_ATTR_NONE;
973 else if (! is_noreg_base && is_noreg_index) {
974 /* Base is set but index not */
976 /* Base points to LEA: assimilate everything */
977 if (am_flav & ia32_O)
978 ret_val |= IA32_LEA_ATTR_OFFS;
979 if (am_flav & ia32_S)
980 ret_val |= IA32_LEA_ATTR_SCALE;
981 if (am_flav & ia32_I)
982 ret_val |= IA32_LEA_ATTR_INDEX;
984 ret_val |= IA32_LEA_ATTR_BASE;
986 else if (am_flav & ia32_B ? 0 : 1) {
987 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
988 if (am_flav & ia32_O)
989 ret_val |= IA32_LEA_ATTR_OFFS;
990 if (am_flav & ia32_S)
991 ret_val |= IA32_LEA_ATTR_SCALE;
993 ret_val |= IA32_LEA_ATTR_INDEX;
996 return IA32_LEA_ATTR_NONE;
998 else if (is_noreg_base && ! is_noreg_index) {
999 /* Index is set but not base */
1001 /* Index points to LEA: assimilate everything */
1002 if (am_flav & ia32_O)
1003 ret_val |= IA32_LEA_ATTR_OFFS;
1004 if (am_flav & ia32_S)
1005 ret_val |= IA32_LEA_ATTR_SCALE;
1006 if (am_flav & ia32_B)
1007 ret_val |= IA32_LEA_ATTR_BASE;
1009 ret_val |= IA32_LEA_ATTR_INDEX;
1011 else if (am_flav & ia32_I ? 0 : 1) {
1012 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
1013 if (am_flav & ia32_O)
1014 ret_val |= IA32_LEA_ATTR_OFFS;
1015 if (am_flav & ia32_S)
1016 ret_val |= IA32_LEA_ATTR_SCALE;
1018 ret_val |= IA32_LEA_ATTR_BASE;
1021 return IA32_LEA_ATTR_NONE;
1024 assert(0 && "There must have been set base or index");
1031 * Adds res before irn into schedule if irn was scheduled.
1032 * @param irn The schedule point
1033 * @param res The node to be scheduled
1035 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
1036 if (sched_is_scheduled(irn))
1037 sched_add_before(irn, res);
1041 * Removes irn from schedule if it was scheduled. If irn is a mode_T node
1042 * all it's Projs are removed as well.
1043 * @param irn The irn to be removed from schedule
1045 static INLINE void try_remove_from_sched(ir_node *irn) {
1048 if (sched_is_scheduled(irn)) {
1049 if (get_irn_mode(irn) == mode_T) {
1050 const ir_edge_t *edge;
1051 foreach_out_edge(irn, edge) {
1052 ir_node *proj = get_edge_src_irn(edge);
1053 if (sched_is_scheduled(proj)) {
1054 set_irn_n(proj, 0, new_Bad());
1060 arity = get_irn_arity(irn);
1061 for(i = 0; i < arity; ++i) {
1062 set_irn_n(irn, i, new_Bad());
1069 * Folds Add or Sub to LEA if possible
1071 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
1072 ir_graph *irg = get_irn_irg(irn);
1073 dbg_info *dbg = get_irn_dbg_info(irn);
1074 ir_node *block = get_nodes_block(irn);
1076 ir_node *shift = NULL;
1077 ir_node *lea_o = NULL;
1078 ir_node *lea = NULL;
1080 const char *offs_cnst = NULL;
1081 char *offs_lea = NULL;
1087 ident *am_sc = NULL;
1088 ir_entity *lea_ent = NULL;
1089 ir_node *left, *right, *temp;
1090 ir_node *base, *index;
1091 int consumed_left_shift;
1092 ia32_am_flavour_t am_flav;
1093 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1095 if (is_ia32_Add(irn))
1098 left = get_irn_n(irn, 2);
1099 right = get_irn_n(irn, 3);
1101 /* "normalize" arguments in case of add with two operands */
1102 if (isadd && ! be_is_NoReg(cg, right)) {
1103 /* put LEA == ia32_am_O as right operand */
1104 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
1105 set_irn_n(irn, 2, right);
1106 set_irn_n(irn, 3, left);
1112 /* put LEA != ia32_am_O as left operand */
1113 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
1114 set_irn_n(irn, 2, right);
1115 set_irn_n(irn, 3, left);
1121 /* put SHL as left operand iff left is NOT a LEA */
1122 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
1123 set_irn_n(irn, 2, right);
1124 set_irn_n(irn, 3, left);
1137 /* check for operation with immediate */
1138 if (is_ia32_ImmConst(irn)) {
1139 DBG((mod, LEVEL_1, "\tfound op with imm const"));
1141 offs_cnst = get_ia32_cnst(irn);
1144 else if (isadd && is_ia32_ImmSymConst(irn)) {
1145 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
1149 am_sc = get_ia32_id_cnst(irn);
1150 am_sc_sign = is_ia32_am_sc_sign(irn);
1153 /* determine the operand which needs to be checked */
1154 temp = be_is_NoReg(cg, right) ? left : right;
1156 /* check if right operand is AMConst (LEA with ia32_am_O) */
1157 /* but we can only eat it up if there is no other symconst */
1158 /* because the linker won't accept two symconsts */
1159 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
1160 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
1162 offs_lea = get_ia32_am_offs(temp);
1163 am_sc = get_ia32_am_sc(temp);
1164 am_sc_sign = is_ia32_am_sc_sign(temp);
1171 else if (temp == right)
1176 /* default for add -> make right operand to index */
1179 consumed_left_shift = -1;
1181 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
1183 /* determine the operand which needs to be checked */
1185 if (is_ia32_Lea(left)) {
1187 consumed_left_shift = 0;
1190 /* check for SHL 1,2,3 */
1191 if (pred_is_specific_node(temp, is_ia32_Shl)) {
1194 if (get_ia32_Immop_tarval(temp)) {
1195 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
1198 index = get_irn_n(temp, 2);
1199 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
1201 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
1211 if (! be_is_NoReg(cg, index)) {
1212 /* if we have index, but left == right -> no base */
1213 if (left == right) {
1216 else if (consumed_left_shift == 1) {
1217 /* -> base is right operand */
1218 base = (right == lea_o) ? noreg : right;
1223 /* Try to assimilate a LEA as left operand */
1224 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1225 /* check if we can assimilate the LEA */
1226 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1228 if (take_attr == IA32_LEA_ATTR_NONE) {
1229 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1232 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1233 lea = left; /* for statistics */
1235 if (take_attr & IA32_LEA_ATTR_OFFS)
1236 offs = get_ia32_am_offs(left);
1238 if (take_attr & IA32_LEA_ATTR_AMSC) {
1239 am_sc = get_ia32_am_sc(left);
1241 am_sc_sign = is_ia32_am_sc_sign(left);
1244 if (take_attr & IA32_LEA_ATTR_SCALE)
1245 scale = get_ia32_am_scale(left);
1247 if (take_attr & IA32_LEA_ATTR_BASE)
1248 base = get_irn_n(left, 0);
1250 if (take_attr & IA32_LEA_ATTR_INDEX)
1251 index = get_irn_n(left, 1);
1253 if (take_attr & IA32_LEA_ATTR_FENT)
1254 lea_ent = get_ia32_frame_ent(left);
1258 /* ok, we can create a new LEA */
1260 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1262 /* add the old offset of a previous LEA */
1264 add_ia32_am_offs(res, offs);
1267 /* add the new offset */
1270 add_ia32_am_offs(res, offs_cnst);
1273 add_ia32_am_offs(res, offs_lea);
1277 /* either lea_O-cnst, -cnst or -lea_O */
1280 add_ia32_am_offs(res, offs_lea);
1283 sub_ia32_am_offs(res, offs_cnst);
1286 sub_ia32_am_offs(res, offs_lea);
1290 /* set the address mode symconst */
1292 set_ia32_am_sc(res, am_sc);
1294 set_ia32_am_sc_sign(res);
1297 /* copy the frame entity (could be set in case of Add */
1298 /* which was a FrameAddr) */
1299 if (lea_ent != NULL) {
1300 set_ia32_frame_ent(res, lea_ent);
1301 set_ia32_use_frame(res);
1303 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1304 if(is_ia32_use_frame(irn))
1305 set_ia32_use_frame(res);
1309 set_ia32_am_scale(res, scale);
1311 am_flav = ia32_am_N;
1312 /* determine new am flavour */
1313 if (offs || offs_cnst || offs_lea || have_am_sc) {
1316 if (! be_is_NoReg(cg, base)) {
1319 if (! be_is_NoReg(cg, index)) {
1325 set_ia32_am_flavour(res, am_flav);
1327 set_ia32_op_type(res, ia32_AddrModeS);
1329 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1331 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1333 /* we will exchange it, report here before the Proj is created */
1334 if (shift && lea && lea_o) {
1335 try_remove_from_sched(shift);
1336 try_remove_from_sched(lea);
1337 try_remove_from_sched(lea_o);
1338 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1340 else if (shift && lea) {
1341 try_remove_from_sched(shift);
1342 try_remove_from_sched(lea);
1343 DBG_OPT_LEA3(irn, lea, shift, res);
1345 else if (shift && lea_o) {
1346 try_remove_from_sched(shift);
1347 try_remove_from_sched(lea_o);
1348 DBG_OPT_LEA3(irn, lea_o, shift, res);
1350 else if (lea && lea_o) {
1351 try_remove_from_sched(lea);
1352 try_remove_from_sched(lea_o);
1353 DBG_OPT_LEA3(irn, lea_o, lea, res);
1356 try_remove_from_sched(shift);
1357 DBG_OPT_LEA2(irn, shift, res);
1360 try_remove_from_sched(lea);
1361 DBG_OPT_LEA2(irn, lea, res);
1364 try_remove_from_sched(lea_o);
1365 DBG_OPT_LEA2(irn, lea_o, res);
1368 DBG_OPT_LEA1(irn, res);
1370 /* get the result Proj of the Add/Sub */
1371 try_add_to_sched(irn, res);
1372 try_remove_from_sched(irn);
1374 assert(irn && "Couldn't find result proj");
1376 /* exchange the old op with the new LEA */
1385 * Merges a Load/Store node with a LEA.
1386 * @param irn The Load/Store node
1387 * @param lea The LEA
1389 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1390 ir_entity *irn_ent = get_ia32_frame_ent(irn);
1391 ir_entity *lea_ent = get_ia32_frame_ent(lea);
1393 /* If the irn and the LEA both have a different frame entity set: do not merge */
1394 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
1396 else if (irn_ent == NULL && lea_ent != NULL) {
1397 set_ia32_frame_ent(irn, lea_ent);
1398 set_ia32_use_frame(irn);
1401 /* get the AM attributes from the LEA */
1402 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1403 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1404 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1406 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1407 if (is_ia32_am_sc_sign(lea))
1408 set_ia32_am_sc_sign(irn);
1410 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1412 /* set base and index */
1413 set_irn_n(irn, 0, get_irn_n(lea, 0));
1414 set_irn_n(irn, 1, get_irn_n(lea, 1));
1416 try_remove_from_sched(lea);
1418 /* clear remat flag */
1419 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1421 if (is_ia32_Ld(irn))
1422 DBG_OPT_LOAD_LEA(lea, irn);
1424 DBG_OPT_STORE_LEA(lea, irn);
1429 * Sets new_right index of irn to right and new_left index to left.
1430 * Also exchange left and right
1432 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1435 set_irn_n(irn, new_right, *right);
1436 set_irn_n(irn, new_left, *left);
1442 /* this is only needed for Compares, but currently ALL nodes
1443 * have this attribute :-) */
1444 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1448 * Performs address calculation optimization (create LEAs if possible)
1450 static void optimize_lea(ir_node *irn, void *env) {
1451 ia32_code_gen_t *cg = env;
1452 ir_node *block, *noreg_gp, *left, *right;
1454 if (! is_ia32_irn(irn))
1457 /* Following cases can occur: */
1458 /* - Sub (l, imm) -> LEA [base - offset] */
1459 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1460 /* - Add (l, imm) -> LEA [base + offset] */
1461 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1462 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1463 /* - Add (l, r) -> LEA [base + index * scale] */
1464 /* with scale > 1 iff l/r == shl (1,2,3) */
1466 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1467 left = get_irn_n(irn, 2);
1468 right = get_irn_n(irn, 3);
1469 block = get_nodes_block(irn);
1470 noreg_gp = ia32_new_NoReg_gp(cg);
1472 /* Do not try to create a LEA if one of the operands is a Load. */
1473 /* check is irn is a candidate for address calculation */
1474 if (is_addr_candidate(block, irn)) {
1477 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1478 res = fold_addr(cg, irn, noreg_gp);
1481 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1483 DB((cg->mod, LEVEL_1, "not transformed\n"));
1486 else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1487 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1488 /* - Store -> LEA into Store } it might be better to keep the LEA */
1489 left = get_irn_n(irn, 0);
1491 if (is_ia32_Lea(left)) {
1492 const ir_edge_t *edge, *ne;
1495 /* merge all Loads/Stores connected to this LEA with the LEA */
1496 foreach_out_edge_safe(left, edge, ne) {
1497 src = get_edge_src_irn(edge);
1499 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1500 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1501 if (! is_ia32_got_lea(src))
1502 merge_loadstore_lea(src, left);
1503 set_ia32_got_lea(src);
1511 * Checks for address mode patterns and performs the
1512 * necessary transformations.
1513 * This function is called by a walker.
1515 static void optimize_am(ir_node *irn, void *env) {
1516 ia32_am_opt_env_t *am_opt_env = env;
1517 ia32_code_gen_t *cg = am_opt_env->cg;
1518 ir_graph *irg = get_irn_irg(irn);
1519 heights_t *h = am_opt_env->h;
1520 ir_node *block, *left, *right;
1521 ir_node *store, *load, *mem_proj;
1522 ir_node *addr_b, *addr_i;
1523 int need_exchange_on_fail = 0;
1524 ia32_am_type_t am_support;
1525 ia32_am_cand_t cand;
1526 ia32_am_cand_t orig_cand;
1528 int source_possible;
1529 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1531 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1533 if (is_ia32_Lea(irn))
1536 am_support = get_ia32_am_support(irn);
1537 block = get_nodes_block(irn);
1539 DBG((mod, LEVEL_1, "checking for AM\n"));
1541 /* fold following patterns: */
1542 /* - op -> Load into AMop with am_Source */
1544 /* - op is am_Source capable AND */
1545 /* - the Load is only used by this op AND */
1546 /* - the Load is in the same block */
1547 /* - Store -> op -> Load into AMop with am_Dest */
1549 /* - op is am_Dest capable AND */
1550 /* - the Store uses the same address as the Load AND */
1551 /* - the Load is only used by this op AND */
1552 /* - the Load and Store are in the same block AND */
1553 /* - nobody else uses the result of the op */
1554 if (get_ia32_am_support(irn) == ia32_am_None)
1557 cand = is_am_candidate(cg, h, block, irn);
1558 if (cand == IA32_AM_CAND_NONE)
1562 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1564 left = get_irn_n(irn, 2);
1565 if (get_irn_arity(irn) == 4) {
1566 /* it's an "unary" operation */
1568 assert(cand == IA32_AM_CAND_BOTH);
1570 right = get_irn_n(irn, 3);
1573 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1574 source_possible = am_support & ia32_am_Source ? 1 : 0;
1576 if (dest_possible) {
1581 /* we should only have 1 user which is a store */
1582 if (ia32_get_irn_n_edges(irn) == 1) {
1583 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1585 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1587 addr_b = get_irn_n(store, 0);
1588 addr_i = get_irn_n(store, 1);
1592 if (store == NULL) {
1597 if (dest_possible) {
1598 /* normalize nodes, we need the interesting load on the left side */
1599 if (cand & IA32_AM_CAND_RIGHT) {
1600 load = get_Proj_pred(right);
1601 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1602 exchange_left_right(irn, &left, &right, 3, 2);
1603 need_exchange_on_fail ^= 1;
1604 if (cand == IA32_AM_CAND_RIGHT)
1605 cand = IA32_AM_CAND_LEFT;
1610 if (dest_possible) {
1611 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1612 load = get_Proj_pred(left);
1614 #ifndef AGGRESSIVE_AM
1615 /* we have to be the only user of the load */
1616 if (get_irn_n_edges(left) > 1) {
1625 if (dest_possible) {
1626 /* the store has to use the loads memory or the same memory
1628 ir_node *loadmem = get_irn_n(load, 2);
1629 ir_node *storemem = get_irn_n(store, 3);
1630 assert(get_irn_mode(loadmem) == mode_M);
1631 assert(get_irn_mode(storemem) == mode_M);
1632 if(storemem != loadmem || !is_Proj(storemem)
1633 || get_Proj_pred(storemem) != load) {
1638 if (dest_possible) {
1639 /* Compare Load and Store address */
1640 if (!load_store_addr_is_equal(load, store, addr_b, addr_i))
1644 if (dest_possible) {
1645 /* all conditions fullfilled, do the transformation */
1646 assert(cand & IA32_AM_CAND_LEFT);
1648 /* set new base, index and attributes */
1649 set_irn_n(irn, 0, addr_b);
1650 set_irn_n(irn, 1, addr_i);
1651 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1652 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1653 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1654 set_ia32_op_type(irn, ia32_AddrModeD);
1655 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1656 if(is_ia32_use_frame(load))
1657 set_ia32_use_frame(irn);
1658 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1660 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1661 if (is_ia32_am_sc_sign(load))
1662 set_ia32_am_sc_sign(irn);
1664 if (is_ia32_use_frame(load))
1665 set_ia32_use_frame(irn);
1667 /* connect to Load memory and disconnect Load */
1668 if (get_irn_arity(irn) == 5) {
1670 set_irn_n(irn, 4, get_irn_n(load, 2));
1671 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1674 set_irn_n(irn, 3, get_irn_n(load, 2));
1675 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1678 set_irn_mode(irn, mode_M);
1680 /* connect the memory Proj of the Store to the op */
1681 mem_proj = ia32_get_proj_for_mode(store, mode_M);
1682 edges_reroute(mem_proj, irn, irg);
1684 /* clear remat flag */
1685 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1687 try_remove_from_sched(load);
1688 try_remove_from_sched(store);
1689 DBG_OPT_AM_D(load, store, irn);
1691 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1692 need_exchange_on_fail = 0;
1693 source_possible = 0;
1696 if (source_possible) {
1697 /* normalize ops, we need the load on the right */
1698 if(cand == IA32_AM_CAND_LEFT) {
1699 if(node_is_ia32_comm(irn)) {
1700 exchange_left_right(irn, &left, &right, 3, 2);
1701 need_exchange_on_fail ^= 1;
1702 cand = IA32_AM_CAND_RIGHT;
1704 source_possible = 0;
1709 if (source_possible) {
1710 /* all conditions fullfilled, do transform */
1711 assert(cand & IA32_AM_CAND_RIGHT);
1712 load = get_Proj_pred(right);
1714 if(get_irn_n_edges(load) > 1) {
1715 source_possible = 0;
1719 if (source_possible) {
1720 addr_b = get_irn_n(load, 0);
1721 addr_i = get_irn_n(load, 1);
1723 /* set new base, index and attributes */
1724 set_irn_n(irn, 0, addr_b);
1725 set_irn_n(irn, 1, addr_i);
1726 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1727 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1728 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1729 set_ia32_op_type(irn, ia32_AddrModeS);
1730 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1731 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1733 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1734 if (is_ia32_am_sc_sign(load))
1735 set_ia32_am_sc_sign(irn);
1737 /* clear remat flag */
1738 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1740 if (is_ia32_use_frame(load))
1741 set_ia32_use_frame(irn);
1743 /* connect to Load memory and disconnect Load */
1744 if (get_irn_arity(irn) == 5) {
1746 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
1747 set_irn_n(irn, 4, get_irn_n(load, 2));
1749 assert(get_irn_arity(irn) == 4);
1751 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1752 set_irn_n(irn, 3, get_irn_n(load, 2));
1755 DBG_OPT_AM_S(load, irn);
1757 /* If Load has a memory Proj, connect it to the op */
1758 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1759 if (mem_proj != NULL) {
1761 ir_mode *mode = get_irn_mode(irn);
1763 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1764 get_nodes_block(irn), new_Unknown(mode_T), mode, 0);
1765 set_irn_mode(irn, mode_T);
1766 edges_reroute(irn, res_proj, irg);
1767 set_Proj_pred(res_proj, irn);
1769 set_Proj_pred(mem_proj, irn);
1770 set_Proj_proj(mem_proj, 1);
1773 if(get_irn_n_edges(load) == 0) {
1774 try_remove_from_sched(load);
1776 need_exchange_on_fail = 0;
1778 DB((mod, LEVEL_1, "merged with %+F into source AM\n", load));
1781 /* was exchanged but optimize failed: exchange back */
1782 if (need_exchange_on_fail) {
1783 exchange_left_right(irn, &left, &right, 3, 2);
1788 * Performs address mode optimization.
1790 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1791 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1792 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1793 edges_deactivate(cg->irg);
1794 edges_activate(cg->irg);
1797 /* no optimizations at all */
1801 /* beware: we cannot optimize LEA and AM in one run because */
1802 /* LEA optimization adds new nodes to the irg which */
1803 /* invalidates the phase data */
1805 if (cg->opt & IA32_OPT_LEA) {
1806 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1810 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1812 if (cg->opt & IA32_OPT_DOAM) {
1813 /* we need height information for am optimization */
1814 heights_t *h = heights_new(cg->irg);
1815 ia32_am_opt_env_t env;
1820 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);