8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
25 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
27 typedef int is_op_func_t(const ir_node *n);
30 * checks if a node represents the NOREG value
32 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
33 be_abi_irg_t *babi = cg->birg->abi;
34 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
35 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
37 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
38 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
43 /*************************************************
46 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
47 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
48 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
49 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
51 *************************************************/
54 * creates a unique ident by adding a number to a tag
56 * @param tag the tag string, must contain a %d if a number
59 static ident *unique_id(const char *tag)
61 static unsigned id = 0;
64 snprintf(str, sizeof(str), tag, ++id);
65 return new_id_from_str(str);
71 * Transforms a SymConst.
73 * @param mod the debug module
74 * @param block the block the new node should belong to
75 * @param node the ir SymConst node
76 * @param mode mode of the SymConst
77 * @return the created ia32 Const node
79 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
81 dbg_info *dbg = env->dbg;
82 ir_mode *mode = env->mode;
83 ir_graph *irg = env->irg;
84 ir_node *block = env->block;
86 if (mode_is_float(mode)) {
88 if (USE_SSE2(env->cg))
89 cnst = new_rd_ia32_xConst(dbg, irg, block, mode);
91 cnst = new_rd_ia32_vfConst(dbg, irg, block, mode);
94 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
96 set_ia32_Const_attr(cnst, env->irn);
101 * Get a primitive type for a mode.
103 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
105 pmap_entry *e = pmap_find(types, mode);
110 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
111 res = new_type_primitive(new_id_from_str(buf), mode);
112 pmap_insert(types, mode, res);
120 * Get an entity that is initialized with a tarval
122 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
124 tarval *tv = get_Const_tarval(cnst);
125 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
130 ir_mode *mode = get_irn_mode(cnst);
131 ir_type *tp = get_Const_type(cnst);
132 if (tp == firm_unknown_type)
133 tp = get_prim_type(cg->isa->types, mode);
135 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
137 set_entity_ld_ident(res, get_entity_ident(res));
138 set_entity_visibility(res, visibility_local);
139 set_entity_variability(res, variability_constant);
140 set_entity_allocation(res, allocation_static);
142 /* we create a new entity here: It's initialization must resist on the
144 rem = current_ir_graph;
145 current_ir_graph = get_const_code_irg();
146 set_atomic_ent_value(res, new_Const_type(tv, tp));
147 current_ir_graph = rem;
149 pmap_insert(cg->isa->tv_ent, tv, res);
157 * Transforms a Const.
159 * @param mod the debug module
160 * @param block the block the new node should belong to
161 * @param node the ir Const node
162 * @param mode mode of the Const
163 * @return the created ia32 Const node
165 static ir_node *gen_Const(ia32_transform_env_t *env) {
168 ir_graph *irg = env->irg;
169 ir_node *block = env->block;
170 ir_node *node = env->irn;
171 dbg_info *dbg = env->dbg;
172 ir_mode *mode = env->mode;
174 if (mode_is_float(mode)) {
176 if (! USE_SSE2(env->cg)) {
177 cnst_classify_t clss = classify_Const(node);
179 if (clss == CNST_NULL)
180 return new_rd_ia32_vfldz(dbg, irg, block, mode);
181 else if (clss == CNST_ONE)
182 return new_rd_ia32_vfld1(dbg, irg, block, mode);
184 sym.entity_p = get_entity_for_tv(env->cg, node);
186 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
188 cnst = gen_SymConst(env);
191 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
192 set_ia32_Const_attr(cnst, node);
200 * Transforms (all) Const's into ia32_Const and places them in the
201 * block where they are used (or in the cfg-pred Block in case of Phi's).
202 * Additionally all reference nodes are changed into mode_Is nodes.
204 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
205 ia32_code_gen_t *cg = env;
206 ia32_transform_env_t tenv;
208 ir_node *pred, *cnst;
215 mode = get_irn_mode(irn);
217 /* transform all reference nodes into mode_Is nodes */
218 if (mode_is_reference(mode)) {
220 set_irn_mode(irn, mode);
223 tenv.block = get_nodes_block(irn);
226 DEBUG_ONLY(tenv.mod = cg->mod;)
228 /* Loop over all predecessors and check for Sym/Const nodes */
229 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
230 pred = get_irn_n(irn, i);
232 opc = get_irn_opcode(pred);
234 tenv.mode = get_irn_mode(pred);
235 tenv.dbg = get_irn_dbg_info(pred);
237 /* If it's a Phi, then we need to create the */
238 /* new Const in it's predecessor block */
240 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
243 /* put the const into the block where the original const was */
244 if (! (cg->opt & IA32_OPT_PLACECNST)) {
245 tenv.block = get_nodes_block(pred);
250 cnst = gen_Const(&tenv);
253 cnst = gen_SymConst(&tenv);
259 /* if we found a const, then set it */
261 set_irn_n(irn, i, cnst);
268 /********************************************************************************************************
269 * _____ _ _ ____ _ _ _ _ _
270 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
271 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
272 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
273 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
274 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
277 ********************************************************************************************************/
280 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
283 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
284 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
288 * Checks for potential CJmp/CJmpAM optimization candidates.
290 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
291 ir_node *cand = NULL;
292 ir_node *prev = sched_prev(irn);
294 if (is_Block(prev)) {
295 if (get_Block_n_cfgpreds(prev) == 1)
296 prev = get_Block_cfgpred(prev, 0);
301 /* The predecessor must be a ProjX. */
302 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
303 prev = get_Proj_pred(prev);
305 if (is_op_func(prev))
312 static int is_TestJmp_cand(const ir_node *irn) {
313 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
317 * Checks if two consecutive arguments of cand matches
318 * the two arguments of irn (TestJmp).
320 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
321 ir_node *in1 = get_irn_n(irn, 0);
322 ir_node *in2 = get_irn_n(irn, 1);
323 int i, n = get_irn_arity(cand);
326 for (i = 0; i < n - 1; i++) {
327 if (get_irn_n(cand, i) == in1 &&
328 get_irn_n(cand, i + 1) == in2)
336 return ia32_cnst_compare(cand, irn);
342 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
344 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
345 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
348 /* we found a possible candidate */
349 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
352 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
354 if (is_ia32_And(cand))
355 set_irn_op(irn, op_ia32_CJmpAM);
357 set_irn_op(irn, op_ia32_CJmp);
359 DB((cg->mod, LEVEL_1, "%+F\n", irn));
363 static int is_CondJmp_cand(const ir_node *irn) {
364 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
368 * Checks if the arguments of cand are the same of irn.
370 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
371 int i, n = get_irn_arity(cand);
374 for (i = 0; i < n; i++) {
375 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
382 return ia32_cnst_compare(cand, irn);
388 * Tries to replace a CondJmp by a CJmpAM
390 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
391 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
394 /* we found a possible candidate */
395 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
398 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
401 set_irn_op(irn, op_ia32_CJmp);
403 DB((cg->mod, LEVEL_1, "%+F\n", irn));
408 * Creates a Push from Store(IncSP(gp_reg_size))
410 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
411 ir_node *sp = get_irn_n(irn, 0);
412 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
413 const ir_edge_t *edge;
415 if (get_ia32_am_offs(irn) || !be_is_IncSP(sp))
418 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
419 &ia32_gp_regs[REG_GP_NOREG])
422 val = get_irn_n(irn, 2);
423 if (mode_is_float(get_irn_mode(val)))
426 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
427 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
430 /* ok, translate into Push */
431 edge = get_irn_out_edge_first(irn);
432 old_proj_M = get_edge_src_irn(edge);
434 next = sched_next(irn);
438 bl = get_nodes_block(irn);
439 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
440 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
441 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
442 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
444 /* the push must have SP out register */
445 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
447 exchange(old_proj_M, proj_M);
448 exchange(sp, proj_res);
449 sched_add_before(next, push);
450 sched_add_after(push, proj_res);
454 * Creates a Pop from IncSP(Load(sp))
456 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
457 ir_node *old_proj_M = be_get_IncSP_mem(irn);
458 ir_node *load = skip_Proj(old_proj_M);
459 ir_node *old_proj_res = NULL;
460 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
461 const ir_edge_t *edge;
462 const arch_register_t *reg, *sp;
464 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
467 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
468 &ia32_gp_regs[REG_GP_NOREG])
470 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
473 /* ok, translate into pop */
474 foreach_out_edge(load, edge) {
475 ir_node *succ = get_edge_src_irn(edge);
476 if (succ != old_proj_M) {
481 if (! old_proj_res) {
483 return; /* should not happen */
486 bl = get_nodes_block(load);
488 /* IncSP is typically scheduled after the load, so remove it first */
490 next = sched_next(old_proj_res);
491 sched_remove(old_proj_res);
494 reg = arch_get_irn_register(cg->arch_env, load);
495 sp = arch_get_irn_register(cg->arch_env, irn);
497 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
498 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
499 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
500 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
502 exchange(old_proj_M, proj_M);
503 exchange(old_proj_res, proj_res);
504 exchange(irn, proj_sp);
506 arch_set_irn_register(cg->arch_env, proj_res, reg);
507 arch_set_irn_register(cg->arch_env, proj_sp, sp);
509 sched_add_before(next, proj_sp);
510 sched_add_before(proj_sp, proj_res);
511 sched_add_before(proj_res,pop);
517 * Tries to optimize two following IncSP.
519 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
520 ir_node *prev = be_get_IncSP_pred(irn);
521 int real_uses = get_irn_n_edges(prev);
523 if (be_is_IncSP(prev) && real_uses == 1) {
524 /* first IncSP has only one IncSP user, kill the first one */
525 unsigned prev_offs = be_get_IncSP_offset(prev);
526 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
527 unsigned curr_offs = be_get_IncSP_offset(irn);
528 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
530 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
531 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
535 curr_dir = be_stack_dir_expand;
538 curr_dir = be_stack_dir_shrink;
539 be_set_IncSP_offset(prev, 0);
540 be_set_IncSP_offset(irn, (unsigned)new_ofs);
541 be_set_IncSP_direction(irn, curr_dir);
543 /* Omit the optimized IncSP */
544 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
549 * Performs Peephole Optimizations.
551 void ia32_peephole_optimization(ir_node *irn, void *env) {
552 ia32_code_gen_t *cg = env;
554 if (is_ia32_TestJmp(irn))
555 ia32_optimize_TestJmp(irn, cg);
556 else if (is_ia32_CondJmp(irn))
557 ia32_optimize_CondJmp(irn, cg);
558 else if (be_is_IncSP(irn))
559 ia32_optimize_IncSP(irn, cg);
564 /******************************************************************
566 * /\ | | | | | \/ | | |
567 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
568 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
569 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
570 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
572 ******************************************************************/
574 static int node_is_ia32_comm(const ir_node *irn) {
575 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
578 static int ia32_get_irn_n_edges(const ir_node *irn) {
579 const ir_edge_t *edge;
582 foreach_out_edge(irn, edge) {
590 * Returns the first mode_M Proj connected to irn.
592 static ir_node *get_mem_proj(const ir_node *irn) {
593 const ir_edge_t *edge;
596 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
598 foreach_out_edge(irn, edge) {
599 src = get_edge_src_irn(edge);
601 assert(is_Proj(src) && "Proj expected");
603 if (get_irn_mode(src) == mode_M)
611 * Returns the first Proj with mode != mode_M connected to irn.
613 static ir_node *get_res_proj(const ir_node *irn) {
614 const ir_edge_t *edge;
617 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
619 foreach_out_edge(irn, edge) {
620 src = get_edge_src_irn(edge);
622 assert(is_Proj(src) && "Proj expected");
624 if (get_irn_mode(src) != mode_M)
632 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
634 * @param pred The node to be checked
635 * @param is_op_func The check-function
636 * @return 1 if conditions are fulfilled, 0 otherwise
638 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
639 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
647 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
648 * and if the predecessor is in block bl.
650 * @param bl The block
651 * @param pred The node to be checked
652 * @param is_op_func The check-function
653 * @return 1 if conditions are fulfilled, 0 otherwise
655 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
656 int (*is_op_func)(const ir_node *n))
659 pred = get_Proj_pred(pred);
660 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
671 * Checks if irn is a candidate for address calculation or address mode.
673 * address calculation (AC):
674 * - none of the operand must be a Load within the same block OR
675 * - all Loads must have more than one user OR
676 * - the irn has a frame entity (it's a former FrameAddr)
679 * - at least one operand has to be a Load within the same block AND
680 * - the load must not have other users than the irn AND
681 * - the irn must not have a frame entity set
683 * @param block The block the Loads must/not be in
684 * @param irn The irn to check
685 * @param check_addr 1 if to check for address calculation, 0 otherwise
686 * return 1 if irn is a candidate for AC or AM, 0 otherwise
688 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
690 int n, is_cand = check_addr;
692 in = get_irn_n(irn, 2);
694 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
695 n = ia32_get_irn_n_edges(in);
696 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
699 in = get_irn_n(irn, 3);
701 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
702 n = ia32_get_irn_n_edges(in);
703 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
706 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
712 * Compares the base and index addr and the load/store entities
713 * and returns 1 if they are equal.
715 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
716 const ir_node *addr_b, const ir_node *addr_i)
718 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
719 entity *lent = get_ia32_frame_ent(load);
720 entity *sent = get_ia32_frame_ent(store);
721 ident *lid = get_ia32_am_sc(load);
722 ident *sid = get_ia32_am_sc(store);
723 char *loffs = get_ia32_am_offs(load);
724 char *soffs = get_ia32_am_offs(store);
726 /* are both entities set and equal? */
727 if (is_equal && (lent || sent))
728 is_equal = lent && sent && (lent == sent);
730 /* are address mode idents set and equal? */
731 if (is_equal && (lid || sid))
732 is_equal = lid && sid && (lid == sid);
734 /* are offsets set and equal */
735 if (is_equal && (loffs || soffs))
736 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
738 /* are the load and the store of the same mode? */
739 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
744 typedef enum _ia32_take_lea_attr {
745 IA32_LEA_ATTR_NONE = 0,
746 IA32_LEA_ATTR_BASE = (1 << 0),
747 IA32_LEA_ATTR_INDEX = (1 << 1),
748 IA32_LEA_ATTR_OFFS = (1 << 2),
749 IA32_LEA_ATTR_SCALE = (1 << 3),
750 IA32_LEA_ATTR_AMSC = (1 << 4),
751 IA32_LEA_ATTR_FENT = (1 << 5)
752 } ia32_take_lea_attr;
755 * Decides if we have to keep the LEA operand or if we can assimilate it.
757 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
758 int have_am_sc, ia32_code_gen_t *cg)
760 ir_node *lea_base = get_irn_n(lea, 0);
761 ir_node *lea_idx = get_irn_n(lea, 1);
762 entity *irn_ent = get_ia32_frame_ent(irn);
763 entity *lea_ent = get_ia32_frame_ent(lea);
765 int is_noreg_base = be_is_NoReg(cg, base);
766 int is_noreg_index = be_is_NoReg(cg, index);
767 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
769 /* If the Add and the LEA both have a different frame entity set: keep */
770 if (irn_ent && lea_ent && (irn_ent != lea_ent))
771 return IA32_LEA_ATTR_NONE;
772 else if (! irn_ent && lea_ent)
773 ret_val |= IA32_LEA_ATTR_FENT;
775 /* If the Add and the LEA both have already an address mode symconst: keep */
776 if (have_am_sc && get_ia32_am_sc(lea))
777 return IA32_LEA_ATTR_NONE;
778 else if (get_ia32_am_sc(lea))
779 ret_val |= IA32_LEA_ATTR_AMSC;
781 /* Check the different base-index combinations */
783 if (! is_noreg_base && ! is_noreg_index) {
784 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
785 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
786 if (am_flav & ia32_O)
787 ret_val |= IA32_LEA_ATTR_OFFS;
789 ret_val |= IA32_LEA_ATTR_BASE;
792 return IA32_LEA_ATTR_NONE;
794 else if (! is_noreg_base && is_noreg_index) {
795 /* Base is set but index not */
797 /* Base points to LEA: assimilate everything */
798 if (am_flav & ia32_O)
799 ret_val |= IA32_LEA_ATTR_OFFS;
800 if (am_flav & ia32_S)
801 ret_val |= IA32_LEA_ATTR_SCALE;
802 if (am_flav & ia32_I)
803 ret_val |= IA32_LEA_ATTR_INDEX;
805 ret_val |= IA32_LEA_ATTR_BASE;
807 else if (am_flav & ia32_B ? 0 : 1) {
808 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
809 if (am_flav & ia32_O)
810 ret_val |= IA32_LEA_ATTR_OFFS;
811 if (am_flav & ia32_S)
812 ret_val |= IA32_LEA_ATTR_SCALE;
814 ret_val |= IA32_LEA_ATTR_INDEX;
817 return IA32_LEA_ATTR_NONE;
819 else if (is_noreg_base && ! is_noreg_index) {
820 /* Index is set but not base */
822 /* Index points to LEA: assimilate everything */
823 if (am_flav & ia32_O)
824 ret_val |= IA32_LEA_ATTR_OFFS;
825 if (am_flav & ia32_S)
826 ret_val |= IA32_LEA_ATTR_SCALE;
827 if (am_flav & ia32_B)
828 ret_val |= IA32_LEA_ATTR_BASE;
830 ret_val |= IA32_LEA_ATTR_INDEX;
832 else if (am_flav & ia32_I ? 0 : 1) {
833 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
834 if (am_flav & ia32_O)
835 ret_val |= IA32_LEA_ATTR_OFFS;
836 if (am_flav & ia32_S)
837 ret_val |= IA32_LEA_ATTR_SCALE;
839 ret_val |= IA32_LEA_ATTR_BASE;
842 return IA32_LEA_ATTR_NONE;
845 assert(0 && "There must have been set base or index");
853 * Folds Add or Sub to LEA if possible
855 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
856 ir_graph *irg = get_irn_irg(irn);
857 dbg_info *dbg = get_irn_dbg_info(irn);
858 ir_node *block = get_nodes_block(irn);
860 ir_node *shift = NULL;
861 ir_node *lea_o = NULL;
864 const char *offs_cnst = NULL;
865 char *offs_lea = NULL;
872 entity *lea_ent = NULL;
873 ir_node *left, *right, *temp;
874 ir_node *base, *index;
875 ia32_am_flavour_t am_flav;
876 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
878 if (is_ia32_Add(irn))
881 left = get_irn_n(irn, 2);
882 right = get_irn_n(irn, 3);
884 /* "normalize" arguments in case of add with two operands */
885 if (isadd && ! be_is_NoReg(cg, right)) {
886 /* put LEA == ia32_am_O as right operand */
887 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
888 set_irn_n(irn, 2, right);
889 set_irn_n(irn, 3, left);
895 /* put LEA != ia32_am_O as left operand */
896 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
897 set_irn_n(irn, 2, right);
898 set_irn_n(irn, 3, left);
904 /* put SHL as left operand iff left is NOT a LEA */
905 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
906 set_irn_n(irn, 2, right);
907 set_irn_n(irn, 3, left);
920 /* check for operation with immediate */
921 if (is_ia32_ImmConst(irn)) {
922 DBG((mod, LEVEL_1, "\tfound op with imm const"));
924 offs_cnst = get_ia32_cnst(irn);
927 else if (is_ia32_ImmSymConst(irn)) {
928 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
932 am_sc = get_ia32_id_cnst(irn);
933 am_sc_sign = is_ia32_am_sc_sign(irn);
936 /* determine the operand which needs to be checked */
937 if (be_is_NoReg(cg, right)) {
944 /* check if right operand is AMConst (LEA with ia32_am_O) */
945 /* but we can only eat it up if there is no other symconst */
946 /* because the linker won't accept two symconsts */
947 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
948 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
950 offs_lea = get_ia32_am_offs(temp);
951 am_sc = get_ia32_am_sc(temp);
952 am_sc_sign = is_ia32_am_sc_sign(temp);
959 /* default for add -> make right operand to index */
963 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
965 /* determine the operand which needs to be checked */
967 if (is_ia32_Lea(left)) {
971 /* check for SHL 1,2,3 */
972 if (pred_is_specific_node(temp, is_ia32_Shl)) {
973 temp = get_Proj_pred(temp);
976 if (get_ia32_Immop_tarval(temp)) {
977 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
980 index = get_irn_n(temp, 2);
982 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
992 if (! be_is_NoReg(cg, index)) {
993 /* if we have index, but left == right -> no base */
997 else if (! is_ia32_Lea(left) && (index != right)) {
998 /* index != right -> we found a good Shl */
999 /* left != LEA -> this Shl was the left operand */
1000 /* -> base is right operand */
1006 /* Try to assimilate a LEA as left operand */
1007 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1008 /* check if we can assimilate the LEA */
1009 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1011 if (take_attr == IA32_LEA_ATTR_NONE) {
1012 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1015 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1016 lea = left; /* for statistics */
1018 if (take_attr & IA32_LEA_ATTR_OFFS)
1019 offs = get_ia32_am_offs(left);
1021 if (take_attr & IA32_LEA_ATTR_AMSC) {
1022 am_sc = get_ia32_am_sc(left);
1024 am_sc_sign = is_ia32_am_sc_sign(left);
1027 if (take_attr & IA32_LEA_ATTR_SCALE)
1028 scale = get_ia32_am_scale(left);
1030 if (take_attr & IA32_LEA_ATTR_BASE)
1031 base = get_irn_n(left, 0);
1033 if (take_attr & IA32_LEA_ATTR_INDEX)
1034 index = get_irn_n(left, 1);
1036 if (take_attr & IA32_LEA_ATTR_FENT)
1037 lea_ent = get_ia32_frame_ent(left);
1041 /* ok, we can create a new LEA */
1043 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1045 /* add the old offset of a previous LEA */
1047 add_ia32_am_offs(res, offs);
1050 /* add the new offset */
1053 add_ia32_am_offs(res, offs_cnst);
1056 add_ia32_am_offs(res, offs_lea);
1060 /* either lea_O-cnst, -cnst or -lea_O */
1063 add_ia32_am_offs(res, offs_lea);
1066 sub_ia32_am_offs(res, offs_cnst);
1069 sub_ia32_am_offs(res, offs_lea);
1073 /* set the address mode symconst */
1075 set_ia32_am_sc(res, am_sc);
1077 set_ia32_am_sc_sign(res);
1080 /* copy the frame entity (could be set in case of Add */
1081 /* which was a FrameAddr) */
1083 set_ia32_frame_ent(res, lea_ent);
1085 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1087 if (get_ia32_frame_ent(res))
1088 set_ia32_use_frame(res);
1091 set_ia32_am_scale(res, scale);
1093 am_flav = ia32_am_N;
1094 /* determine new am flavour */
1095 if (offs || offs_cnst || offs_lea) {
1098 if (! be_is_NoReg(cg, base)) {
1101 if (! be_is_NoReg(cg, index)) {
1107 set_ia32_am_flavour(res, am_flav);
1109 set_ia32_op_type(res, ia32_AddrModeS);
1111 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1113 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1115 /* we will exchange it, report here before the Proj is created */
1116 if (shift && lea && lea_o)
1117 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1118 else if (shift && lea)
1119 DBG_OPT_LEA3(irn, lea, shift, res);
1120 else if (shift && lea_o)
1121 DBG_OPT_LEA3(irn, lea_o, shift, res);
1122 else if (lea && lea_o)
1123 DBG_OPT_LEA3(irn, lea_o, lea, res);
1125 DBG_OPT_LEA2(irn, shift, res);
1127 DBG_OPT_LEA2(irn, lea, res);
1129 DBG_OPT_LEA2(irn, lea_o, res);
1131 DBG_OPT_LEA1(irn, res);
1133 /* get the result Proj of the Add/Sub */
1134 irn = get_res_proj(irn);
1136 assert(irn && "Couldn't find result proj");
1138 /* exchange the old op with the new LEA */
1147 * Merges a Load/Store node with a LEA.
1148 * @param irn The Load/Store node
1149 * @param lea The LEA
1151 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1152 entity *irn_ent = get_ia32_frame_ent(irn);
1153 entity *lea_ent = get_ia32_frame_ent(lea);
1155 /* If the irn and the LEA both have a different frame entity set: do not merge */
1156 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1158 else if (! irn_ent && lea_ent) {
1159 set_ia32_frame_ent(irn, lea_ent);
1160 set_ia32_use_frame(irn);
1163 /* get the AM attributes from the LEA */
1164 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1165 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1166 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1168 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1169 if (is_ia32_am_sc_sign(lea))
1170 set_ia32_am_sc_sign(irn);
1172 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1174 /* set base and index */
1175 set_irn_n(irn, 0, get_irn_n(lea, 0));
1176 set_irn_n(irn, 1, get_irn_n(lea, 1));
1178 /* clear remat flag */
1179 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1181 if (is_ia32_Ld(irn))
1182 DBG_OPT_LOAD_LEA(lea, irn);
1184 DBG_OPT_STORE_LEA(lea, irn);
1189 * Optimizes a pattern around irn to address mode if possible.
1191 void ia32_optimize_am(ir_node *irn, void *env) {
1192 ia32_code_gen_t *cg = env;
1196 ir_node *block, *noreg_gp, *noreg_fp;
1197 ir_node *left, *right, *temp;
1198 ir_node *store, *load, *mem_proj;
1199 ir_node *succ, *addr_b, *addr_i;
1200 int check_am_src = 0;
1201 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1203 if (! is_ia32_irn(irn))
1206 dbg = get_irn_dbg_info(irn);
1207 mode = get_irn_mode(irn);
1208 block = get_nodes_block(irn);
1209 noreg_gp = ia32_new_NoReg_gp(cg);
1210 noreg_fp = ia32_new_NoReg_fp(cg);
1212 DBG((mod, LEVEL_1, "checking for AM\n"));
1214 /* 1st part: check for address calculations and transform the into Lea */
1216 /* Following cases can occur: */
1217 /* - Sub (l, imm) -> LEA [base - offset] */
1218 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1219 /* - Add (l, imm) -> LEA [base + offset] */
1220 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1221 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1222 /* - Add (l, r) -> LEA [base + index * scale] */
1223 /* with scale > 1 iff l/r == shl (1,2,3) */
1225 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1226 left = get_irn_n(irn, 2);
1227 right = get_irn_n(irn, 3);
1229 /* Do not try to create a LEA if one of the operands is a Load. */
1230 /* check is irn is a candidate for address calculation */
1231 if (is_candidate(block, irn, 1)) {
1232 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1233 res = fold_addr(cg, irn, noreg_gp);
1236 DB((mod, LEVEL_1, "transformed into %+F\n", res));
1238 DB((mod, LEVEL_1, "not transformed\n"));
1242 /* 2nd part: fold following patterns: */
1243 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1244 /* - Store -> LEA into Store } it might be better to keep the LEA */
1245 /* - op -> Load into AMop with am_Source */
1247 /* - op is am_Source capable AND */
1248 /* - the Load is only used by this op AND */
1249 /* - the Load is in the same block */
1250 /* - Store -> op -> Load into AMop with am_Dest */
1252 /* - op is am_Dest capable AND */
1253 /* - the Store uses the same address as the Load AND */
1254 /* - the Load is only used by this op AND */
1255 /* - the Load and Store are in the same block AND */
1256 /* - nobody else uses the result of the op */
1258 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
1259 /* 1st: check for Load/Store -> LEA */
1260 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1261 left = get_irn_n(irn, 0);
1263 if (is_ia32_Lea(left)) {
1264 const ir_edge_t *edge, *ne;
1267 /* merge all Loads/Stores connected to this LEA with the LEA */
1268 foreach_out_edge_safe(left, edge, ne) {
1269 src = get_edge_src_irn(edge);
1271 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1272 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1273 merge_loadstore_lea(src, left);
1278 /* check if the node is an address mode candidate */
1279 else if (is_candidate(block, irn, 0)) {
1280 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1282 left = get_irn_n(irn, 2);
1283 if (get_irn_arity(irn) == 4) {
1284 /* it's an "unary" operation */
1288 right = get_irn_n(irn, 3);
1291 /* normalize commutative ops */
1292 if (node_is_ia32_comm(irn)) {
1293 /* Assure that right operand is always a Load if there is one */
1294 /* because non-commutative ops can only use Dest AM if the right */
1295 /* operand is a load, so we only need to check right operand. */
1296 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1298 set_irn_n(irn, 2, right);
1299 set_irn_n(irn, 3, left);
1307 /* check for Store -> op -> Load */
1309 /* Store -> op -> Load optimization is only possible if supported by op */
1310 /* and if right operand is a Load */
1311 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1312 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1315 /* An address mode capable op always has a result Proj. */
1316 /* If this Proj is used by more than one other node, we don't need to */
1317 /* check further, otherwise we check for Store and remember the address, */
1318 /* the Store points to. */
1320 succ = get_res_proj(irn);
1321 assert(succ && "Couldn't find result proj");
1327 /* now check for users and Store */
1328 if (ia32_get_irn_n_edges(succ) == 1) {
1329 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1331 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1333 addr_b = get_irn_n(store, 0);
1334 addr_i = get_irn_n(store, 1);
1339 /* we found a Store as single user: Now check for Load */
1341 /* Extra check for commutative ops with two Loads */
1342 /* -> put the interesting Load right */
1343 if (node_is_ia32_comm(irn) &&
1344 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1346 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1347 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1349 /* We exchange left and right, so it's easier to kill */
1350 /* the correct Load later and to handle unary operations. */
1351 set_irn_n(irn, 2, right);
1352 set_irn_n(irn, 3, left);
1360 /* skip the Proj for easier access */
1361 load = get_Proj_pred(right);
1363 /* Compare Load and Store address */
1364 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1365 /* Right Load is from same address, so we can */
1366 /* disconnect the Load and Store here */
1368 /* set new base, index and attributes */
1369 set_irn_n(irn, 0, addr_b);
1370 set_irn_n(irn, 1, addr_i);
1371 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1372 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1373 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1374 set_ia32_op_type(irn, ia32_AddrModeD);
1375 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1376 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1378 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1379 if (is_ia32_am_sc_sign(load))
1380 set_ia32_am_sc_sign(irn);
1382 if (is_ia32_use_frame(load))
1383 set_ia32_use_frame(irn);
1385 /* connect to Load memory and disconnect Load */
1386 if (get_irn_arity(irn) == 5) {
1388 set_irn_n(irn, 4, get_irn_n(load, 2));
1389 set_irn_n(irn, 3, noreg_gp);
1393 set_irn_n(irn, 3, get_irn_n(load, 2));
1394 set_irn_n(irn, 2, noreg_gp);
1397 /* connect the memory Proj of the Store to the op */
1398 mem_proj = get_mem_proj(store);
1399 set_Proj_pred(mem_proj, irn);
1400 set_Proj_proj(mem_proj, 1);
1402 /* clear remat flag */
1403 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1405 DBG_OPT_AM_D(load, store, irn);
1407 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1410 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1411 /* There was no store, check if we still can optimize for source address mode */
1414 } /* if (support AM Dest) */
1415 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1416 /* op doesn't support am AM Dest -> check for AM Source */
1420 /* normalize commutative ops */
1421 if (node_is_ia32_comm(irn)) {
1422 /* Assure that left operand is always a Load if there is one */
1423 /* because non-commutative ops can only use Source AM if the */
1424 /* left operand is a Load, so we only need to check the left */
1425 /* operand afterwards. */
1426 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1427 set_irn_n(irn, 2, right);
1428 set_irn_n(irn, 3, left);
1436 /* optimize op -> Load iff Load is only used by this op */
1437 /* and left operand is a Load which only used by this irn */
1439 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1440 (ia32_get_irn_n_edges(left) == 1))
1442 left = get_Proj_pred(left);
1444 addr_b = get_irn_n(left, 0);
1445 addr_i = get_irn_n(left, 1);
1447 /* set new base, index and attributes */
1448 set_irn_n(irn, 0, addr_b);
1449 set_irn_n(irn, 1, addr_i);
1450 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1451 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1452 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1453 set_ia32_op_type(irn, ia32_AddrModeS);
1454 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1455 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1457 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1458 if (is_ia32_am_sc_sign(left))
1459 set_ia32_am_sc_sign(irn);
1461 /* clear remat flag */
1462 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1464 if (is_ia32_use_frame(left))
1465 set_ia32_use_frame(irn);
1467 /* connect to Load memory */
1468 if (get_irn_arity(irn) == 5) {
1470 set_irn_n(irn, 4, get_irn_n(left, 2));
1474 set_irn_n(irn, 3, get_irn_n(left, 2));
1477 /* disconnect from Load */
1478 set_irn_n(irn, 2, noreg_gp);
1480 DBG_OPT_AM_S(left, irn);
1482 /* If Load has a memory Proj, connect it to the op */
1483 mem_proj = get_mem_proj(left);
1485 set_Proj_pred(mem_proj, irn);
1486 set_Proj_proj(mem_proj, 1);
1489 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));