2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Christian Wuerdig
33 #include "firm_types.h"
43 #include "../benode_t.h"
44 #include "../besched_t.h"
46 #include "ia32_new_nodes.h"
47 #include "bearch_ia32_t.h"
48 #include "gen_ia32_regalloc_if.h"
49 #include "ia32_transform.h"
50 #include "ia32_dbg_stat.h"
51 #include "ia32_util.h"
53 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
55 //#define AGGRESSIVE_AM
58 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
59 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
60 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
61 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
64 typedef int is_op_func_t(const ir_node *n);
65 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
68 * checks if a node represents the NOREG value
70 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
71 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
74 /********************************************************************************************************
75 * _____ _ _ ____ _ _ _ _ _
76 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
77 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
78 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
79 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
80 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
83 ********************************************************************************************************/
86 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
89 // only optimize up to 48 stores behind IncSPs
90 #define MAXPUSH_OPTIMIZE 48
93 * Tries to create pushs from IncSP,Store combinations
95 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
99 ir_node *stores[MAXPUSH_OPTIMIZE];
100 ir_node *block = get_nodes_block(irn);
101 ir_graph *irg = cg->irg;
103 ir_mode *spmode = get_irn_mode(irn);
105 memset(stores, 0, sizeof(stores));
107 assert(be_is_IncSP(irn));
109 offset = be_get_IncSP_offset(irn);
114 * We first walk the schedule after the IncSP node as long as we find
115 * suitable stores that could be transformed to a push.
116 * We save them into the stores array which is sorted by the frame offset/4
117 * attached to the node
119 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
124 // it has to be a store
125 if(!is_ia32_Store(node))
128 // it has to use our sp value
129 if(get_irn_n(node, 0) != irn)
131 // store has to be attached to NoMem
132 mem = get_irn_n(node, 3);
137 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
140 offset = get_ia32_am_offs_int(node);
142 storeslot = offset / 4;
143 if(storeslot >= MAXPUSH_OPTIMIZE)
146 // storing into the same slot twice is bad (and shouldn't happen...)
147 if(stores[storeslot] != NULL)
150 // storing at half-slots is bad
154 stores[storeslot] = node;
157 curr_sp = get_irn_n(irn, 0);
159 // walk the stores in inverse order and create pushs for them
160 i = (offset / 4) - 1;
161 if(i >= MAXPUSH_OPTIMIZE) {
162 i = MAXPUSH_OPTIMIZE - 1;
165 for( ; i >= 0; --i) {
166 const arch_register_t *spreg;
168 ir_node *val, *mem, *mem_proj;
169 ir_node *store = stores[i];
170 ir_node *noreg = ia32_new_NoReg_gp(cg);
172 if(store == NULL || is_Bad(store))
175 val = get_irn_n(store, 2);
176 mem = get_irn_n(store, 3);
177 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
179 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, val, curr_sp, mem);
181 set_ia32_am_support(push, ia32_am_Source, ia32_am_unary);
182 copy_ia32_Immop_attr(push, store);
184 sched_add_before(irn, push);
186 // create stackpointer proj
187 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
188 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
189 #ifdef SCHEDULE_PROJS
190 sched_add_before(irn, curr_sp);
192 // create memory proj
193 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
195 // use the memproj now
196 exchange(store, mem_proj);
198 // we can remove the store now
204 be_set_IncSP_offset(irn, offset);
206 // can we remove the IncSP now?
208 const ir_edge_t *edge, *next;
210 foreach_out_edge_safe(irn, edge, next) {
211 ir_node *arg = get_edge_src_irn(edge);
212 int pos = get_edge_src_pos(edge);
214 set_irn_n(arg, pos, curr_sp);
217 set_irn_n(irn, 0, new_Bad());
220 set_irn_n(irn, 0, curr_sp);
225 * Tries to optimize two following IncSP.
227 static void ia32_optimize_IncSP(ir_node *node)
232 ir_node *pred = be_get_IncSP_pred(node);
235 if(!be_is_IncSP(pred))
238 if(get_irn_n_edges(pred) > 1)
241 pred_offs = be_get_IncSP_offset(pred);
242 curr_offs = be_get_IncSP_offset(node);
244 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
245 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
249 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
250 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
254 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
255 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
258 offs = curr_offs + pred_offs;
261 be_set_IncSP_offset(node, offs);
263 /* rewire dependency edges */
264 predpred = be_get_IncSP_pred(pred);
265 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
268 be_set_IncSP_pred(node, predpred);
274 * Performs Peephole Optimizations.
276 static void ia32_peephole_optimize_node(ir_node *node, void *env) {
277 ia32_code_gen_t *cg = env;
279 if (be_is_IncSP(node)) {
280 ia32_optimize_IncSP(node);
282 if (cg->opt & IA32_OPT_PUSHARGS)
283 ia32_create_Pushs(node, cg);
287 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
288 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
291 /******************************************************************
293 * /\ | | | | | \/ | | |
294 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
295 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
296 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
297 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
299 ******************************************************************/
306 static int node_is_ia32_comm(const ir_node *irn) {
307 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
310 static int ia32_get_irn_n_edges(const ir_node *irn) {
311 const ir_edge_t *edge;
314 foreach_out_edge(irn, edge) {
322 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
324 * @param pred The node to be checked
325 * @param is_op_func The check-function
326 * @return 1 if conditions are fulfilled, 0 otherwise
328 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
329 return is_op_func(pred);
333 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
334 * and if the predecessor is in block bl.
336 * @param bl The block
337 * @param pred The node to be checked
338 * @param is_op_func The check-function
339 * @return 1 if conditions are fulfilled, 0 otherwise
341 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
342 int (*is_op_func)(const ir_node *n))
345 pred = get_Proj_pred(pred);
346 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
355 * Checks if irn is a candidate for address calculation. We avoid transforming
356 * adds to leas if they have a load as pred, because then we can use AM mode
359 * - none of the operand must be a Load within the same block OR
360 * - all Loads must have more than one user OR
362 * @param block The block the Loads must/mustnot be in
363 * @param irn The irn to check
364 * return 1 if irn is a candidate, 0 otherwise
366 static int is_addr_candidate(const ir_node *irn)
368 #ifndef AGGRESSIVE_AM
369 const ir_node *block = get_nodes_block(irn);
370 ir_node *left, *right;
373 left = get_irn_n(irn, 2);
374 right = get_irn_n(irn, 3);
376 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
377 n = ia32_get_irn_n_edges(left);
378 /* load with only one user: don't create LEA */
383 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
384 n = ia32_get_irn_n_edges(right);
395 * Checks if irn is a candidate for address mode.
398 * - at least one operand has to be a Load within the same block AND
399 * - the load must not have other users than the irn AND
400 * - the irn must not have a frame entity set
402 * @param cg The ia32 code generator
403 * @param h The height information of the irg
404 * @param block The block the Loads must/mustnot be in
405 * @param irn The irn to check
406 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
408 static ia32_am_cand_t is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
409 ir_node *in, *load, *other, *left, *right;
410 int is_cand = 0, cand;
413 if (is_ia32_Ld(irn) || is_ia32_St(irn) ||
414 is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
415 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
418 if(get_ia32_frame_ent(irn) != NULL)
419 return IA32_AM_CAND_NONE;
421 left = get_irn_n(irn, 2);
422 arity = get_irn_arity(irn);
423 if(get_ia32_am_arity(irn) == ia32_am_binary) {
425 right = get_irn_n(irn, 3);
427 assert(get_ia32_am_arity(irn) == ia32_am_unary);
434 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
435 #ifndef AGGRESSIVE_AM
437 n = ia32_get_irn_n_edges(in);
438 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
443 load = get_Proj_pred(in);
446 /* 8bit Loads are not supported (for binary ops),
447 * they cannot be used with every register */
448 if (get_ia32_am_arity(irn) == ia32_am_binary &&
449 get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
453 /* If there is a data dependency of other irn from load: cannot use AM */
454 if (is_cand && get_nodes_block(other) == block) {
455 other = skip_Proj(other);
456 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
457 /* this could happen in loops */
458 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
462 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
466 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
467 #ifndef AGGRESSIVE_AM
469 n = ia32_get_irn_n_edges(in);
470 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
475 load = get_Proj_pred(in);
478 /* 8bit Loads are not supported, they cannot be used with every register */
479 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
482 /* If there is a data dependency of other irn from load: cannot use load */
483 if (is_cand && get_nodes_block(other) == block) {
484 other = skip_Proj(other);
485 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
486 /* this could happen in loops */
487 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
491 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
493 /* if the irn has a frame entity: we do not use address mode */
498 * Compares the base and index addr and the load/store entities
499 * and returns 1 if they are equal.
501 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
502 const ir_node *addr_b, const ir_node *addr_i)
504 if(get_irn_n(load, 0) != addr_b)
506 if(get_irn_n(load, 1) != addr_i)
509 if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
512 if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
514 if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
516 if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
518 if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
524 typedef enum _ia32_take_lea_attr {
525 IA32_LEA_ATTR_NONE = 0,
526 IA32_LEA_ATTR_BASE = (1 << 0),
527 IA32_LEA_ATTR_INDEX = (1 << 1),
528 IA32_LEA_ATTR_OFFS = (1 << 2),
529 IA32_LEA_ATTR_SCALE = (1 << 3),
530 IA32_LEA_ATTR_AMSC = (1 << 4),
531 IA32_LEA_ATTR_FENT = (1 << 5)
532 } ia32_take_lea_attr;
535 * Decides if we have to keep the LEA operand or if we can assimilate it.
537 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
538 int have_am_sc, ia32_code_gen_t *cg)
540 ir_entity *irn_ent = get_ia32_frame_ent(irn);
541 ir_entity *lea_ent = get_ia32_frame_ent(lea);
543 int is_noreg_base = be_is_NoReg(cg, base);
544 int is_noreg_index = be_is_NoReg(cg, index);
545 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
547 /* If the Add and the LEA both have a different frame entity set: keep */
548 if (irn_ent && lea_ent && (irn_ent != lea_ent))
549 return IA32_LEA_ATTR_NONE;
550 else if (! irn_ent && lea_ent)
551 ret_val |= IA32_LEA_ATTR_FENT;
553 /* If the Add and the LEA both have already an address mode symconst: keep */
554 if (have_am_sc && get_ia32_am_sc(lea))
555 return IA32_LEA_ATTR_NONE;
556 else if (get_ia32_am_sc(lea))
557 ret_val |= IA32_LEA_ATTR_AMSC;
559 /* Check the different base-index combinations */
561 if (! is_noreg_base && ! is_noreg_index) {
562 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
563 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
564 if (am_flav & ia32_O)
565 ret_val |= IA32_LEA_ATTR_OFFS;
567 ret_val |= IA32_LEA_ATTR_BASE;
570 return IA32_LEA_ATTR_NONE;
572 else if (! is_noreg_base && is_noreg_index) {
573 /* Base is set but index not */
575 /* Base points to LEA: assimilate everything */
576 if (am_flav & ia32_O)
577 ret_val |= IA32_LEA_ATTR_OFFS;
578 if (am_flav & ia32_S)
579 ret_val |= IA32_LEA_ATTR_SCALE;
580 if (am_flav & ia32_I)
581 ret_val |= IA32_LEA_ATTR_INDEX;
583 ret_val |= IA32_LEA_ATTR_BASE;
585 else if (am_flav & ia32_B ? 0 : 1) {
586 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
587 if (am_flav & ia32_O)
588 ret_val |= IA32_LEA_ATTR_OFFS;
589 if (am_flav & ia32_S)
590 ret_val |= IA32_LEA_ATTR_SCALE;
592 ret_val |= IA32_LEA_ATTR_INDEX;
595 return IA32_LEA_ATTR_NONE;
597 else if (is_noreg_base && ! is_noreg_index) {
598 /* Index is set but not base */
600 /* Index points to LEA: assimilate everything */
601 if (am_flav & ia32_O)
602 ret_val |= IA32_LEA_ATTR_OFFS;
603 if (am_flav & ia32_S)
604 ret_val |= IA32_LEA_ATTR_SCALE;
605 if (am_flav & ia32_B)
606 ret_val |= IA32_LEA_ATTR_BASE;
608 ret_val |= IA32_LEA_ATTR_INDEX;
610 else if (am_flav & ia32_I ? 0 : 1) {
611 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
612 if (am_flav & ia32_O)
613 ret_val |= IA32_LEA_ATTR_OFFS;
614 if (am_flav & ia32_S)
615 ret_val |= IA32_LEA_ATTR_SCALE;
617 ret_val |= IA32_LEA_ATTR_BASE;
620 return IA32_LEA_ATTR_NONE;
623 assert(0 && "There must have been set base or index");
630 * Adds res before irn into schedule if irn was scheduled.
631 * @param irn The schedule point
632 * @param res The node to be scheduled
634 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
635 if (sched_is_scheduled(irn))
636 sched_add_before(irn, res);
640 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
641 * all it's Projs are removed as well.
642 * @param irn The irn to be removed from schedule
644 static INLINE void try_kill(ir_node *node)
646 if(get_irn_mode(node) == mode_T) {
647 const ir_edge_t *edge, *next;
648 foreach_out_edge_safe(node, edge, next) {
649 ir_node *proj = get_edge_src_irn(edge);
654 if(get_irn_n_edges(node) != 0)
657 if (sched_is_scheduled(node)) {
665 * Folds Add or Sub to LEA if possible
667 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
668 ir_graph *irg = get_irn_irg(irn);
669 dbg_info *dbg_info = get_irn_dbg_info(irn);
670 ir_node *block = get_nodes_block(irn);
672 ir_node *shift = NULL;
673 ir_node *lea_o = NULL;
683 ir_entity *am_sc = NULL;
684 ir_entity *lea_ent = NULL;
685 ir_node *noreg = ia32_new_NoReg_gp(cg);
686 ir_node *left, *right, *temp;
687 ir_node *base, *index;
688 int consumed_left_shift;
689 ia32_am_flavour_t am_flav;
691 if (is_ia32_Add(irn))
694 left = get_irn_n(irn, 2);
695 right = get_irn_n(irn, 3);
697 /* "normalize" arguments in case of add with two operands */
698 if (isadd && ! be_is_NoReg(cg, right)) {
699 /* put LEA == ia32_am_O as right operand */
700 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
701 set_irn_n(irn, 2, right);
702 set_irn_n(irn, 3, left);
708 /* put LEA != ia32_am_O as left operand */
709 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
710 set_irn_n(irn, 2, right);
711 set_irn_n(irn, 3, left);
717 /* put SHL as left operand iff left is NOT a LEA */
718 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
719 set_irn_n(irn, 2, right);
720 set_irn_n(irn, 3, left);
733 /* check for operation with immediate */
734 if (is_ia32_ImmConst(irn)) {
735 tarval *tv = get_ia32_Immop_tarval(irn);
737 DBG((dbg, LEVEL_1, "\tfound op with imm const"));
739 offs_cnst = get_tarval_long(tv);
742 else if (isadd && is_ia32_ImmSymConst(irn)) {
743 DBG((dbg, LEVEL_1, "\tfound op with imm symconst"));
747 am_sc = get_ia32_Immop_symconst(irn);
748 am_sc_sign = is_ia32_am_sc_sign(irn);
751 /* determine the operand which needs to be checked */
752 temp = be_is_NoReg(cg, right) ? left : right;
754 /* check if right operand is AMConst (LEA with ia32_am_O) */
755 /* but we can only eat it up if there is no other symconst */
756 /* because the linker won't accept two symconsts */
757 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
758 DBG((dbg, LEVEL_1, "\tgot op with LEA am_O"));
760 offs_lea = get_ia32_am_offs_int(temp);
761 am_sc = get_ia32_am_sc(temp);
762 am_sc_sign = is_ia32_am_sc_sign(temp);
769 else if (temp == right)
774 /* default for add -> make right operand to index */
777 consumed_left_shift = -1;
779 DBG((dbg, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
781 /* determine the operand which needs to be checked */
783 if (is_ia32_Lea(left)) {
785 consumed_left_shift = 0;
788 /* check for SHL 1,2,3 */
789 if (pred_is_specific_node(temp, is_ia32_Shl)) {
790 ir_node *right = get_irn_n(temp, n_ia32_Shl_right);
792 if (is_ia32_Immediate(right)) {
793 const ia32_immediate_attr_t *attr
794 = get_ia32_immediate_attr_const(right);
795 long shiftval = attr->offset;
798 index = get_irn_n(temp, 2);
799 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
803 DBG((dbg, LEVEL_1, "\tgot scaled index %+F\n", index));
809 if (! be_is_NoReg(cg, index)) {
810 /* if we have index, but left == right -> no base */
814 else if (consumed_left_shift == 1) {
815 /* -> base is right operand */
816 base = (right == lea_o) ? noreg : right;
821 /* Try to assimilate a LEA as left operand */
822 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
823 /* check if we can assimilate the LEA */
824 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
826 if (take_attr == IA32_LEA_ATTR_NONE) {
827 DBG((dbg, LEVEL_1, "\tleave old LEA, creating new one\n"));
830 DBG((dbg, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
831 lea = left; /* for statistics */
833 if (take_attr & IA32_LEA_ATTR_OFFS)
834 offs = get_ia32_am_offs_int(left);
836 if (take_attr & IA32_LEA_ATTR_AMSC) {
837 am_sc = get_ia32_am_sc(left);
839 am_sc_sign = is_ia32_am_sc_sign(left);
842 if (take_attr & IA32_LEA_ATTR_SCALE)
843 scale = get_ia32_am_scale(left);
845 if (take_attr & IA32_LEA_ATTR_BASE)
846 base = get_irn_n(left, 0);
848 if (take_attr & IA32_LEA_ATTR_INDEX)
849 index = get_irn_n(left, 1);
851 if (take_attr & IA32_LEA_ATTR_FENT)
852 lea_ent = get_ia32_frame_ent(left);
856 /* ok, we can create a new LEA */
858 res = new_rd_ia32_Lea(dbg_info, irg, block, base, index);
859 /* we don't want stuff before the barrier... */
860 if(be_is_NoReg(cg, base) && be_is_NoReg(cg, index)) {
861 add_irn_dep(res, get_irg_frame(irg));
864 /* add the old offset of a previous LEA */
865 add_ia32_am_offs_int(res, offs);
867 /* add the new offset */
869 add_ia32_am_offs_int(res, offs_cnst);
870 add_ia32_am_offs_int(res, offs_lea);
872 /* either lea_O-cnst, -cnst or -lea_O */
873 if (offs_cnst != 0) {
874 add_ia32_am_offs_int(res, offs_lea);
875 add_ia32_am_offs_int(res, -offs_cnst);
877 add_ia32_am_offs_int(res, offs_lea);
881 /* set the address mode symconst */
883 set_ia32_am_sc(res, am_sc);
885 set_ia32_am_sc_sign(res);
888 /* copy the frame entity (could be set in case of Add */
889 /* which was a FrameAddr) */
890 if (lea_ent != NULL) {
891 set_ia32_frame_ent(res, lea_ent);
892 set_ia32_use_frame(res);
894 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
895 if(is_ia32_use_frame(irn))
896 set_ia32_use_frame(res);
900 set_ia32_am_scale(res, scale);
903 /* determine new am flavour */
904 if (offs || offs_cnst || offs_lea || have_am_sc) {
907 if (! be_is_NoReg(cg, base)) {
910 if (! be_is_NoReg(cg, index)) {
916 set_ia32_am_flavour(res, am_flav);
918 set_ia32_op_type(res, ia32_AddrModeS);
920 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
922 DBG((dbg, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
924 assert(irn && "Couldn't find result proj");
926 /* get the result Proj of the Add/Sub */
927 try_add_to_sched(irn, res);
929 /* exchange the old op with the new LEA */
933 /* we will exchange it, report here before the Proj is created */
934 if (shift && lea && lea_o) {
938 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
939 } else if (shift && lea) {
942 DBG_OPT_LEA3(irn, lea, shift, res);
943 } else if (shift && lea_o) {
946 DBG_OPT_LEA3(irn, lea_o, shift, res);
947 } else if (lea && lea_o) {
950 DBG_OPT_LEA3(irn, lea_o, lea, res);
953 DBG_OPT_LEA2(irn, shift, res);
956 DBG_OPT_LEA2(irn, lea, res);
959 DBG_OPT_LEA2(irn, lea_o, res);
961 DBG_OPT_LEA1(irn, res);
970 * Merges a Load/Store node with a LEA.
971 * @param irn The Load/Store node
974 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
975 ir_entity *irn_ent = get_ia32_frame_ent(irn);
976 ir_entity *lea_ent = get_ia32_frame_ent(lea);
978 /* If the irn and the LEA both have a different frame entity set: do not merge */
979 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
981 else if (irn_ent == NULL && lea_ent != NULL) {
982 set_ia32_frame_ent(irn, lea_ent);
983 set_ia32_use_frame(irn);
986 /* get the AM attributes from the LEA */
987 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
988 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
989 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
991 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
992 if (is_ia32_am_sc_sign(lea))
993 set_ia32_am_sc_sign(irn);
995 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
997 /* set base and index */
998 set_irn_n(irn, 0, get_irn_n(lea, 0));
999 set_irn_n(irn, 1, get_irn_n(lea, 1));
1003 /* clear remat flag */
1004 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1006 if (is_ia32_Ld(irn))
1007 DBG_OPT_LOAD_LEA(lea, irn);
1009 DBG_OPT_STORE_LEA(lea, irn);
1014 * Sets new_right index of irn to right and new_left index to left.
1015 * Also exchange left and right
1017 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right,
1018 int new_left, int new_right)
1022 assert(is_ia32_commutative(irn));
1024 set_irn_n(irn, new_right, *right);
1025 set_irn_n(irn, new_left, *left);
1031 /* this is only needed for Compares, but currently ALL nodes
1032 * have this attribute :-) */
1033 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1037 * Performs address calculation optimization (create LEAs if possible)
1039 static void optimize_lea(ia32_code_gen_t *cg, ir_node *irn) {
1040 if (! is_ia32_irn(irn))
1043 /* Following cases can occur: */
1044 /* - Sub (l, imm) -> LEA [base - offset] */
1045 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1046 /* - Add (l, imm) -> LEA [base + offset] */
1047 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1048 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1049 /* - Add (l, r) -> LEA [base + index * scale] */
1050 /* with scale > 1 iff l/r == shl (1,2,3) */
1051 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1054 if(!is_addr_candidate(irn))
1057 DBG((dbg, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1058 res = fold_addr(cg, irn);
1061 DB((dbg, LEVEL_1, "transformed into %+F\n", res));
1063 DB((dbg, LEVEL_1, "not transformed\n"));
1064 } else if (is_ia32_Ld(irn) || is_ia32_St(irn)) {
1065 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1066 /* - Store -> LEA into Store } it might be better to keep the LEA */
1067 ir_node *left = get_irn_n(irn, 0);
1069 if (is_ia32_Lea(left)) {
1070 const ir_edge_t *edge, *ne;
1073 /* merge all Loads/Stores connected to this LEA with the LEA */
1074 foreach_out_edge_safe(left, edge, ne) {
1075 src = get_edge_src_irn(edge);
1077 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src))) {
1078 DBG((dbg, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1079 if (! is_ia32_got_lea(src))
1080 merge_loadstore_lea(src, left);
1081 set_ia32_got_lea(src);
1088 static void optimize_conv_store(ir_node *node)
1092 ir_mode *store_mode;
1094 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1097 pred = get_irn_n(node, 2);
1098 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1101 /* the store only stores the lower bits, so we only need the conv
1102 * it it shrinks the mode */
1103 conv_mode = get_ia32_ls_mode(pred);
1104 store_mode = get_ia32_ls_mode(node);
1105 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1108 set_irn_n(node, 2, get_irn_n(pred, 2));
1109 if(get_irn_n_edges(pred) == 0) {
1114 static void optimize_load_conv(ir_node *node)
1116 ir_node *pred, *predpred;
1120 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1123 pred = get_irn_n(node, 2);
1127 predpred = get_Proj_pred(pred);
1128 if(!is_ia32_Load(predpred))
1131 /* the load is sign extending the upper bits, so we only need the conv
1132 * if it shrinks the mode */
1133 load_mode = get_ia32_ls_mode(predpred);
1134 conv_mode = get_ia32_ls_mode(node);
1135 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1138 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1139 /* change the load if it has only 1 user */
1140 if(get_irn_n_edges(pred) == 1) {
1142 if(get_mode_sign(conv_mode)) {
1143 newmode = find_signed_mode(load_mode);
1145 newmode = find_unsigned_mode(load_mode);
1147 assert(newmode != NULL);
1148 set_ia32_ls_mode(predpred, newmode);
1150 /* otherwise we have to keep the conv */
1156 exchange(node, pred);
1159 static void optimize_conv_conv(ir_node *node)
1165 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1168 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1169 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1170 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1173 /* we know that after a conv, the upper bits are sign extended
1174 * so we only need the 2nd conv if it shrinks the mode */
1175 conv_mode = get_ia32_ls_mode(node);
1176 pred_mode = get_ia32_ls_mode(pred);
1177 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(pred_mode))
1180 /* we can't eliminate an upconv signed->unsigned */
1181 if (get_mode_size_bits(conv_mode) != get_mode_size_bits(pred_mode) &&
1182 !get_mode_sign(conv_mode) && get_mode_sign(pred_mode))
1186 exchange(node, pred);
1189 static void optimize_node(ir_node *node, void *env)
1191 ia32_code_gen_t *cg = env;
1193 optimize_load_conv(node);
1194 optimize_conv_store(node);
1195 optimize_conv_conv(node);
1196 optimize_lea(cg, node);
1200 * Checks for address mode patterns and performs the
1201 * necessary transformations.
1202 * This function is called by a walker.
1204 static void optimize_am(ir_node *irn, void *env) {
1205 ia32_am_opt_env_t *am_opt_env = env;
1206 ia32_code_gen_t *cg = am_opt_env->cg;
1207 ir_graph *irg = get_irn_irg(irn);
1208 heights_t *h = am_opt_env->h;
1209 ir_node *block, *left, *right;
1210 ir_node *store, *load, *mem_proj;
1211 ir_node *addr_b, *addr_i;
1212 int need_exchange_on_fail = 0;
1213 ia32_am_type_t am_support;
1214 ia32_am_arity_t am_arity;
1215 ia32_am_cand_t cand;
1216 ia32_am_cand_t orig_cand;
1218 int source_possible;
1220 static const arch_register_req_t dest_out_reg_req_0 = {
1221 arch_register_req_type_none,
1222 NULL, /* regclass */
1223 NULL, /* limit bitset */
1225 -1 /* different pos */
1227 static const arch_register_req_t *dest_am_out_reqs[] = {
1231 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn))
1233 if (is_ia32_Lea(irn))
1236 am_support = get_ia32_am_support(irn);
1237 am_arity = get_ia32_am_arity(irn);
1238 block = get_nodes_block(irn);
1240 /* fold following patterns:
1241 * - op -> Load into AMop with am_Source
1243 * - op is am_Source capable AND
1244 * - the Load is only used by this op AND
1245 * - the Load is in the same block
1246 * - Store -> op -> Load into AMop with am_Dest
1248 * - op is am_Dest capable AND
1249 * - the Store uses the same address as the Load AND
1250 * - the Load is only used by this op AND
1251 * - the Load and Store are in the same block AND
1252 * - nobody else uses the result of the op
1254 if (am_support == ia32_am_None)
1257 assert(am_arity == ia32_am_unary || am_arity == ia32_am_binary);
1259 cand = is_am_candidate(h, block, irn);
1260 if (cand == IA32_AM_CAND_NONE)
1264 DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F (candleft %d candright %d)... \n", irn,
1265 cand & IA32_AM_CAND_LEFT, cand & IA32_AM_CAND_RIGHT));
1267 left = get_irn_n(irn, 2);
1268 if (am_arity == ia32_am_unary) {
1269 assert(get_irn_arity(irn) >= 4);
1271 assert(cand == IA32_AM_CAND_BOTH);
1273 assert(get_irn_arity(irn) >= 5);
1274 right = get_irn_n(irn, 3);
1277 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1278 source_possible = am_support & ia32_am_Source ? 1 : 0;
1280 DBG((dbg, LEVEL_2, "\tdest_possible %d source_possible %d ... \n", dest_possible, source_possible));
1282 if (dest_possible) {
1287 /* we should only have 1 user which is a store */
1288 if (ia32_get_irn_n_edges(irn) == 1) {
1289 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1291 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1293 addr_b = get_irn_n(store, 0);
1294 addr_i = get_irn_n(store, 1);
1298 if (store == NULL) {
1299 DBG((dbg, LEVEL_2, "\tno store found, not using dest_mode\n"));
1304 if (dest_possible) {
1305 /* normalize nodes, we need the interesting load on the left side */
1306 if (cand & IA32_AM_CAND_RIGHT) {
1307 load = get_Proj_pred(right);
1308 if (load_store_addr_is_equal(load, store, addr_b, addr_i)
1309 && node_is_ia32_comm(irn)) {
1310 DBG((dbg, LEVEL_2, "\texchanging left/right\n"));
1311 exchange_left_right(irn, &left, &right, 3, 2);
1312 need_exchange_on_fail ^= 1;
1313 if (cand == IA32_AM_CAND_RIGHT)
1314 cand = IA32_AM_CAND_LEFT;
1319 if (dest_possible) {
1320 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1321 load = get_Proj_pred(left);
1323 #ifndef AGGRESSIVE_AM
1324 /* we have to be the only user of the load */
1325 if (get_irn_n_edges(left) > 1) {
1326 DBG((dbg, LEVEL_2, "\tmatching load has too may users, not using dest_mode\n"));
1331 DBG((dbg, LEVEL_2, "\tno matching load found, not using dest_mode"));
1336 if (dest_possible) {
1337 /* the store has to use the loads memory or the same memory
1339 ir_node *loadmem = get_irn_n(load, 2);
1340 ir_node *storemem = get_irn_n(store, 3);
1341 assert(get_irn_mode(loadmem) == mode_M);
1342 assert(get_irn_mode(storemem) == mode_M);
1343 /* TODO there could be a sync between store and load... */
1344 if(storemem != loadmem && (!is_Proj(storemem) || get_Proj_pred(storemem) != load)) {
1345 DBG((dbg, LEVEL_2, "\tload/store using different memories, not using dest_mode"));
1350 if (dest_possible) {
1351 /* Compare Load and Store address */
1352 if (!load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1353 DBG((dbg, LEVEL_2, "\taddresses not equal, not using dest_mode"));
1358 if (dest_possible) {
1359 ir_mode *lsmode = get_ia32_ls_mode(load);
1360 if(get_mode_size_bits(lsmode) != 32) {
1365 if (dest_possible) {
1366 /* all conditions fullfilled, do the transformation */
1367 assert(cand & IA32_AM_CAND_LEFT);
1369 /* set new base, index and attributes */
1370 set_irn_n(irn, 0, addr_b);
1371 set_irn_n(irn, 1, addr_i);
1372 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1373 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1374 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1375 set_ia32_op_type(irn, ia32_AddrModeD);
1376 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1377 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1379 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1380 if (is_ia32_am_sc_sign(load))
1381 set_ia32_am_sc_sign(irn);
1383 /* connect to Load memory and disconnect Load */
1384 if (am_arity == ia32_am_binary) {
1386 set_irn_n(irn, 4, get_irn_n(load, 2));
1387 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1390 set_irn_n(irn, 3, get_irn_n(load, 2));
1391 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1394 /* change node mode and out register requirements */
1395 set_irn_mode(irn, mode_M);
1396 set_ia32_out_req_all(irn, dest_am_out_reqs);
1398 /* connect the memory Proj of the Store to the op */
1399 edges_reroute(store, irn, irg);
1401 /* clear remat flag */
1402 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1406 DBG_OPT_AM_D(load, store, irn);
1408 DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1409 need_exchange_on_fail = 0;
1410 source_possible = 0;
1413 if (source_possible) {
1414 /* normalize ops, we need the load on the right */
1415 if(cand == IA32_AM_CAND_LEFT) {
1416 if(node_is_ia32_comm(irn)) {
1417 exchange_left_right(irn, &left, &right, 3, 2);
1418 need_exchange_on_fail ^= 1;
1419 cand = IA32_AM_CAND_RIGHT;
1421 source_possible = 0;
1426 if (source_possible) {
1427 /* all conditions fullfilled, do transform */
1428 assert(cand & IA32_AM_CAND_RIGHT);
1429 load = get_Proj_pred(right);
1431 if(get_irn_n_edges(load) > 1) {
1432 source_possible = 0;
1436 if (source_possible) {
1437 ir_mode *ls_mode = get_ia32_ls_mode(load);
1438 if(get_mode_size_bits(ls_mode) != 32)
1439 source_possible = 0;
1443 if (source_possible) {
1444 addr_b = get_irn_n(load, 0);
1445 addr_i = get_irn_n(load, 1);
1447 /* set new base, index and attributes */
1448 set_irn_n(irn, 0, addr_b);
1449 set_irn_n(irn, 1, addr_i);
1450 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1451 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1452 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1453 set_ia32_op_type(irn, ia32_AddrModeS);
1454 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1455 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1457 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1458 if (is_ia32_am_sc_sign(load))
1459 set_ia32_am_sc_sign(irn);
1461 /* clear remat flag */
1462 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1464 if (is_ia32_use_frame(load)) {
1465 if(get_ia32_frame_ent(load) == NULL) {
1466 set_ia32_need_stackent(irn);
1468 set_ia32_use_frame(irn);
1471 /* connect to Load memory and disconnect Load */
1472 if (am_arity == ia32_am_binary) {
1474 right = ia32_get_admissible_noreg(cg, irn, 3);
1475 set_irn_n(irn, 3, right);
1476 set_irn_n(irn, 4, get_irn_n(load, n_ia32_Load_mem));
1479 right = ia32_get_admissible_noreg(cg, irn, 2);
1480 set_irn_n(irn, 2, right);
1481 set_irn_n(irn, 3, get_irn_n(load, n_ia32_Load_mem));
1484 DBG_OPT_AM_S(load, irn);
1486 /* If Load has a memory Proj, connect it to the op */
1487 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1488 if (mem_proj != NULL) {
1490 ir_mode *mode = get_irn_mode(irn);
1492 assert(mode != mode_T);
1494 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1495 get_nodes_block(irn), new_Unknown(mode_T),
1497 set_irn_mode(irn, mode_T);
1498 edges_reroute(irn, res_proj, irg);
1499 set_Proj_pred(res_proj, irn);
1501 set_Proj_pred(mem_proj, irn);
1502 set_Proj_proj(mem_proj, 1);
1504 #ifdef SCHEDULE_PROJS
1505 if(sched_is_scheduled(irn)) {
1506 sched_add_after(irn, res_proj);
1507 sched_add_after(irn, mem_proj);
1513 need_exchange_on_fail = 0;
1515 /* immediate are only allowed on the right side */
1516 if(is_ia32_Immediate(left)) {
1517 exchange_left_right(irn, &left, &right, 3, 2);
1520 DB((dbg, LEVEL_1, "merged with %+F into source AM\n", load));
1523 /* was exchanged but optimize failed: exchange back */
1524 if (need_exchange_on_fail) {
1525 exchange_left_right(irn, &left, &right, 3, 2);
1530 * Performs conv and address mode optimization.
1532 void ia32_optimize_graph(ia32_code_gen_t *cg) {
1533 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1534 if (! (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA))) {
1535 /* no optimizations at all */
1539 /* beware: we cannot optimize LEA and AM in one run because */
1540 /* LEA optimization adds new nodes to the irg which */
1541 /* invalidates the phase data */
1543 if (cg->opt & IA32_OPT_LEA) {
1544 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1548 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1550 /* hack for now, so these don't get created during optimize, because then
1551 * they will be unknown to the heights module
1553 ia32_new_NoReg_gp(cg);
1554 ia32_new_NoReg_fp(cg);
1555 ia32_new_NoReg_vfp(cg);
1557 if (cg->opt & IA32_OPT_DOAM) {
1558 /* we need height information for am optimization */
1559 heights_t *h = heights_new(cg->irg);
1560 ia32_am_opt_env_t env;
1565 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
1571 void ia32_init_optimize(void)
1573 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");