2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Christian Wuerdig
33 #include "firm_types.h"
43 #include "../benode_t.h"
44 #include "../besched_t.h"
46 #include "ia32_new_nodes.h"
47 #include "bearch_ia32_t.h"
48 #include "gen_ia32_regalloc_if.h"
49 #include "ia32_transform.h"
50 #include "ia32_dbg_stat.h"
51 #include "ia32_util.h"
53 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
59 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
60 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
61 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
64 typedef int is_op_func_t(const ir_node *n);
65 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
68 * checks if a node represents the NOREG value
70 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
71 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
74 /********************************************************************************************************
75 * _____ _ _ ____ _ _ _ _ _
76 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
77 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
78 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
79 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
80 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
83 ********************************************************************************************************/
86 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
89 static int ia32_const_equal(const ir_node *n1, const ir_node *n2) {
90 if(get_ia32_immop_type(n1) != get_ia32_immop_type(n2))
93 if(get_ia32_immop_type(n1) == ia32_ImmConst) {
94 return get_ia32_Immop_tarval(n1) == get_ia32_Immop_tarval(n2);
95 } else if(get_ia32_immop_type(n1) == ia32_ImmSymConst) {
96 return get_ia32_Immop_symconst(n1) == get_ia32_Immop_symconst(n2);
99 assert(get_ia32_immop_type(n1) == ia32_ImmNone);
104 * Checks for potential CJmp/CJmpAM optimization candidates.
106 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
107 ir_node *cand = NULL;
108 ir_node *prev = sched_prev(irn);
110 if (is_Block(prev)) {
111 if (get_Block_n_cfgpreds(prev) == 1)
112 prev = get_Block_cfgpred(prev, 0);
117 /* The predecessor must be a ProjX. */
118 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
119 prev = get_Proj_pred(prev);
121 if (is_op_func(prev))
128 static int is_TestJmp_cand(const ir_node *irn) {
129 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
133 * Checks if two consecutive arguments of cand matches
134 * the two arguments of irn (TestJmp).
136 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
137 ir_node *in1 = get_irn_n(irn, 0);
138 ir_node *in2 = get_irn_n(irn, 1);
139 int i, n = get_irn_arity(cand);
142 for (i = 0; i < n - 1; i++) {
143 if (get_irn_n(cand, i) == in1 &&
144 get_irn_n(cand, i + 1) == in2)
154 return ia32_const_equal(cand, irn);
158 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
160 static void ia32_optimize_TestJmp(ir_node *irn)
162 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
165 /* we found a possible candidate */
166 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
169 DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
171 if (is_ia32_And(cand))
172 set_irn_op(irn, op_ia32_CJmpAM);
174 set_irn_op(irn, op_ia32_CJmp);
176 DB((dbg, LEVEL_1, "%+F\n", irn));
180 static int is_CondJmp_cand(const ir_node *irn) {
181 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
185 * Checks if the arguments of cand are the same of irn.
187 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
190 arity = get_irn_arity(cand);
191 for (i = 0; i < arity; i++) {
192 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
197 return ia32_const_equal(cand, irn);
201 * Tries to replace a CondJmp by a CJmpAM
203 static void ia32_optimize_CondJmp(ir_node *irn)
205 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
208 /* we found a possible candidate */
209 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
212 DBG((dbg, LEVEL_1, "replacing %+F by ", irn));
215 set_irn_op(irn, op_ia32_CJmpAM);
217 DB((dbg, LEVEL_1, "%+F\n", irn));
221 // only optimize up to 48 stores behind IncSPs
222 #define MAXPUSH_OPTIMIZE 48
225 * Tries to create pushs from IncSP,Store combinations
227 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
231 ir_node *stores[MAXPUSH_OPTIMIZE];
232 ir_node *block = get_nodes_block(irn);
233 ir_graph *irg = cg->irg;
235 ir_mode *spmode = get_irn_mode(irn);
237 memset(stores, 0, sizeof(stores));
239 assert(be_is_IncSP(irn));
241 offset = be_get_IncSP_offset(irn);
246 * We first walk the schedule after the IncSP node as long as we find
247 * suitable stores that could be transformed to a push.
248 * We save them into the stores array which is sorted by the frame offset/4
249 * attached to the node
251 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
256 // it has to be a store
257 if(!is_ia32_Store(node))
260 // it has to use our sp value
261 if(get_irn_n(node, 0) != irn)
263 // store has to be attached to NoMem
264 mem = get_irn_n(node, 3);
269 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
272 offset = get_ia32_am_offs_int(node);
274 storeslot = offset / 4;
275 if(storeslot >= MAXPUSH_OPTIMIZE)
278 // storing into the same slot twice is bad (and shouldn't happen...)
279 if(stores[storeslot] != NULL)
282 // storing at half-slots is bad
286 stores[storeslot] = node;
289 curr_sp = get_irn_n(irn, 0);
291 // walk the stores in inverse order and create pushs for them
292 i = (offset / 4) - 1;
293 if(i >= MAXPUSH_OPTIMIZE) {
294 i = MAXPUSH_OPTIMIZE - 1;
297 for( ; i >= 0; --i) {
298 const arch_register_t *spreg;
300 ir_node *val, *mem, *mem_proj;
301 ir_node *store = stores[i];
302 ir_node *noreg = ia32_new_NoReg_gp(cg);
304 if(store == NULL || is_Bad(store))
307 val = get_irn_n(store, 2);
308 mem = get_irn_n(store, 3);
309 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
312 push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
314 set_ia32_am_support(push, ia32_am_Source, ia32_am_unary);
315 copy_ia32_Immop_attr(push, store);
317 sched_add_before(irn, push);
319 // create stackpointer proj
320 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
321 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
322 #ifdef SCHEDULE_PROJS
323 sched_add_before(irn, curr_sp);
325 // create memory proj
326 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
328 // use the memproj now
329 exchange(store, mem_proj);
331 // we can remove the store now
337 be_set_IncSP_offset(irn, offset);
339 // can we remove the IncSP now?
341 const ir_edge_t *edge, *next;
343 foreach_out_edge_safe(irn, edge, next) {
344 ir_node *arg = get_edge_src_irn(edge);
345 int pos = get_edge_src_pos(edge);
347 set_irn_n(arg, pos, curr_sp);
350 set_irn_n(irn, 0, new_Bad());
353 set_irn_n(irn, 0, curr_sp);
359 * Tries to optimize two following IncSP.
361 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
362 ir_node *prev = be_get_IncSP_pred(irn);
363 int real_uses = get_irn_n_edges(prev);
365 if (be_is_IncSP(prev) && real_uses == 1) {
366 /* first IncSP has only one IncSP user, kill the first one */
367 int prev_offs = be_get_IncSP_offset(prev);
368 int curr_offs = be_get_IncSP_offset(irn);
370 be_set_IncSP_offset(prev, prev_offs + curr_offs);
372 /* Omit the optimized IncSP */
373 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
375 set_irn_n(prev, 0, new_Bad());
382 * Performs Peephole Optimizations.
384 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
385 ia32_code_gen_t *cg = env;
387 /* AMD CPUs want explicit compare before conditional jump */
388 if (! ARCH_AMD(cg->opt_arch)) {
389 if (is_ia32_TestJmp(irn))
390 ia32_optimize_TestJmp(irn);
391 else if (is_ia32_CondJmp(irn))
392 ia32_optimize_CondJmp(irn);
395 if (be_is_IncSP(irn)) {
396 // optimize_IncSP doesn't respect dependency edges yet...
397 //ia32_optimize_IncSP(irn, cg);
399 if (cg->opt & IA32_OPT_PUSHARGS)
400 ia32_create_Pushs(irn, cg);
404 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
405 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
408 /******************************************************************
410 * /\ | | | | | \/ | | |
411 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
412 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
413 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
414 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
416 ******************************************************************/
423 static int node_is_ia32_comm(const ir_node *irn) {
424 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
427 static int ia32_get_irn_n_edges(const ir_node *irn) {
428 const ir_edge_t *edge;
431 foreach_out_edge(irn, edge) {
439 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
441 * @param pred The node to be checked
442 * @param is_op_func The check-function
443 * @return 1 if conditions are fulfilled, 0 otherwise
445 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
446 return is_op_func(pred);
450 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
451 * and if the predecessor is in block bl.
453 * @param bl The block
454 * @param pred The node to be checked
455 * @param is_op_func The check-function
456 * @return 1 if conditions are fulfilled, 0 otherwise
458 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
459 int (*is_op_func)(const ir_node *n))
462 pred = get_Proj_pred(pred);
463 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
472 * Checks if irn is a candidate for address calculation. We avoid transforming
473 * adds to leas if they have a load as pred, because then we can use AM mode
476 * - none of the operand must be a Load within the same block OR
477 * - all Loads must have more than one user OR
479 * @param block The block the Loads must/mustnot be in
480 * @param irn The irn to check
481 * return 1 if irn is a candidate, 0 otherwise
483 static int is_addr_candidate(const ir_node *irn)
485 #ifndef AGGRESSIVE_AM
486 const ir_node *block = get_nodes_block(irn);
487 ir_node *left, *right;
490 left = get_irn_n(irn, 2);
491 right = get_irn_n(irn, 3);
493 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
494 n = ia32_get_irn_n_edges(left);
495 /* load with only one user: don't create LEA */
500 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
501 n = ia32_get_irn_n_edges(right);
512 * Checks if irn is a candidate for address mode.
515 * - at least one operand has to be a Load within the same block AND
516 * - the load must not have other users than the irn AND
517 * - the irn must not have a frame entity set
519 * @param cg The ia32 code generator
520 * @param h The height information of the irg
521 * @param block The block the Loads must/mustnot be in
522 * @param irn The irn to check
523 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
525 static ia32_am_cand_t is_am_candidate(heights_t *h, const ir_node *block, ir_node *irn) {
526 ir_node *in, *load, *other, *left, *right;
527 int is_cand = 0, cand;
530 if (is_ia32_Ld(irn) || is_ia32_St(irn) ||
531 is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
532 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
535 if(get_ia32_frame_ent(irn) != NULL)
536 return IA32_AM_CAND_NONE;
538 left = get_irn_n(irn, 2);
539 arity = get_irn_arity(irn);
540 if(get_ia32_am_arity(irn) == ia32_am_binary) {
542 right = get_irn_n(irn, 3);
544 assert(get_ia32_am_arity(irn) == ia32_am_unary);
551 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
552 #ifndef AGGRESSIVE_AM
554 n = ia32_get_irn_n_edges(in);
555 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
560 load = get_Proj_pred(in);
563 /* 8bit Loads are not supported (for binary ops),
564 * they cannot be used with every register */
565 if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
566 assert(get_irn_arity(irn) == 5);
570 /* If there is a data dependency of other irn from load: cannot use AM */
571 if (is_cand && get_nodes_block(other) == block) {
572 other = skip_Proj(other);
573 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
574 /* this could happen in loops */
575 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
579 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
583 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
584 #ifndef AGGRESSIVE_AM
586 n = ia32_get_irn_n_edges(in);
587 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
592 load = get_Proj_pred(in);
595 /* 8bit Loads are not supported, they cannot be used with every register */
596 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
599 /* If there is a data dependency of other irn from load: cannot use load */
600 if (is_cand && get_nodes_block(other) == block) {
601 other = skip_Proj(other);
602 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
603 /* this could happen in loops */
604 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
608 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
610 /* if the irn has a frame entity: we do not use address mode */
615 * Compares the base and index addr and the load/store entities
616 * and returns 1 if they are equal.
618 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
619 const ir_node *addr_b, const ir_node *addr_i)
621 if(get_irn_n(load, 0) != addr_b)
623 if(get_irn_n(load, 1) != addr_i)
626 if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
629 if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
631 if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
633 if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
635 if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
641 typedef enum _ia32_take_lea_attr {
642 IA32_LEA_ATTR_NONE = 0,
643 IA32_LEA_ATTR_BASE = (1 << 0),
644 IA32_LEA_ATTR_INDEX = (1 << 1),
645 IA32_LEA_ATTR_OFFS = (1 << 2),
646 IA32_LEA_ATTR_SCALE = (1 << 3),
647 IA32_LEA_ATTR_AMSC = (1 << 4),
648 IA32_LEA_ATTR_FENT = (1 << 5)
649 } ia32_take_lea_attr;
652 * Decides if we have to keep the LEA operand or if we can assimilate it.
654 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
655 int have_am_sc, ia32_code_gen_t *cg)
657 ir_entity *irn_ent = get_ia32_frame_ent(irn);
658 ir_entity *lea_ent = get_ia32_frame_ent(lea);
660 int is_noreg_base = be_is_NoReg(cg, base);
661 int is_noreg_index = be_is_NoReg(cg, index);
662 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
664 /* If the Add and the LEA both have a different frame entity set: keep */
665 if (irn_ent && lea_ent && (irn_ent != lea_ent))
666 return IA32_LEA_ATTR_NONE;
667 else if (! irn_ent && lea_ent)
668 ret_val |= IA32_LEA_ATTR_FENT;
670 /* If the Add and the LEA both have already an address mode symconst: keep */
671 if (have_am_sc && get_ia32_am_sc(lea))
672 return IA32_LEA_ATTR_NONE;
673 else if (get_ia32_am_sc(lea))
674 ret_val |= IA32_LEA_ATTR_AMSC;
676 /* Check the different base-index combinations */
678 if (! is_noreg_base && ! is_noreg_index) {
679 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
680 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
681 if (am_flav & ia32_O)
682 ret_val |= IA32_LEA_ATTR_OFFS;
684 ret_val |= IA32_LEA_ATTR_BASE;
687 return IA32_LEA_ATTR_NONE;
689 else if (! is_noreg_base && is_noreg_index) {
690 /* Base is set but index not */
692 /* Base points to LEA: assimilate everything */
693 if (am_flav & ia32_O)
694 ret_val |= IA32_LEA_ATTR_OFFS;
695 if (am_flav & ia32_S)
696 ret_val |= IA32_LEA_ATTR_SCALE;
697 if (am_flav & ia32_I)
698 ret_val |= IA32_LEA_ATTR_INDEX;
700 ret_val |= IA32_LEA_ATTR_BASE;
702 else if (am_flav & ia32_B ? 0 : 1) {
703 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
704 if (am_flav & ia32_O)
705 ret_val |= IA32_LEA_ATTR_OFFS;
706 if (am_flav & ia32_S)
707 ret_val |= IA32_LEA_ATTR_SCALE;
709 ret_val |= IA32_LEA_ATTR_INDEX;
712 return IA32_LEA_ATTR_NONE;
714 else if (is_noreg_base && ! is_noreg_index) {
715 /* Index is set but not base */
717 /* Index points to LEA: assimilate everything */
718 if (am_flav & ia32_O)
719 ret_val |= IA32_LEA_ATTR_OFFS;
720 if (am_flav & ia32_S)
721 ret_val |= IA32_LEA_ATTR_SCALE;
722 if (am_flav & ia32_B)
723 ret_val |= IA32_LEA_ATTR_BASE;
725 ret_val |= IA32_LEA_ATTR_INDEX;
727 else if (am_flav & ia32_I ? 0 : 1) {
728 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
729 if (am_flav & ia32_O)
730 ret_val |= IA32_LEA_ATTR_OFFS;
731 if (am_flav & ia32_S)
732 ret_val |= IA32_LEA_ATTR_SCALE;
734 ret_val |= IA32_LEA_ATTR_BASE;
737 return IA32_LEA_ATTR_NONE;
740 assert(0 && "There must have been set base or index");
747 * Adds res before irn into schedule if irn was scheduled.
748 * @param irn The schedule point
749 * @param res The node to be scheduled
751 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
752 if (sched_is_scheduled(irn))
753 sched_add_before(irn, res);
757 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
758 * all it's Projs are removed as well.
759 * @param irn The irn to be removed from schedule
761 static INLINE void try_remove_from_sched(ir_node *node) {
764 if(get_irn_mode(node) == mode_T) {
765 const ir_edge_t *edge, *next;
766 foreach_out_edge_safe(node, edge, next) {
767 ir_node *proj = get_edge_src_irn(edge);
768 try_remove_from_sched(proj);
772 if(get_irn_n_edges(node) != 0)
775 if (sched_is_scheduled(node)) {
779 arity = get_irn_arity(node);
780 for(i = 0; i < arity; ++i) {
781 set_irn_n(node, i, new_Bad());
786 * Folds Add or Sub to LEA if possible
788 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
789 ir_graph *irg = get_irn_irg(irn);
790 dbg_info *dbg_info = get_irn_dbg_info(irn);
791 ir_node *block = get_nodes_block(irn);
793 ir_node *shift = NULL;
794 ir_node *lea_o = NULL;
804 ir_entity *am_sc = NULL;
805 ir_entity *lea_ent = NULL;
806 ir_node *noreg = ia32_new_NoReg_gp(cg);
807 ir_node *left, *right, *temp;
808 ir_node *base, *index;
809 int consumed_left_shift;
810 ia32_am_flavour_t am_flav;
812 if (is_ia32_Add(irn))
815 left = get_irn_n(irn, 2);
816 right = get_irn_n(irn, 3);
818 /* "normalize" arguments in case of add with two operands */
819 if (isadd && ! be_is_NoReg(cg, right)) {
820 /* put LEA == ia32_am_O as right operand */
821 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
822 set_irn_n(irn, 2, right);
823 set_irn_n(irn, 3, left);
829 /* put LEA != ia32_am_O as left operand */
830 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
831 set_irn_n(irn, 2, right);
832 set_irn_n(irn, 3, left);
838 /* put SHL as left operand iff left is NOT a LEA */
839 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
840 set_irn_n(irn, 2, right);
841 set_irn_n(irn, 3, left);
854 /* check for operation with immediate */
855 if (is_ia32_ImmConst(irn)) {
856 tarval *tv = get_ia32_Immop_tarval(irn);
858 DBG((dbg, LEVEL_1, "\tfound op with imm const"));
860 offs_cnst = get_tarval_long(tv);
863 else if (isadd && is_ia32_ImmSymConst(irn)) {
864 DBG((dbg, LEVEL_1, "\tfound op with imm symconst"));
868 am_sc = get_ia32_Immop_symconst(irn);
869 am_sc_sign = is_ia32_am_sc_sign(irn);
872 /* determine the operand which needs to be checked */
873 temp = be_is_NoReg(cg, right) ? left : right;
875 /* check if right operand is AMConst (LEA with ia32_am_O) */
876 /* but we can only eat it up if there is no other symconst */
877 /* because the linker won't accept two symconsts */
878 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
879 DBG((dbg, LEVEL_1, "\tgot op with LEA am_O"));
881 offs_lea = get_ia32_am_offs_int(temp);
882 am_sc = get_ia32_am_sc(temp);
883 am_sc_sign = is_ia32_am_sc_sign(temp);
890 else if (temp == right)
895 /* default for add -> make right operand to index */
898 consumed_left_shift = -1;
900 DBG((dbg, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
902 /* determine the operand which needs to be checked */
904 if (is_ia32_Lea(left)) {
906 consumed_left_shift = 0;
909 /* check for SHL 1,2,3 */
910 if (pred_is_specific_node(temp, is_ia32_Shl)) {
911 ir_node *right = get_irn_n(temp, n_ia32_Shl_right);
913 if (is_ia32_Immediate(right)) {
914 const ia32_immediate_attr_t *attr
915 = get_ia32_immediate_attr_const(right);
916 long shiftval = attr->offset;
919 index = get_irn_n(temp, 2);
920 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
924 DBG((dbg, LEVEL_1, "\tgot scaled index %+F\n", index));
930 if (! be_is_NoReg(cg, index)) {
931 /* if we have index, but left == right -> no base */
935 else if (consumed_left_shift == 1) {
936 /* -> base is right operand */
937 base = (right == lea_o) ? noreg : right;
942 /* Try to assimilate a LEA as left operand */
943 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
944 /* check if we can assimilate the LEA */
945 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
947 if (take_attr == IA32_LEA_ATTR_NONE) {
948 DBG((dbg, LEVEL_1, "\tleave old LEA, creating new one\n"));
951 DBG((dbg, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
952 lea = left; /* for statistics */
954 if (take_attr & IA32_LEA_ATTR_OFFS)
955 offs = get_ia32_am_offs_int(left);
957 if (take_attr & IA32_LEA_ATTR_AMSC) {
958 am_sc = get_ia32_am_sc(left);
960 am_sc_sign = is_ia32_am_sc_sign(left);
963 if (take_attr & IA32_LEA_ATTR_SCALE)
964 scale = get_ia32_am_scale(left);
966 if (take_attr & IA32_LEA_ATTR_BASE)
967 base = get_irn_n(left, 0);
969 if (take_attr & IA32_LEA_ATTR_INDEX)
970 index = get_irn_n(left, 1);
972 if (take_attr & IA32_LEA_ATTR_FENT)
973 lea_ent = get_ia32_frame_ent(left);
977 /* ok, we can create a new LEA */
979 res = new_rd_ia32_Lea(dbg_info, irg, block, base, index);
980 /* we don't want stuff before the barrier... */
981 if(be_is_NoReg(cg, base) && be_is_NoReg(cg, index)) {
982 add_irn_dep(res, get_irg_frame(irg));
985 /* add the old offset of a previous LEA */
986 add_ia32_am_offs_int(res, offs);
988 /* add the new offset */
990 add_ia32_am_offs_int(res, offs_cnst);
991 add_ia32_am_offs_int(res, offs_lea);
993 /* either lea_O-cnst, -cnst or -lea_O */
994 if (offs_cnst != 0) {
995 add_ia32_am_offs_int(res, offs_lea);
996 add_ia32_am_offs_int(res, -offs_cnst);
998 add_ia32_am_offs_int(res, offs_lea);
1002 /* set the address mode symconst */
1004 set_ia32_am_sc(res, am_sc);
1006 set_ia32_am_sc_sign(res);
1009 /* copy the frame entity (could be set in case of Add */
1010 /* which was a FrameAddr) */
1011 if (lea_ent != NULL) {
1012 set_ia32_frame_ent(res, lea_ent);
1013 set_ia32_use_frame(res);
1015 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1016 if(is_ia32_use_frame(irn))
1017 set_ia32_use_frame(res);
1021 set_ia32_am_scale(res, scale);
1023 am_flav = ia32_am_N;
1024 /* determine new am flavour */
1025 if (offs || offs_cnst || offs_lea || have_am_sc) {
1028 if (! be_is_NoReg(cg, base)) {
1031 if (! be_is_NoReg(cg, index)) {
1037 set_ia32_am_flavour(res, am_flav);
1039 set_ia32_op_type(res, ia32_AddrModeS);
1041 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1043 DBG((dbg, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
1045 assert(irn && "Couldn't find result proj");
1047 /* get the result Proj of the Add/Sub */
1048 try_add_to_sched(irn, res);
1050 /* exchange the old op with the new LEA */
1051 try_remove_from_sched(irn);
1054 /* we will exchange it, report here before the Proj is created */
1055 if (shift && lea && lea_o) {
1056 try_remove_from_sched(shift);
1057 try_remove_from_sched(lea);
1058 try_remove_from_sched(lea_o);
1059 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1060 } else if (shift && lea) {
1061 try_remove_from_sched(shift);
1062 try_remove_from_sched(lea);
1063 DBG_OPT_LEA3(irn, lea, shift, res);
1064 } else if (shift && lea_o) {
1065 try_remove_from_sched(shift);
1066 try_remove_from_sched(lea_o);
1067 DBG_OPT_LEA3(irn, lea_o, shift, res);
1068 } else if (lea && lea_o) {
1069 try_remove_from_sched(lea);
1070 try_remove_from_sched(lea_o);
1071 DBG_OPT_LEA3(irn, lea_o, lea, res);
1073 try_remove_from_sched(shift);
1074 DBG_OPT_LEA2(irn, shift, res);
1076 try_remove_from_sched(lea);
1077 DBG_OPT_LEA2(irn, lea, res);
1079 try_remove_from_sched(lea_o);
1080 DBG_OPT_LEA2(irn, lea_o, res);
1082 DBG_OPT_LEA1(irn, res);
1091 * Merges a Load/Store node with a LEA.
1092 * @param irn The Load/Store node
1093 * @param lea The LEA
1095 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1096 ir_entity *irn_ent = get_ia32_frame_ent(irn);
1097 ir_entity *lea_ent = get_ia32_frame_ent(lea);
1099 /* If the irn and the LEA both have a different frame entity set: do not merge */
1100 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
1102 else if (irn_ent == NULL && lea_ent != NULL) {
1103 set_ia32_frame_ent(irn, lea_ent);
1104 set_ia32_use_frame(irn);
1107 /* get the AM attributes from the LEA */
1108 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
1109 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1110 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1112 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1113 if (is_ia32_am_sc_sign(lea))
1114 set_ia32_am_sc_sign(irn);
1116 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1118 /* set base and index */
1119 set_irn_n(irn, 0, get_irn_n(lea, 0));
1120 set_irn_n(irn, 1, get_irn_n(lea, 1));
1122 try_remove_from_sched(lea);
1124 /* clear remat flag */
1125 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1127 if (is_ia32_Ld(irn))
1128 DBG_OPT_LOAD_LEA(lea, irn);
1130 DBG_OPT_STORE_LEA(lea, irn);
1135 * Sets new_right index of irn to right and new_left index to left.
1136 * Also exchange left and right
1138 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1141 set_irn_n(irn, new_right, *right);
1142 set_irn_n(irn, new_left, *left);
1148 /* this is only needed for Compares, but currently ALL nodes
1149 * have this attribute :-) */
1150 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1154 * Performs address calculation optimization (create LEAs if possible)
1156 static void optimize_lea(ia32_code_gen_t *cg, ir_node *irn) {
1157 if (! is_ia32_irn(irn))
1160 /* Following cases can occur: */
1161 /* - Sub (l, imm) -> LEA [base - offset] */
1162 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1163 /* - Add (l, imm) -> LEA [base + offset] */
1164 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1165 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1166 /* - Add (l, r) -> LEA [base + index * scale] */
1167 /* with scale > 1 iff l/r == shl (1,2,3) */
1168 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1171 if(!is_addr_candidate(irn))
1174 DBG((dbg, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1175 res = fold_addr(cg, irn);
1178 DB((dbg, LEVEL_1, "transformed into %+F\n", res));
1180 DB((dbg, LEVEL_1, "not transformed\n"));
1181 } else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1182 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1183 /* - Store -> LEA into Store } it might be better to keep the LEA */
1184 ir_node *left = get_irn_n(irn, 0);
1186 if (is_ia32_Lea(left)) {
1187 const ir_edge_t *edge, *ne;
1190 /* merge all Loads/Stores connected to this LEA with the LEA */
1191 foreach_out_edge_safe(left, edge, ne) {
1192 src = get_edge_src_irn(edge);
1194 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1195 DBG((dbg, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1196 if (! is_ia32_got_lea(src))
1197 merge_loadstore_lea(src, left);
1198 set_ia32_got_lea(src);
1205 static void optimize_conv_store(ir_node *node)
1209 ir_mode *store_mode;
1211 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1214 pred = get_irn_n(node, 2);
1215 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1218 /* the store only stores the lower bits, so we only need the conv
1219 * it it shrinks the mode */
1220 conv_mode = get_ia32_ls_mode(pred);
1221 store_mode = get_ia32_ls_mode(node);
1222 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1225 set_irn_n(node, 2, get_irn_n(pred, 2));
1226 if(get_irn_n_edges(pred) == 0) {
1231 static void optimize_load_conv(ir_node *node)
1233 ir_node *pred, *predpred;
1237 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1240 pred = get_irn_n(node, 2);
1244 predpred = get_Proj_pred(pred);
1245 if(!is_ia32_Load(predpred))
1248 /* the load is sign extending the upper bits, so we only need the conv
1249 * if it shrinks the mode */
1250 load_mode = get_ia32_ls_mode(predpred);
1251 conv_mode = get_ia32_ls_mode(node);
1252 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1255 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1256 /* change the load if it has only 1 user */
1257 if(get_irn_n_edges(pred) == 1) {
1259 if(get_mode_sign(conv_mode)) {
1260 newmode = find_signed_mode(load_mode);
1262 newmode = find_unsigned_mode(load_mode);
1264 assert(newmode != NULL);
1265 set_ia32_ls_mode(predpred, newmode);
1267 /* otherwise we have to keep the conv */
1273 exchange(node, pred);
1276 static void optimize_conv_conv(ir_node *node)
1282 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1285 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1286 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1287 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1290 /* we know that after a conv, the upper bits are sign extended
1291 * so we only need the 2nd conv if it shrinks the mode */
1292 conv_mode = get_ia32_ls_mode(node);
1293 pred_mode = get_ia32_ls_mode(pred);
1294 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(pred_mode))
1297 /* we can't eliminate an upconv signed->unsigned */
1298 if (get_mode_size_bits(conv_mode) != get_mode_size_bits(pred_mode) &&
1299 !get_mode_sign(conv_mode) && get_mode_sign(pred_mode))
1303 exchange(node, pred);
1306 static void optimize_node(ir_node *node, void *env)
1308 ia32_code_gen_t *cg = env;
1310 optimize_load_conv(node);
1311 optimize_conv_store(node);
1312 optimize_conv_conv(node);
1313 optimize_lea(cg, node);
1317 * Checks for address mode patterns and performs the
1318 * necessary transformations.
1319 * This function is called by a walker.
1321 static void optimize_am(ir_node *irn, void *env) {
1322 ia32_am_opt_env_t *am_opt_env = env;
1323 ia32_code_gen_t *cg = am_opt_env->cg;
1324 ir_graph *irg = get_irn_irg(irn);
1325 heights_t *h = am_opt_env->h;
1326 ir_node *block, *left, *right;
1327 ir_node *store, *load, *mem_proj;
1328 ir_node *addr_b, *addr_i;
1329 int need_exchange_on_fail = 0;
1330 ia32_am_type_t am_support;
1331 ia32_am_arity_t am_arity;
1332 ia32_am_cand_t cand;
1333 ia32_am_cand_t orig_cand;
1335 int source_possible;
1337 static const arch_register_req_t dest_out_reg_req_0 = {
1338 arch_register_req_type_none,
1339 NULL, /* regclass */
1340 NULL, /* limit bitset */
1342 -1 /* different pos */
1344 static const arch_register_req_t *dest_am_out_reqs[] = {
1348 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1350 if (is_ia32_Lea(irn))
1353 am_support = get_ia32_am_support(irn);
1354 am_arity = get_ia32_am_arity(irn);
1355 block = get_nodes_block(irn);
1357 /* fold following patterns:
1358 * - op -> Load into AMop with am_Source
1360 * - op is am_Source capable AND
1361 * - the Load is only used by this op AND
1362 * - the Load is in the same block
1363 * - Store -> op -> Load into AMop with am_Dest
1365 * - op is am_Dest capable AND
1366 * - the Store uses the same address as the Load AND
1367 * - the Load is only used by this op AND
1368 * - the Load and Store are in the same block AND
1369 * - nobody else uses the result of the op
1371 if (am_support == ia32_am_None)
1374 assert(am_arity == ia32_am_unary || am_arity == ia32_am_binary);
1376 cand = is_am_candidate(h, block, irn);
1377 if (cand == IA32_AM_CAND_NONE)
1381 DBG((dbg, LEVEL_1, "\tfound address mode candidate %+F (candleft %d candright %d)... \n", irn,
1382 cand & IA32_AM_CAND_LEFT, cand & IA32_AM_CAND_RIGHT));
1384 left = get_irn_n(irn, 2);
1385 if (am_arity == ia32_am_unary) {
1387 assert(cand == IA32_AM_CAND_BOTH);
1389 right = get_irn_n(irn, 3);
1392 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1393 source_possible = am_support & ia32_am_Source ? 1 : 0;
1395 DBG((dbg, LEVEL_2, "\tdest_possible %d source_possible %d ... \n", dest_possible, source_possible));
1397 if (dest_possible) {
1402 /* we should only have 1 user which is a store */
1403 if (ia32_get_irn_n_edges(irn) == 1) {
1404 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1406 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1408 addr_b = get_irn_n(store, 0);
1409 addr_i = get_irn_n(store, 1);
1413 if (store == NULL) {
1414 DBG((dbg, LEVEL_2, "\tno store found, not using dest_mode\n"));
1419 if (dest_possible) {
1420 /* normalize nodes, we need the interesting load on the left side */
1421 if (cand & IA32_AM_CAND_RIGHT) {
1422 load = get_Proj_pred(right);
1423 if (load_store_addr_is_equal(load, store, addr_b, addr_i)
1424 && node_is_ia32_comm(irn)) {
1425 DBG((dbg, LEVEL_2, "\texchanging left/right\n"));
1426 exchange_left_right(irn, &left, &right, 3, 2);
1427 need_exchange_on_fail ^= 1;
1428 if (cand == IA32_AM_CAND_RIGHT)
1429 cand = IA32_AM_CAND_LEFT;
1434 if (dest_possible) {
1435 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1436 load = get_Proj_pred(left);
1438 #ifndef AGGRESSIVE_AM
1439 /* we have to be the only user of the load */
1440 if (get_irn_n_edges(left) > 1) {
1441 DBG((dbg, LEVEL_2, "\tmatching load has too may users, not using dest_mode\n"));
1446 DBG((dbg, LEVEL_2, "\tno matching load found, not using dest_mode"));
1451 if (dest_possible) {
1452 /* the store has to use the loads memory or the same memory
1454 ir_node *loadmem = get_irn_n(load, 2);
1455 ir_node *storemem = get_irn_n(store, 3);
1456 assert(get_irn_mode(loadmem) == mode_M);
1457 assert(get_irn_mode(storemem) == mode_M);
1458 /* TODO there could be a sync between store and load... */
1459 if(storemem != loadmem && (!is_Proj(storemem) || get_Proj_pred(storemem) != load)) {
1460 DBG((dbg, LEVEL_2, "\tload/store using different memories, not using dest_mode"));
1465 if (dest_possible) {
1466 /* Compare Load and Store address */
1467 if (!load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1468 DBG((dbg, LEVEL_2, "\taddresses not equal, not using dest_mode"));
1473 if (dest_possible) {
1474 ir_mode *lsmode = get_ia32_ls_mode(load);
1475 if(get_mode_size_bits(lsmode) != 32) {
1480 if (dest_possible) {
1481 /* all conditions fullfilled, do the transformation */
1482 assert(cand & IA32_AM_CAND_LEFT);
1484 /* set new base, index and attributes */
1485 set_irn_n(irn, 0, addr_b);
1486 set_irn_n(irn, 1, addr_i);
1487 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1488 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1489 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1490 set_ia32_op_type(irn, ia32_AddrModeD);
1491 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1492 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1494 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1495 if (is_ia32_am_sc_sign(load))
1496 set_ia32_am_sc_sign(irn);
1498 /* connect to Load memory and disconnect Load */
1499 if (am_arity == ia32_am_binary) {
1501 set_irn_n(irn, 4, get_irn_n(load, 2));
1502 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1505 set_irn_n(irn, 3, get_irn_n(load, 2));
1506 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1509 /* change node mode and out register requirements */
1510 set_irn_mode(irn, mode_M);
1511 set_ia32_out_req_all(irn, dest_am_out_reqs);
1513 /* connect the memory Proj of the Store to the op */
1514 edges_reroute(store, irn, irg);
1516 /* clear remat flag */
1517 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1519 try_remove_from_sched(store);
1520 try_remove_from_sched(load);
1521 DBG_OPT_AM_D(load, store, irn);
1523 DB((dbg, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1524 need_exchange_on_fail = 0;
1525 source_possible = 0;
1528 if (source_possible) {
1529 /* normalize ops, we need the load on the right */
1530 if(cand == IA32_AM_CAND_LEFT) {
1531 if(node_is_ia32_comm(irn)) {
1532 exchange_left_right(irn, &left, &right, 3, 2);
1533 need_exchange_on_fail ^= 1;
1534 cand = IA32_AM_CAND_RIGHT;
1536 source_possible = 0;
1541 if (source_possible) {
1542 /* all conditions fullfilled, do transform */
1543 assert(cand & IA32_AM_CAND_RIGHT);
1544 load = get_Proj_pred(right);
1546 if(get_irn_n_edges(load) > 1) {
1547 source_possible = 0;
1551 if (source_possible) {
1552 ir_mode *ls_mode = get_ia32_ls_mode(load);
1553 if(get_mode_size_bits(ls_mode) != 32)
1554 source_possible = 0;
1558 if (source_possible) {
1559 addr_b = get_irn_n(load, 0);
1560 addr_i = get_irn_n(load, 1);
1562 /* set new base, index and attributes */
1563 set_irn_n(irn, 0, addr_b);
1564 set_irn_n(irn, 1, addr_i);
1565 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1566 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1567 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1568 set_ia32_op_type(irn, ia32_AddrModeS);
1569 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1570 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1572 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1573 if (is_ia32_am_sc_sign(load))
1574 set_ia32_am_sc_sign(irn);
1576 /* clear remat flag */
1577 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1579 if (is_ia32_use_frame(load)) {
1580 if(get_ia32_frame_ent(load) == NULL) {
1581 set_ia32_need_stackent(irn);
1583 set_ia32_use_frame(irn);
1586 /* connect to Load memory and disconnect Load */
1587 if (am_arity == ia32_am_binary) {
1589 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
1590 set_irn_n(irn, 4, get_irn_n(load, 2));
1593 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1594 set_irn_n(irn, 3, get_irn_n(load, 2));
1597 DBG_OPT_AM_S(load, irn);
1599 /* If Load has a memory Proj, connect it to the op */
1600 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1601 if (mem_proj != NULL) {
1603 ir_mode *mode = get_irn_mode(irn);
1605 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1606 get_nodes_block(irn), new_Unknown(mode_T),
1608 set_irn_mode(irn, mode_T);
1609 edges_reroute(irn, res_proj, irg);
1610 set_Proj_pred(res_proj, irn);
1612 set_Proj_pred(mem_proj, irn);
1613 set_Proj_proj(mem_proj, 1);
1615 if(sched_is_scheduled(irn)) {
1616 sched_add_after(irn, res_proj);
1617 sched_add_after(irn, mem_proj);
1621 if(get_irn_n_edges(load) == 0) {
1622 try_remove_from_sched(load);
1624 need_exchange_on_fail = 0;
1626 DB((dbg, LEVEL_1, "merged with %+F into source AM\n", load));
1629 /* was exchanged but optimize failed: exchange back */
1630 if (need_exchange_on_fail) {
1631 exchange_left_right(irn, &left, &right, 3, 2);
1636 * Performs conv and address mode optimization.
1638 void ia32_optimize_graph(ia32_code_gen_t *cg) {
1639 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1640 if (! (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA))) {
1641 /* no optimizations at all */
1645 /* beware: we cannot optimize LEA and AM in one run because */
1646 /* LEA optimization adds new nodes to the irg which */
1647 /* invalidates the phase data */
1649 if (cg->opt & IA32_OPT_LEA) {
1650 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1654 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1656 /* hack for now, so these don't get created during optimize, because then
1657 * they will be unknown to the heights module
1659 ia32_new_NoReg_gp(cg);
1660 ia32_new_NoReg_fp(cg);
1661 ia32_new_NoReg_vfp(cg);
1663 if (cg->opt & IA32_OPT_DOAM) {
1664 /* we need height information for am optimization */
1665 heights_t *h = heights_new(cg->irg);
1666 ia32_am_opt_env_t env;
1671 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);
1677 void ia32_init_optimize(void)
1679 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");