3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universitaet Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
28 #include "../benode_t.h"
29 #include "../besched_t.h"
31 #include "ia32_new_nodes.h"
32 #include "bearch_ia32_t.h"
33 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "ia32_transform.h"
35 #include "ia32_dbg_stat.h"
36 #include "ia32_util.h"
41 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
42 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
43 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
44 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
47 typedef int is_op_func_t(const ir_node *n);
48 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
51 * checks if a node represents the NOREG value
53 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
54 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
57 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
59 We need to transform the consts twice:
60 - the psi condition tree transformer needs existing constants to be ia32 constants
61 - the psi condition tree transformer inserts new firm constants which need to be transformed
63 //ia32_transform_all_firm_consts(cg);
64 irg_walk_graph(cg->irg, NULL, ia32_transform_psi_cond_tree, cg);
65 //ia32_transform_all_firm_consts(cg);
68 /********************************************************************************************************
69 * _____ _ _ ____ _ _ _ _ _
70 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
71 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
72 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
73 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
74 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
77 ********************************************************************************************************/
80 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
83 static int ia32_const_equal(const ir_node *n1, const ir_node *n2) {
84 if(get_ia32_immop_type(n1) != get_ia32_immop_type(n2))
87 if(get_ia32_immop_type(n1) == ia32_ImmConst) {
88 return get_ia32_Immop_tarval(n1) == get_ia32_Immop_tarval(n2);
89 } else if(get_ia32_immop_type(n1) == ia32_ImmSymConst) {
90 return get_ia32_Immop_symconst(n1) == get_ia32_Immop_symconst(n2);
93 assert(get_ia32_immop_type(n1) == ia32_ImmNone);
98 * Checks for potential CJmp/CJmpAM optimization candidates.
100 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
101 ir_node *cand = NULL;
102 ir_node *prev = sched_prev(irn);
104 if (is_Block(prev)) {
105 if (get_Block_n_cfgpreds(prev) == 1)
106 prev = get_Block_cfgpred(prev, 0);
111 /* The predecessor must be a ProjX. */
112 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
113 prev = get_Proj_pred(prev);
115 if (is_op_func(prev))
122 static int is_TestJmp_cand(const ir_node *irn) {
123 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
127 * Checks if two consecutive arguments of cand matches
128 * the two arguments of irn (TestJmp).
130 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
131 ir_node *in1 = get_irn_n(irn, 0);
132 ir_node *in2 = get_irn_n(irn, 1);
133 int i, n = get_irn_arity(cand);
136 for (i = 0; i < n - 1; i++) {
137 if (get_irn_n(cand, i) == in1 &&
138 get_irn_n(cand, i + 1) == in2)
148 return ia32_const_equal(cand, irn);
152 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
154 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
155 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
158 /* we found a possible candidate */
159 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
162 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
164 if (is_ia32_And(cand))
165 set_irn_op(irn, op_ia32_CJmpAM);
167 set_irn_op(irn, op_ia32_CJmp);
169 DB((cg->mod, LEVEL_1, "%+F\n", irn));
173 static int is_CondJmp_cand(const ir_node *irn) {
174 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
178 * Checks if the arguments of cand are the same of irn.
180 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
183 arity = get_irn_arity(cand);
184 for (i = 0; i < arity; i++) {
185 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
190 return ia32_const_equal(cand, irn);
194 * Tries to replace a CondJmp by a CJmpAM
196 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
197 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
200 /* we found a possible candidate */
201 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
204 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
207 set_irn_op(irn, op_ia32_CJmpAM);
209 DB((cg->mod, LEVEL_1, "%+F\n", irn));
213 // only optimize up to 48 stores behind IncSPs
214 #define MAXPUSH_OPTIMIZE 48
217 * Tries to create pushs from IncSP,Store combinations
219 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
223 ir_node *stores[MAXPUSH_OPTIMIZE];
224 ir_node *block = get_nodes_block(irn);
225 ir_graph *irg = cg->irg;
227 ir_mode *spmode = get_irn_mode(irn);
229 memset(stores, 0, sizeof(stores));
231 assert(be_is_IncSP(irn));
233 offset = be_get_IncSP_offset(irn);
238 * We first walk the schedule after the IncSP node as long as we find
239 * suitable stores that could be transformed to a push.
240 * We save them into the stores array which is sorted by the frame offset/4
241 * attached to the node
243 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
248 // it has to be a store
249 if(!is_ia32_Store(node))
252 // it has to use our sp value
253 if(get_irn_n(node, 0) != irn)
255 // store has to be attached to NoMem
256 mem = get_irn_n(node, 3);
261 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
264 offset = get_ia32_am_offs_int(node);
266 storeslot = offset / 4;
267 if(storeslot >= MAXPUSH_OPTIMIZE)
270 // storing into the same slot twice is bad (and shouldn't happen...)
271 if(stores[storeslot] != NULL)
274 // storing at half-slots is bad
278 stores[storeslot] = node;
281 curr_sp = get_irn_n(irn, 0);
283 // walk the stores in inverse order and create pushs for them
284 i = (offset / 4) - 1;
285 if(i >= MAXPUSH_OPTIMIZE) {
286 i = MAXPUSH_OPTIMIZE - 1;
289 for( ; i >= 0; --i) {
290 const arch_register_t *spreg;
292 ir_node *val, *mem, *mem_proj;
293 ir_node *store = stores[i];
294 ir_node *noreg = ia32_new_NoReg_gp(cg);
296 if(store == NULL || is_Bad(store))
299 val = get_irn_n(store, 2);
300 mem = get_irn_n(store, 3);
301 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
304 push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
306 set_ia32_am_support(push, ia32_am_Source);
307 copy_ia32_Immop_attr(push, store);
309 sched_add_before(irn, push);
311 // create stackpointer proj
312 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
313 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
314 sched_add_before(irn, curr_sp);
316 // create memory proj
317 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
318 sched_add_before(irn, mem_proj);
320 // use the memproj now
321 exchange(store, mem_proj);
323 // we can remove the store now
329 be_set_IncSP_offset(irn, offset);
331 // can we remove the IncSP now?
333 const ir_edge_t *edge, *next;
335 foreach_out_edge_safe(irn, edge, next) {
336 ir_node *arg = get_edge_src_irn(edge);
337 int pos = get_edge_src_pos(edge);
339 set_irn_n(arg, pos, curr_sp);
342 set_irn_n(irn, 0, new_Bad());
345 set_irn_n(irn, 0, curr_sp);
351 * Tries to optimize two following IncSP.
353 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
354 ir_node *prev = be_get_IncSP_pred(irn);
355 int real_uses = get_irn_n_edges(prev);
357 if (be_is_IncSP(prev) && real_uses == 1) {
358 /* first IncSP has only one IncSP user, kill the first one */
359 int prev_offs = be_get_IncSP_offset(prev);
360 int curr_offs = be_get_IncSP_offset(irn);
362 be_set_IncSP_offset(prev, prev_offs + curr_offs);
364 /* Omit the optimized IncSP */
365 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
367 set_irn_n(prev, 0, new_Bad());
374 * Performs Peephole Optimizations.
376 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
377 ia32_code_gen_t *cg = env;
379 /* AMD CPUs want explicit compare before conditional jump */
380 if (! ARCH_AMD(cg->opt_arch)) {
381 if (is_ia32_TestJmp(irn))
382 ia32_optimize_TestJmp(irn, cg);
383 else if (is_ia32_CondJmp(irn))
384 ia32_optimize_CondJmp(irn, cg);
387 if (be_is_IncSP(irn)) {
388 // optimize_IncSP doesn't respect dependency edges yet...
389 //ia32_optimize_IncSP(irn, cg);
391 if (cg->opt & IA32_OPT_PUSHARGS)
392 ia32_create_Pushs(irn, cg);
396 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
397 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
400 /******************************************************************
402 * /\ | | | | | \/ | | |
403 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
404 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
405 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
406 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
408 ******************************************************************/
415 static int node_is_ia32_comm(const ir_node *irn) {
416 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
419 static int ia32_get_irn_n_edges(const ir_node *irn) {
420 const ir_edge_t *edge;
423 foreach_out_edge(irn, edge) {
431 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
433 * @param pred The node to be checked
434 * @param is_op_func The check-function
435 * @return 1 if conditions are fulfilled, 0 otherwise
437 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
438 return is_op_func(pred);
442 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
443 * and if the predecessor is in block bl.
445 * @param bl The block
446 * @param pred The node to be checked
447 * @param is_op_func The check-function
448 * @return 1 if conditions are fulfilled, 0 otherwise
450 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
451 int (*is_op_func)(const ir_node *n))
454 pred = get_Proj_pred(pred);
455 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
464 * Checks if irn is a candidate for address calculation. We avoid transforming
465 * adds to leas if they have a load as pred, because then we can use AM mode
468 * - none of the operand must be a Load within the same block OR
469 * - all Loads must have more than one user OR
471 * @param block The block the Loads must/mustnot be in
472 * @param irn The irn to check
473 * return 1 if irn is a candidate, 0 otherwise
475 static int is_addr_candidate(const ir_node *irn) {
476 #ifndef AGGRESSIVE_AM
477 const ir_node *block = get_nodes_block(irn);
478 ir_node *left, *right;
481 left = get_irn_n(irn, 2);
482 right = get_irn_n(irn, 3);
484 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
485 n = ia32_get_irn_n_edges(left);
486 /* load with only one user: don't create LEA */
491 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
492 n = ia32_get_irn_n_edges(right);
502 * Checks if irn is a candidate for address mode.
505 * - at least one operand has to be a Load within the same block AND
506 * - the load must not have other users than the irn AND
507 * - the irn must not have a frame entity set
509 * @param cg The ia32 code generator
510 * @param h The height information of the irg
511 * @param block The block the Loads must/mustnot be in
512 * @param irn The irn to check
513 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
515 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
516 ir_node *in, *load, *other, *left, *right;
517 int is_cand = 0, cand;
520 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
521 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
524 left = get_irn_n(irn, 2);
525 arity = get_irn_arity(irn);
526 assert(arity == 5 || arity == 4);
529 right = get_irn_n(irn, 3);
537 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
538 #ifndef AGGRESSIVE_AM
540 n = ia32_get_irn_n_edges(in);
541 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
546 load = get_Proj_pred(in);
549 /* 8bit Loads are not supported (for binary ops),
550 * they cannot be used with every register */
551 if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
552 assert(get_irn_arity(irn) == 5);
556 /* If there is a data dependency of other irn from load: cannot use AM */
557 if (is_cand && get_nodes_block(other) == block) {
558 other = skip_Proj(other);
559 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
560 /* this could happen in loops */
561 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
565 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
569 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
570 #ifndef AGGRESSIVE_AM
572 n = ia32_get_irn_n_edges(in);
573 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
578 load = get_Proj_pred(in);
581 /* 8bit Loads are not supported, they cannot be used with every register */
582 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
585 /* If there is a data dependency of other irn from load: cannot use load */
586 if (is_cand && get_nodes_block(other) == block) {
587 other = skip_Proj(other);
588 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
589 /* this could happen in loops */
590 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
594 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
596 /* if the irn has a frame entity: we do not use address mode */
597 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
601 * Compares the base and index addr and the load/store entities
602 * and returns 1 if they are equal.
604 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
605 const ir_node *addr_b, const ir_node *addr_i)
607 if(get_irn_n(load, 0) != addr_b)
609 if(get_irn_n(load, 1) != addr_i)
612 if(get_ia32_frame_ent(load) != get_ia32_frame_ent(store))
615 if(get_ia32_am_sc(load) != get_ia32_am_sc(store))
617 if(is_ia32_am_sc_sign(load) != is_ia32_am_sc_sign(store))
619 if(get_ia32_am_offs_int(load) != get_ia32_am_offs_int(store))
621 if(get_ia32_ls_mode(load) != get_ia32_ls_mode(store))
627 typedef enum _ia32_take_lea_attr {
628 IA32_LEA_ATTR_NONE = 0,
629 IA32_LEA_ATTR_BASE = (1 << 0),
630 IA32_LEA_ATTR_INDEX = (1 << 1),
631 IA32_LEA_ATTR_OFFS = (1 << 2),
632 IA32_LEA_ATTR_SCALE = (1 << 3),
633 IA32_LEA_ATTR_AMSC = (1 << 4),
634 IA32_LEA_ATTR_FENT = (1 << 5)
635 } ia32_take_lea_attr;
638 * Decides if we have to keep the LEA operand or if we can assimilate it.
640 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
641 int have_am_sc, ia32_code_gen_t *cg)
643 ir_entity *irn_ent = get_ia32_frame_ent(irn);
644 ir_entity *lea_ent = get_ia32_frame_ent(lea);
646 int is_noreg_base = be_is_NoReg(cg, base);
647 int is_noreg_index = be_is_NoReg(cg, index);
648 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
650 /* If the Add and the LEA both have a different frame entity set: keep */
651 if (irn_ent && lea_ent && (irn_ent != lea_ent))
652 return IA32_LEA_ATTR_NONE;
653 else if (! irn_ent && lea_ent)
654 ret_val |= IA32_LEA_ATTR_FENT;
656 /* If the Add and the LEA both have already an address mode symconst: keep */
657 if (have_am_sc && get_ia32_am_sc(lea))
658 return IA32_LEA_ATTR_NONE;
659 else if (get_ia32_am_sc(lea))
660 ret_val |= IA32_LEA_ATTR_AMSC;
662 /* Check the different base-index combinations */
664 if (! is_noreg_base && ! is_noreg_index) {
665 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
666 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
667 if (am_flav & ia32_O)
668 ret_val |= IA32_LEA_ATTR_OFFS;
670 ret_val |= IA32_LEA_ATTR_BASE;
673 return IA32_LEA_ATTR_NONE;
675 else if (! is_noreg_base && is_noreg_index) {
676 /* Base is set but index not */
678 /* Base points to LEA: assimilate everything */
679 if (am_flav & ia32_O)
680 ret_val |= IA32_LEA_ATTR_OFFS;
681 if (am_flav & ia32_S)
682 ret_val |= IA32_LEA_ATTR_SCALE;
683 if (am_flav & ia32_I)
684 ret_val |= IA32_LEA_ATTR_INDEX;
686 ret_val |= IA32_LEA_ATTR_BASE;
688 else if (am_flav & ia32_B ? 0 : 1) {
689 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
690 if (am_flav & ia32_O)
691 ret_val |= IA32_LEA_ATTR_OFFS;
692 if (am_flav & ia32_S)
693 ret_val |= IA32_LEA_ATTR_SCALE;
695 ret_val |= IA32_LEA_ATTR_INDEX;
698 return IA32_LEA_ATTR_NONE;
700 else if (is_noreg_base && ! is_noreg_index) {
701 /* Index is set but not base */
703 /* Index points to LEA: assimilate everything */
704 if (am_flav & ia32_O)
705 ret_val |= IA32_LEA_ATTR_OFFS;
706 if (am_flav & ia32_S)
707 ret_val |= IA32_LEA_ATTR_SCALE;
708 if (am_flav & ia32_B)
709 ret_val |= IA32_LEA_ATTR_BASE;
711 ret_val |= IA32_LEA_ATTR_INDEX;
713 else if (am_flav & ia32_I ? 0 : 1) {
714 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
715 if (am_flav & ia32_O)
716 ret_val |= IA32_LEA_ATTR_OFFS;
717 if (am_flav & ia32_S)
718 ret_val |= IA32_LEA_ATTR_SCALE;
720 ret_val |= IA32_LEA_ATTR_BASE;
723 return IA32_LEA_ATTR_NONE;
726 assert(0 && "There must have been set base or index");
733 * Adds res before irn into schedule if irn was scheduled.
734 * @param irn The schedule point
735 * @param res The node to be scheduled
737 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
738 if (sched_is_scheduled(irn))
739 sched_add_before(irn, res);
743 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
744 * all it's Projs are removed as well.
745 * @param irn The irn to be removed from schedule
747 static INLINE void try_remove_from_sched(ir_node *node) {
750 if(get_irn_mode(node) == mode_T) {
751 const ir_edge_t *edge;
752 foreach_out_edge(node, edge) {
753 ir_node *proj = get_edge_src_irn(edge);
754 try_remove_from_sched(proj);
758 if(get_irn_n_edges(node) != 0)
761 if (sched_is_scheduled(node)) {
765 arity = get_irn_arity(node);
766 for(i = 0; i < arity; ++i) {
767 set_irn_n(node, i, new_Bad());
772 * Folds Add or Sub to LEA if possible
774 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
775 ir_graph *irg = get_irn_irg(irn);
776 dbg_info *dbg = get_irn_dbg_info(irn);
777 ir_node *block = get_nodes_block(irn);
779 ir_node *shift = NULL;
780 ir_node *lea_o = NULL;
791 ir_entity *lea_ent = NULL;
792 ir_node *noreg = ia32_new_NoReg_gp(cg);
793 ir_node *left, *right, *temp;
794 ir_node *base, *index;
795 int consumed_left_shift;
796 ia32_am_flavour_t am_flav;
797 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
799 if (is_ia32_Add(irn))
802 left = get_irn_n(irn, 2);
803 right = get_irn_n(irn, 3);
805 /* "normalize" arguments in case of add with two operands */
806 if (isadd && ! be_is_NoReg(cg, right)) {
807 /* put LEA == ia32_am_O as right operand */
808 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
809 set_irn_n(irn, 2, right);
810 set_irn_n(irn, 3, left);
816 /* put LEA != ia32_am_O as left operand */
817 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
818 set_irn_n(irn, 2, right);
819 set_irn_n(irn, 3, left);
825 /* put SHL as left operand iff left is NOT a LEA */
826 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
827 set_irn_n(irn, 2, right);
828 set_irn_n(irn, 3, left);
841 /* check for operation with immediate */
842 if (is_ia32_ImmConst(irn)) {
843 tarval *tv = get_ia32_Immop_tarval(irn);
845 DBG((mod, LEVEL_1, "\tfound op with imm const"));
847 offs_cnst = get_tarval_long(tv);
850 else if (isadd && is_ia32_ImmSymConst(irn)) {
851 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
855 am_sc = get_ia32_Immop_symconst(irn);
856 am_sc_sign = is_ia32_am_sc_sign(irn);
859 /* determine the operand which needs to be checked */
860 temp = be_is_NoReg(cg, right) ? left : right;
862 /* check if right operand is AMConst (LEA with ia32_am_O) */
863 /* but we can only eat it up if there is no other symconst */
864 /* because the linker won't accept two symconsts */
865 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
866 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
868 offs_lea = get_ia32_am_offs_int(temp);
869 am_sc = get_ia32_am_sc(temp);
870 am_sc_sign = is_ia32_am_sc_sign(temp);
877 else if (temp == right)
882 /* default for add -> make right operand to index */
885 consumed_left_shift = -1;
887 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
889 /* determine the operand which needs to be checked */
891 if (is_ia32_Lea(left)) {
893 consumed_left_shift = 0;
896 /* check for SHL 1,2,3 */
897 if (pred_is_specific_node(temp, is_ia32_Shl)) {
899 if (is_ia32_ImmConst(temp)) {
900 long shiftval = get_tarval_long(get_ia32_Immop_tarval(temp));
903 index = get_irn_n(temp, 2);
904 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
908 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
914 if (! be_is_NoReg(cg, index)) {
915 /* if we have index, but left == right -> no base */
919 else if (consumed_left_shift == 1) {
920 /* -> base is right operand */
921 base = (right == lea_o) ? noreg : right;
926 /* Try to assimilate a LEA as left operand */
927 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
928 /* check if we can assimilate the LEA */
929 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
931 if (take_attr == IA32_LEA_ATTR_NONE) {
932 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
935 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
936 lea = left; /* for statistics */
938 if (take_attr & IA32_LEA_ATTR_OFFS)
939 offs = get_ia32_am_offs_int(left);
941 if (take_attr & IA32_LEA_ATTR_AMSC) {
942 am_sc = get_ia32_am_sc(left);
944 am_sc_sign = is_ia32_am_sc_sign(left);
947 if (take_attr & IA32_LEA_ATTR_SCALE)
948 scale = get_ia32_am_scale(left);
950 if (take_attr & IA32_LEA_ATTR_BASE)
951 base = get_irn_n(left, 0);
953 if (take_attr & IA32_LEA_ATTR_INDEX)
954 index = get_irn_n(left, 1);
956 if (take_attr & IA32_LEA_ATTR_FENT)
957 lea_ent = get_ia32_frame_ent(left);
961 /* ok, we can create a new LEA */
963 res = new_rd_ia32_Lea(dbg, irg, block, base, index);
965 /* add the old offset of a previous LEA */
966 add_ia32_am_offs_int(res, offs);
968 /* add the new offset */
970 add_ia32_am_offs_int(res, offs_cnst);
971 add_ia32_am_offs_int(res, offs_lea);
973 /* either lea_O-cnst, -cnst or -lea_O */
974 if (offs_cnst != 0) {
975 add_ia32_am_offs_int(res, offs_lea);
976 add_ia32_am_offs_int(res, -offs_cnst);
978 add_ia32_am_offs_int(res, offs_lea);
982 /* set the address mode symconst */
984 set_ia32_am_sc(res, am_sc);
986 set_ia32_am_sc_sign(res);
989 /* copy the frame entity (could be set in case of Add */
990 /* which was a FrameAddr) */
991 if (lea_ent != NULL) {
992 set_ia32_frame_ent(res, lea_ent);
993 set_ia32_use_frame(res);
995 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
996 if(is_ia32_use_frame(irn))
997 set_ia32_use_frame(res);
1001 set_ia32_am_scale(res, scale);
1003 am_flav = ia32_am_N;
1004 /* determine new am flavour */
1005 if (offs || offs_cnst || offs_lea || have_am_sc) {
1008 if (! be_is_NoReg(cg, base)) {
1011 if (! be_is_NoReg(cg, index)) {
1017 set_ia32_am_flavour(res, am_flav);
1019 set_ia32_op_type(res, ia32_AddrModeS);
1021 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1023 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %d]\n", base, index, scale, get_ia32_am_offs_int(res)));
1025 /* we will exchange it, report here before the Proj is created */
1026 if (shift && lea && lea_o) {
1027 try_remove_from_sched(shift);
1028 try_remove_from_sched(lea);
1029 try_remove_from_sched(lea_o);
1030 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1032 else if (shift && lea) {
1033 try_remove_from_sched(shift);
1034 try_remove_from_sched(lea);
1035 DBG_OPT_LEA3(irn, lea, shift, res);
1037 else if (shift && lea_o) {
1038 try_remove_from_sched(shift);
1039 try_remove_from_sched(lea_o);
1040 DBG_OPT_LEA3(irn, lea_o, shift, res);
1042 else if (lea && lea_o) {
1043 try_remove_from_sched(lea);
1044 try_remove_from_sched(lea_o);
1045 DBG_OPT_LEA3(irn, lea_o, lea, res);
1048 try_remove_from_sched(shift);
1049 DBG_OPT_LEA2(irn, shift, res);
1052 try_remove_from_sched(lea);
1053 DBG_OPT_LEA2(irn, lea, res);
1056 try_remove_from_sched(lea_o);
1057 DBG_OPT_LEA2(irn, lea_o, res);
1060 DBG_OPT_LEA1(irn, res);
1062 /* get the result Proj of the Add/Sub */
1063 try_add_to_sched(irn, res);
1064 try_remove_from_sched(irn);
1066 assert(irn && "Couldn't find result proj");
1068 /* exchange the old op with the new LEA */
1077 * Merges a Load/Store node with a LEA.
1078 * @param irn The Load/Store node
1079 * @param lea The LEA
1081 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1082 ir_entity *irn_ent = get_ia32_frame_ent(irn);
1083 ir_entity *lea_ent = get_ia32_frame_ent(lea);
1085 /* If the irn and the LEA both have a different frame entity set: do not merge */
1086 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
1088 else if (irn_ent == NULL && lea_ent != NULL) {
1089 set_ia32_frame_ent(irn, lea_ent);
1090 set_ia32_use_frame(irn);
1093 /* get the AM attributes from the LEA */
1094 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
1095 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1096 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1098 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1099 if (is_ia32_am_sc_sign(lea))
1100 set_ia32_am_sc_sign(irn);
1102 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1104 /* set base and index */
1105 set_irn_n(irn, 0, get_irn_n(lea, 0));
1106 set_irn_n(irn, 1, get_irn_n(lea, 1));
1108 try_remove_from_sched(lea);
1110 /* clear remat flag */
1111 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1113 if (is_ia32_Ld(irn))
1114 DBG_OPT_LOAD_LEA(lea, irn);
1116 DBG_OPT_STORE_LEA(lea, irn);
1121 * Sets new_right index of irn to right and new_left index to left.
1122 * Also exchange left and right
1124 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1127 set_irn_n(irn, new_right, *right);
1128 set_irn_n(irn, new_left, *left);
1134 /* this is only needed for Compares, but currently ALL nodes
1135 * have this attribute :-) */
1136 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1140 * Performs address calculation optimization (create LEAs if possible)
1142 static void optimize_lea(ir_node *irn, void *env) {
1143 ia32_code_gen_t *cg = env;
1145 if (! is_ia32_irn(irn))
1148 /* Following cases can occur: */
1149 /* - Sub (l, imm) -> LEA [base - offset] */
1150 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1151 /* - Add (l, imm) -> LEA [base + offset] */
1152 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1153 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1154 /* - Add (l, r) -> LEA [base + index * scale] */
1155 /* with scale > 1 iff l/r == shl (1,2,3) */
1156 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1159 if(!is_addr_candidate(irn))
1162 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1163 res = fold_addr(cg, irn);
1166 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1168 DB((cg->mod, LEVEL_1, "not transformed\n"));
1169 } else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1170 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1171 /* - Store -> LEA into Store } it might be better to keep the LEA */
1172 ir_node *left = get_irn_n(irn, 0);
1174 if (is_ia32_Lea(left)) {
1175 const ir_edge_t *edge, *ne;
1178 /* merge all Loads/Stores connected to this LEA with the LEA */
1179 foreach_out_edge_safe(left, edge, ne) {
1180 src = get_edge_src_irn(edge);
1182 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1183 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1184 if (! is_ia32_got_lea(src))
1185 merge_loadstore_lea(src, left);
1186 set_ia32_got_lea(src);
1194 * Checks for address mode patterns and performs the
1195 * necessary transformations.
1196 * This function is called by a walker.
1198 static void optimize_am(ir_node *irn, void *env) {
1199 ia32_am_opt_env_t *am_opt_env = env;
1200 ia32_code_gen_t *cg = am_opt_env->cg;
1201 ir_graph *irg = get_irn_irg(irn);
1202 heights_t *h = am_opt_env->h;
1203 ir_node *block, *left, *right;
1204 ir_node *store, *load, *mem_proj;
1205 ir_node *addr_b, *addr_i;
1206 int need_exchange_on_fail = 0;
1207 ia32_am_type_t am_support;
1208 ia32_am_cand_t cand;
1209 ia32_am_cand_t orig_cand;
1211 int source_possible;
1212 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1214 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1216 if (is_ia32_Lea(irn))
1219 am_support = get_ia32_am_support(irn);
1220 block = get_nodes_block(irn);
1222 DBG((mod, LEVEL_1, "checking for AM\n"));
1224 /* fold following patterns: */
1225 /* - op -> Load into AMop with am_Source */
1227 /* - op is am_Source capable AND */
1228 /* - the Load is only used by this op AND */
1229 /* - the Load is in the same block */
1230 /* - Store -> op -> Load into AMop with am_Dest */
1232 /* - op is am_Dest capable AND */
1233 /* - the Store uses the same address as the Load AND */
1234 /* - the Load is only used by this op AND */
1235 /* - the Load and Store are in the same block AND */
1236 /* - nobody else uses the result of the op */
1237 if (get_ia32_am_support(irn) == ia32_am_None)
1240 cand = is_am_candidate(cg, h, block, irn);
1241 if (cand == IA32_AM_CAND_NONE)
1245 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1247 left = get_irn_n(irn, 2);
1248 if (get_irn_arity(irn) == 4) {
1249 /* it's an "unary" operation */
1251 assert(cand == IA32_AM_CAND_BOTH);
1253 right = get_irn_n(irn, 3);
1256 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1257 source_possible = am_support & ia32_am_Source ? 1 : 0;
1259 if (dest_possible) {
1264 /* we should only have 1 user which is a store */
1265 if (ia32_get_irn_n_edges(irn) == 1) {
1266 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1268 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1270 addr_b = get_irn_n(store, 0);
1271 addr_i = get_irn_n(store, 1);
1275 if (store == NULL) {
1280 if (dest_possible) {
1281 /* normalize nodes, we need the interesting load on the left side */
1282 if (cand & IA32_AM_CAND_RIGHT) {
1283 load = get_Proj_pred(right);
1284 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1285 exchange_left_right(irn, &left, &right, 3, 2);
1286 need_exchange_on_fail ^= 1;
1287 if (cand == IA32_AM_CAND_RIGHT)
1288 cand = IA32_AM_CAND_LEFT;
1293 if (dest_possible) {
1294 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1295 load = get_Proj_pred(left);
1297 #ifndef AGGRESSIVE_AM
1298 /* we have to be the only user of the load */
1299 if (get_irn_n_edges(left) > 1) {
1308 if (dest_possible) {
1309 /* the store has to use the loads memory or the same memory
1311 ir_node *loadmem = get_irn_n(load, 2);
1312 ir_node *storemem = get_irn_n(store, 3);
1313 assert(get_irn_mode(loadmem) == mode_M);
1314 assert(get_irn_mode(storemem) == mode_M);
1315 if(storemem != loadmem || !is_Proj(storemem)
1316 || get_Proj_pred(storemem) != load) {
1321 if (dest_possible) {
1322 /* Compare Load and Store address */
1323 if (!load_store_addr_is_equal(load, store, addr_b, addr_i))
1327 if (dest_possible) {
1328 /* all conditions fullfilled, do the transformation */
1329 assert(cand & IA32_AM_CAND_LEFT);
1331 /* set new base, index and attributes */
1332 set_irn_n(irn, 0, addr_b);
1333 set_irn_n(irn, 1, addr_i);
1334 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1335 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1336 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1337 set_ia32_op_type(irn, ia32_AddrModeD);
1338 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1339 if(is_ia32_use_frame(load))
1340 set_ia32_use_frame(irn);
1341 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1343 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1344 if (is_ia32_am_sc_sign(load))
1345 set_ia32_am_sc_sign(irn);
1347 if (is_ia32_use_frame(load))
1348 set_ia32_use_frame(irn);
1350 /* connect to Load memory and disconnect Load */
1351 if (get_irn_arity(irn) == 5) {
1353 set_irn_n(irn, 4, get_irn_n(load, 2));
1354 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1357 set_irn_n(irn, 3, get_irn_n(load, 2));
1358 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1361 set_irn_mode(irn, mode_M);
1363 /* connect the memory Proj of the Store to the op */
1364 mem_proj = ia32_get_proj_for_mode(store, mode_M);
1365 edges_reroute(mem_proj, irn, irg);
1367 /* clear remat flag */
1368 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1370 try_remove_from_sched(load);
1371 try_remove_from_sched(store);
1372 DBG_OPT_AM_D(load, store, irn);
1374 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1375 need_exchange_on_fail = 0;
1376 source_possible = 0;
1379 if (source_possible) {
1380 /* normalize ops, we need the load on the right */
1381 if(cand == IA32_AM_CAND_LEFT) {
1382 if(node_is_ia32_comm(irn)) {
1383 exchange_left_right(irn, &left, &right, 3, 2);
1384 need_exchange_on_fail ^= 1;
1385 cand = IA32_AM_CAND_RIGHT;
1387 source_possible = 0;
1392 if (source_possible) {
1393 /* all conditions fullfilled, do transform */
1394 assert(cand & IA32_AM_CAND_RIGHT);
1395 load = get_Proj_pred(right);
1397 if(get_irn_n_edges(load) > 1) {
1398 source_possible = 0;
1402 if (source_possible) {
1403 addr_b = get_irn_n(load, 0);
1404 addr_i = get_irn_n(load, 1);
1406 /* set new base, index and attributes */
1407 set_irn_n(irn, 0, addr_b);
1408 set_irn_n(irn, 1, addr_i);
1409 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1410 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1411 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1412 set_ia32_op_type(irn, ia32_AddrModeS);
1413 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1414 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1416 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1417 if (is_ia32_am_sc_sign(load))
1418 set_ia32_am_sc_sign(irn);
1420 /* clear remat flag */
1421 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1423 if (is_ia32_use_frame(load))
1424 set_ia32_use_frame(irn);
1426 /* connect to Load memory and disconnect Load */
1427 if (get_irn_arity(irn) == 5) {
1429 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
1430 set_irn_n(irn, 4, get_irn_n(load, 2));
1432 assert(get_irn_arity(irn) == 4);
1434 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1435 set_irn_n(irn, 3, get_irn_n(load, 2));
1438 DBG_OPT_AM_S(load, irn);
1440 /* If Load has a memory Proj, connect it to the op */
1441 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1442 if (mem_proj != NULL) {
1444 ir_mode *mode = get_irn_mode(irn);
1446 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1447 get_nodes_block(irn), new_Unknown(mode_T),
1449 set_irn_mode(irn, mode_T);
1450 edges_reroute(irn, res_proj, irg);
1451 set_Proj_pred(res_proj, irn);
1453 set_Proj_pred(mem_proj, irn);
1454 set_Proj_proj(mem_proj, 1);
1456 if(sched_is_scheduled(irn)) {
1457 sched_add_after(irn, res_proj);
1458 sched_add_after(irn, mem_proj);
1462 if(get_irn_n_edges(load) == 0) {
1463 try_remove_from_sched(load);
1465 need_exchange_on_fail = 0;
1467 DB((mod, LEVEL_1, "merged with %+F into source AM\n", load));
1470 /* was exchanged but optimize failed: exchange back */
1471 if (need_exchange_on_fail) {
1472 exchange_left_right(irn, &left, &right, 3, 2);
1477 * Performs address mode optimization.
1479 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1480 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1481 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1482 edges_deactivate(cg->irg);
1483 edges_activate(cg->irg);
1486 /* no optimizations at all */
1490 /* beware: we cannot optimize LEA and AM in one run because */
1491 /* LEA optimization adds new nodes to the irg which */
1492 /* invalidates the phase data */
1494 if (cg->opt & IA32_OPT_LEA) {
1495 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1499 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1501 if (cg->opt & IA32_OPT_DOAM) {
1502 /* we need height information for am optimization */
1503 heights_t *h = heights_new(cg->irg);
1504 ia32_am_opt_env_t env;
1509 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);