2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, val, base);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* happens rarely, but if it does code will panic' */
258 if (is_ia32_Unknown_GP(left))
261 /* walk schedule up and abort when we find left or some other node destroys
263 schedpoint = sched_prev(node);
264 while(schedpoint != left) {
265 schedpoint = sched_prev(schedpoint);
266 if(arch_irn_is(arch_env, schedpoint, modify_flags))
268 if(schedpoint == block)
269 panic("couldn't find left");
272 /* make sure only Lg/Eq tests are used */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 int pnc = get_ia32_condcode(user);
277 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
282 if(!produces_zero_flag(left, pn))
285 left = turn_into_mode_t(left);
287 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
288 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
290 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
292 assert(get_irn_mode(node) != mode_T);
294 be_peephole_before_exchange(node, flags_proj);
295 exchange(node, flags_proj);
297 be_peephole_after_exchange(flags_proj);
301 * AMD Athlon works faster when RET is not destination of
302 * conditional jump or directly preceded by other jump instruction.
303 * Can be avoided by placing a Rep prefix before the return.
305 static void peephole_ia32_Return(ir_node *node) {
306 ir_node *block, *irn;
308 if (!ia32_cg_config.use_pad_return)
311 block = get_nodes_block(node);
313 if (get_Block_n_cfgpreds(block) == 1) {
314 ir_node *pred = get_Block_cfgpred(block, 0);
317 /* The block of the return has only one predecessor,
318 which jumps directly to this block.
319 This jump will be encoded as a fall through, so we
321 However, the predecessor might be empty, so it must be
322 ensured that empty blocks are gone away ... */
327 /* check if this return is the first on the block */
328 sched_foreach_reverse_from(node, irn) {
329 switch (get_irn_opcode(irn)) {
331 /* the return node itself, ignore */
334 /* ignore the barrier, no code generated */
337 /* arg, IncSP 0 nodes might occur, ignore these */
338 if (be_get_IncSP_offset(irn) == 0)
347 /* yep, return is the first real instruction in this block */
350 /* add an rep prefix to the return */
351 ir_node *rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
353 sched_add_before(node, rep);
356 /* ensure, that the 3 byte return is generated */
357 be_Return_set_emit_pop(node, 1);
361 /* only optimize up to 48 stores behind IncSPs */
362 #define MAXPUSH_OPTIMIZE 48
365 * Tries to create pushs from IncSP,Store combinations.
366 * The Stores are replaced by Push's, the IncSP is modified
367 * (possibly into IncSP 0, but not removed).
369 static void peephole_IncSP_Store_to_push(ir_node *irn)
374 ir_node *stores[MAXPUSH_OPTIMIZE];
375 ir_node *block = get_nodes_block(irn);
376 ir_graph *irg = cg->irg;
378 ir_mode *spmode = get_irn_mode(irn);
380 memset(stores, 0, sizeof(stores));
382 assert(be_is_IncSP(irn));
384 offset = be_get_IncSP_offset(irn);
389 * We first walk the schedule after the IncSP node as long as we find
390 * suitable stores that could be transformed to a push.
391 * We save them into the stores array which is sorted by the frame offset/4
392 * attached to the node
394 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
399 // it has to be a store
400 if(!is_ia32_Store(node))
403 // it has to use our sp value
404 if(get_irn_n(node, n_ia32_base) != irn)
406 // store has to be attached to NoMem
407 mem = get_irn_n(node, n_ia32_mem);
412 /* unfortunately we can't support the full AMs possible for push at the
413 * moment. TODO: fix this */
414 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
417 offset = get_ia32_am_offs_int(node);
419 storeslot = offset / 4;
420 if(storeslot >= MAXPUSH_OPTIMIZE)
423 // storing into the same slot twice is bad (and shouldn't happen...)
424 if(stores[storeslot] != NULL)
427 // storing at half-slots is bad
431 stores[storeslot] = node;
434 curr_sp = be_get_IncSP_pred(irn);
436 // walk the stores in inverse order and create pushs for them
437 i = (offset / 4) - 1;
438 if(i >= MAXPUSH_OPTIMIZE) {
439 i = MAXPUSH_OPTIMIZE - 1;
442 for( ; i >= 0; --i) {
443 const arch_register_t *spreg;
445 ir_node *val, *mem, *mem_proj;
446 ir_node *store = stores[i];
447 ir_node *noreg = ia32_new_NoReg_gp(cg);
449 if(store == NULL || is_Bad(store))
452 val = get_irn_n(store, n_ia32_unary_op);
453 mem = get_irn_n(store, n_ia32_mem);
454 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
456 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
458 sched_add_before(irn, push);
460 // create stackpointer proj
461 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
462 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
464 // create memory proj
465 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
467 // use the memproj now
468 exchange(store, mem_proj);
470 // we can remove the store now
476 be_set_IncSP_offset(irn, offset);
477 be_set_IncSP_pred(irn, curr_sp);
481 * Tries to optimize two following IncSP.
483 static void peephole_IncSP_IncSP(ir_node *node)
488 ir_node *pred = be_get_IncSP_pred(node);
491 if(!be_is_IncSP(pred))
494 if(get_irn_n_edges(pred) > 1)
497 pred_offs = be_get_IncSP_offset(pred);
498 curr_offs = be_get_IncSP_offset(node);
500 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
501 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
505 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
506 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
510 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
511 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
514 offs = curr_offs + pred_offs;
517 /* add pred offset to ours and remove pred IncSP */
518 be_set_IncSP_offset(node, offs);
520 predpred = be_get_IncSP_pred(pred);
521 be_peephole_before_exchange(pred, predpred);
523 /* rewire dependency edges */
524 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
525 be_set_IncSP_pred(node, predpred);
529 be_peephole_after_exchange(predpred);
533 * Find a free GP register if possible, else return NULL.
535 static const arch_register_t *get_free_gp_reg(void)
539 for(i = 0; i < N_ia32_gp_REGS; ++i) {
540 const arch_register_t *reg = &ia32_gp_regs[i];
541 if(arch_register_type_is(reg, ignore))
544 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
545 return &ia32_gp_regs[i];
552 * Creates a Pop instruction before the given schedule point.
554 * @param dbgi debug info
555 * @param irg the graph
556 * @param block the block
557 * @param stack the previous stack value
558 * @param schedpoint the new node is added before this node
559 * @param reg the register to pop
561 * @return the new stack value
563 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
564 ir_node *stack, ir_node *schedpoint,
565 const arch_register_t *reg)
567 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
573 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
575 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
576 arch_set_irn_register(arch_env, stack, esp);
577 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
578 arch_set_irn_register(arch_env, val, reg);
580 sched_add_before(schedpoint, pop);
583 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
584 sched_add_before(schedpoint, keep);
590 * Creates a Push instruction before the given schedule point.
592 * @param dbgi debug info
593 * @param irg the graph
594 * @param block the block
595 * @param stack the previous stack value
596 * @param schedpoint the new node is added before this node
597 * @param reg the register to pop
599 * @return the new stack value
601 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
602 ir_node *stack, ir_node *schedpoint,
603 const arch_register_t *reg)
605 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
606 ir_node *noreg, *nomem, *push, *val;
608 val = new_rd_ia32_ProduceVal(NULL, irg, block);
609 arch_set_irn_register(arch_env, val, reg);
610 sched_add_before(schedpoint, val);
612 noreg = ia32_new_NoReg_gp(cg);
613 nomem = get_irg_no_mem(irg);
614 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
615 sched_add_before(schedpoint, push);
617 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
618 arch_set_irn_register(arch_env, stack, esp);
624 * Optimize an IncSp by replacing it with push/pop
626 static void peephole_be_IncSP(ir_node *node)
628 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
629 const arch_register_t *reg;
630 ir_graph *irg = current_ir_graph;
636 /* first optimize incsp->incsp combinations */
637 peephole_IncSP_IncSP(node);
639 /* transform IncSP->Store combinations to Push where possible */
640 peephole_IncSP_Store_to_push(node);
642 if (arch_get_irn_register(arch_env, node) != esp)
645 /* replace IncSP -4 by Pop freereg when possible */
646 offset = be_get_IncSP_offset(node);
647 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
648 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
649 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
650 (offset != +8 || ia32_cg_config.use_sub_esp_8))
654 /* we need a free register for pop */
655 reg = get_free_gp_reg();
659 dbgi = get_irn_dbg_info(node);
660 block = get_nodes_block(node);
661 stack = be_get_IncSP_pred(node);
663 stack = create_pop(dbgi, irg, block, stack, node, reg);
666 stack = create_pop(dbgi, irg, block, stack, node, reg);
669 dbgi = get_irn_dbg_info(node);
670 block = get_nodes_block(node);
671 stack = be_get_IncSP_pred(node);
672 reg = &ia32_gp_regs[REG_EAX];
674 stack = create_push(dbgi, irg, block, stack, node, reg);
677 stack = create_push(dbgi, irg, block, stack, node, reg);
681 be_peephole_before_exchange(node, stack);
683 exchange(node, stack);
684 be_peephole_after_exchange(stack);
688 * Peephole optimisation for ia32_Const's
690 static void peephole_ia32_Const(ir_node *node)
692 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
693 const arch_register_t *reg;
694 ir_graph *irg = current_ir_graph;
701 /* try to transform a mov 0, reg to xor reg reg */
702 if (attr->offset != 0 || attr->symconst != NULL)
704 if (ia32_cg_config.use_mov_0)
706 /* xor destroys the flags, so no-one must be using them */
707 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
710 reg = arch_get_irn_register(arch_env, node);
711 assert(be_peephole_get_reg_value(reg) == NULL);
713 /* create xor(produceval, produceval) */
714 block = get_nodes_block(node);
715 dbgi = get_irn_dbg_info(node);
716 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
717 arch_set_irn_register(arch_env, produceval, reg);
719 noreg = ia32_new_NoReg_gp(cg);
720 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
721 produceval, produceval);
722 arch_set_irn_register(arch_env, xor, reg);
724 sched_add_before(node, produceval);
725 sched_add_before(node, xor);
727 be_peephole_before_exchange(node, xor);
730 be_peephole_after_exchange(xor);
733 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
735 return node == cg->noreg_gp;
738 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
740 ir_graph *irg = current_ir_graph;
741 ir_node *start_block = get_irg_start_block(irg);
742 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
744 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
749 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
752 ir_graph *irg = get_irn_irg(node);
753 ir_node *block = get_nodes_block(node);
754 int offset = get_ia32_am_offs_int(node);
755 int sc_sign = is_ia32_am_sc_sign(node);
756 ir_entity *entity = get_ia32_am_sc(node);
759 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
760 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
764 static int is_am_one(const ir_node *node)
766 int offset = get_ia32_am_offs_int(node);
767 ir_entity *entity = get_ia32_am_sc(node);
769 return offset == 1 && entity == NULL;
772 static int is_am_minus_one(const ir_node *node)
774 int offset = get_ia32_am_offs_int(node);
775 ir_entity *entity = get_ia32_am_sc(node);
777 return offset == -1 && entity == NULL;
781 * Transforms a LEA into an Add or SHL if possible.
783 static void peephole_ia32_Lea(ir_node *node)
785 const arch_env_t *arch_env = cg->arch_env;
786 ir_graph *irg = current_ir_graph;
789 const arch_register_t *base_reg;
790 const arch_register_t *index_reg;
791 const arch_register_t *out_reg;
802 assert(is_ia32_Lea(node));
804 /* we can only do this if are allowed to globber the flags */
805 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
808 base = get_irn_n(node, n_ia32_Lea_base);
809 index = get_irn_n(node, n_ia32_Lea_index);
811 if(is_noreg(cg, base)) {
815 base_reg = arch_get_irn_register(arch_env, base);
817 if(is_noreg(cg, index)) {
821 index_reg = arch_get_irn_register(arch_env, index);
824 if(base == NULL && index == NULL) {
825 /* we shouldn't construct these in the first place... */
827 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
832 out_reg = arch_get_irn_register(arch_env, node);
833 scale = get_ia32_am_scale(node);
834 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
835 /* check if we have immediates values (frame entities should already be
836 * expressed in the offsets) */
837 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
843 /* we can transform leas where the out register is the same as either the
844 * base or index register back to an Add or Shl */
845 if(out_reg == base_reg) {
848 if(!has_immediates) {
849 ir_fprintf(stderr, "Optimisation warning: found lea which is "
854 goto make_add_immediate;
856 if(scale == 0 && !has_immediates) {
861 /* can't create an add */
863 } else if(out_reg == index_reg) {
865 if(has_immediates && scale == 0) {
867 goto make_add_immediate;
868 } else if(!has_immediates && scale > 0) {
870 op2 = create_immediate_from_int(cg, scale);
872 } else if(!has_immediates) {
874 ir_fprintf(stderr, "Optimisation warning: found lea which is "
878 } else if(scale == 0 && !has_immediates) {
883 /* can't create an add */
886 /* can't create an add */
891 if(ia32_cg_config.use_incdec) {
892 if(is_am_one(node)) {
893 dbgi = get_irn_dbg_info(node);
894 block = get_nodes_block(node);
895 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
896 arch_set_irn_register(arch_env, res, out_reg);
899 if(is_am_minus_one(node)) {
900 dbgi = get_irn_dbg_info(node);
901 block = get_nodes_block(node);
902 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
903 arch_set_irn_register(arch_env, res, out_reg);
907 op2 = create_immediate_from_am(cg, node);
910 dbgi = get_irn_dbg_info(node);
911 block = get_nodes_block(node);
912 noreg = ia32_new_NoReg_gp(cg);
914 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
915 arch_set_irn_register(arch_env, res, out_reg);
916 set_ia32_commutative(res);
920 dbgi = get_irn_dbg_info(node);
921 block = get_nodes_block(node);
922 noreg = ia32_new_NoReg_gp(cg);
924 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
925 arch_set_irn_register(arch_env, res, out_reg);
929 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
931 /* add new ADD/SHL to schedule */
932 DBG_OPT_LEA2ADD(node, res);
934 /* exchange the Add and the LEA */
935 be_peephole_before_exchange(node, res);
936 sched_add_before(node, res);
939 be_peephole_after_exchange(res);
943 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
945 static void peephole_ia32_Imul_split(ir_node *imul) {
946 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
947 const arch_register_t *reg;
948 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
952 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
953 /* no memory, imm form ignore */
956 /* we need a free register */
957 reg = get_free_gp_reg();
961 /* fine, we can rebuild it */
962 dbgi = get_irn_dbg_info(imul);
963 block = get_nodes_block(imul);
964 irg = current_ir_graph;
965 base = get_irn_n(imul, n_ia32_IMul_base);
966 index = get_irn_n(imul, n_ia32_IMul_index);
967 mem = get_irn_n(imul, n_ia32_IMul_mem);
968 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
970 /* copy all attributes */
971 set_irn_pinned(load, get_irn_pinned(imul));
972 set_ia32_op_type(load, ia32_AddrModeS);
973 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
975 set_ia32_am_scale(load, get_ia32_am_scale(imul));
976 set_ia32_am_sc(load, get_ia32_am_sc(imul));
977 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
978 if (is_ia32_am_sc_sign(imul))
979 set_ia32_am_sc_sign(load);
980 if (is_ia32_use_frame(imul))
981 set_ia32_use_frame(load);
982 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
984 sched_add_before(imul, load);
986 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
987 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
989 arch_set_irn_register(arch_env, res, reg);
990 be_peephole_after_exchange(res);
992 set_irn_n(imul, n_ia32_IMul_mem, mem);
993 noreg = get_irn_n(imul, n_ia32_IMul_left);
994 set_irn_n(imul, n_ia32_IMul_left, res);
995 set_ia32_op_type(imul, ia32_Normal);
999 * Replace xorps r,r and xorpd r,r by pxor r,r
1001 static void peephole_ia32_xZero(ir_node *xor) {
1002 set_irn_op(xor, op_ia32_xPzero);
1006 * Register a peephole optimisation function.
1008 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1009 assert(op->ops.generic == NULL);
1010 op->ops.generic = (op_func)func;
1013 /* Perform peephole-optimizations. */
1014 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1017 arch_env = cg->arch_env;
1019 /* register peephole optimisations */
1020 clear_irp_opcodes_generic_func();
1021 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1022 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
1023 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1024 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1025 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1026 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1027 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1028 if (! ia32_cg_config.use_imul_mem_imm32)
1029 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1030 if (ia32_cg_config.use_pxor)
1031 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1033 be_peephole_opt(cg->birg);
1037 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1038 * all it's Projs are removed as well.
1039 * @param irn The irn to be removed from schedule
1041 static INLINE void try_kill(ir_node *node)
1043 if(get_irn_mode(node) == mode_T) {
1044 const ir_edge_t *edge, *next;
1045 foreach_out_edge_safe(node, edge, next) {
1046 ir_node *proj = get_edge_src_irn(edge);
1051 if(get_irn_n_edges(node) != 0)
1054 if (sched_is_scheduled(node)) {
1061 static void optimize_conv_store(ir_node *node)
1066 ir_mode *store_mode;
1068 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1071 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1072 pred_proj = get_irn_n(node, n_ia32_Store_val);
1073 if(is_Proj(pred_proj)) {
1074 pred = get_Proj_pred(pred_proj);
1078 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1080 if(get_ia32_op_type(pred) != ia32_Normal)
1083 /* the store only stores the lower bits, so we only need the conv
1084 * it it shrinks the mode */
1085 conv_mode = get_ia32_ls_mode(pred);
1086 store_mode = get_ia32_ls_mode(node);
1087 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1090 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1091 if(get_irn_n_edges(pred_proj) == 0) {
1092 be_kill_node(pred_proj);
1093 if(pred != pred_proj)
1098 static void optimize_load_conv(ir_node *node)
1100 ir_node *pred, *predpred;
1104 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1107 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1108 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1112 predpred = get_Proj_pred(pred);
1113 if(!is_ia32_Load(predpred))
1116 /* the load is sign extending the upper bits, so we only need the conv
1117 * if it shrinks the mode */
1118 load_mode = get_ia32_ls_mode(predpred);
1119 conv_mode = get_ia32_ls_mode(node);
1120 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1123 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1124 /* change the load if it has only 1 user */
1125 if(get_irn_n_edges(pred) == 1) {
1127 if(get_mode_sign(conv_mode)) {
1128 newmode = find_signed_mode(load_mode);
1130 newmode = find_unsigned_mode(load_mode);
1132 assert(newmode != NULL);
1133 set_ia32_ls_mode(predpred, newmode);
1135 /* otherwise we have to keep the conv */
1141 exchange(node, pred);
1144 static void optimize_conv_conv(ir_node *node)
1146 ir_node *pred_proj, *pred, *result_conv;
1147 ir_mode *pred_mode, *conv_mode;
1151 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1154 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1155 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1156 if(is_Proj(pred_proj))
1157 pred = get_Proj_pred(pred_proj);
1161 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1164 /* we know that after a conv, the upper bits are sign extended
1165 * so we only need the 2nd conv if it shrinks the mode */
1166 conv_mode = get_ia32_ls_mode(node);
1167 conv_mode_bits = get_mode_size_bits(conv_mode);
1168 pred_mode = get_ia32_ls_mode(pred);
1169 pred_mode_bits = get_mode_size_bits(pred_mode);
1171 if(conv_mode_bits == pred_mode_bits
1172 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1173 result_conv = pred_proj;
1174 } else if(conv_mode_bits <= pred_mode_bits) {
1175 /* if 2nd conv is smaller then first conv, then we can always take the
1177 if(get_irn_n_edges(pred_proj) == 1) {
1178 result_conv = pred_proj;
1179 set_ia32_ls_mode(pred, conv_mode);
1181 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1182 if (get_mode_size_bits(conv_mode) == 8) {
1183 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1184 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1187 /* we don't want to end up with 2 loads, so we better do nothing */
1188 if(get_irn_mode(pred) == mode_T) {
1192 result_conv = exact_copy(pred);
1193 set_ia32_ls_mode(result_conv, conv_mode);
1195 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1196 if (get_mode_size_bits(conv_mode) == 8) {
1197 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1198 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1202 /* if both convs have the same sign, then we can take the smaller one */
1203 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1204 result_conv = pred_proj;
1206 /* no optimisation possible if smaller conv is sign-extend */
1207 if(mode_is_signed(pred_mode)) {
1210 /* we can take the smaller conv if it is unsigned */
1211 result_conv = pred_proj;
1216 exchange(node, result_conv);
1218 if(get_irn_n_edges(pred_proj) == 0) {
1219 be_kill_node(pred_proj);
1220 if(pred != pred_proj)
1223 optimize_conv_conv(result_conv);
1226 static void optimize_node(ir_node *node, void *env)
1230 optimize_load_conv(node);
1231 optimize_conv_store(node);
1232 optimize_conv_conv(node);
1236 * Performs conv and address mode optimization.
1238 void ia32_optimize_graph(ia32_code_gen_t *cg)
1240 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1243 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1246 void ia32_init_optimize(void)
1248 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");