2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_common_transform.h"
55 #include "ia32_transform.h"
56 #include "ia32_dbg_stat.h"
57 #include "ia32_util.h"
58 #include "ia32_architecture.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static const arch_env_t *arch_env;
63 static ia32_code_gen_t *cg;
65 static void copy_mark(const ir_node *old, ir_node *new)
67 if (is_ia32_is_reload(old))
68 set_ia32_is_reload(new);
69 if (is_ia32_is_spill(old))
70 set_ia32_is_spill(new);
71 if (is_ia32_is_remat(old))
72 set_ia32_is_remat(new);
75 typedef enum produces_flag_t {
82 * Return which usable flag the given node produces
84 * @param node the node to check
85 * @param pn the projection number of the used result
87 static produces_flag_t produces_test_flag(ir_node *node, int pn)
90 const ia32_immediate_attr_t *imm_attr;
92 if (!is_ia32_irn(node))
93 return produces_no_flag;
95 switch (get_ia32_irn_opcode(node)) {
110 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
111 count = get_irn_n(node, n_ia32_ShlD_count);
112 goto check_shift_amount;
117 assert(n_ia32_Shl_count == n_ia32_Shr_count
118 && n_ia32_Shl_count == n_ia32_Sar_count);
119 count = get_irn_n(node, n_ia32_Shl_count);
121 /* when shift count is zero the flags are not affected, so we can only
122 * do this for constants != 0 */
123 if (!is_ia32_Immediate(count))
124 return produces_no_flag;
126 imm_attr = get_ia32_immediate_attr_const(count);
127 if (imm_attr->symconst != NULL)
128 return produces_no_flag;
129 if ((imm_attr->offset & 0x1f) == 0)
130 return produces_no_flag;
134 return pn == pn_ia32_Mul_res_high ?
135 produces_flag_carry : produces_no_flag;
138 return produces_no_flag;
141 return pn == pn_ia32_res ?
142 produces_flag_zero : produces_no_flag;
146 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
148 * @param node the node to change
150 * @return the new mode_T node (if the mode was changed) or node itself
152 static ir_node *turn_into_mode_t(ir_node *node)
157 const arch_register_t *reg;
159 if(get_irn_mode(node) == mode_T)
162 assert(get_irn_mode(node) == mode_Iu);
164 new_node = exact_copy(node);
165 set_irn_mode(new_node, mode_T);
167 block = get_nodes_block(new_node);
168 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
171 reg = arch_get_irn_register(arch_env, node);
172 arch_set_irn_register(arch_env, res_proj, reg);
174 sched_add_before(node, new_node);
175 be_peephole_exchange(node, res_proj);
180 * Replace Cmp(x, 0) by a Test(x, x)
182 static void peephole_ia32_Cmp(ir_node *const node)
185 ia32_immediate_attr_t const *imm;
192 ia32_attr_t const *attr;
196 arch_register_t const *reg;
197 ir_edge_t const *edge;
198 ir_edge_t const *tmp;
200 if (get_ia32_op_type(node) != ia32_Normal)
203 right = get_irn_n(node, n_ia32_Cmp_right);
204 if (!is_ia32_Immediate(right))
207 imm = get_ia32_immediate_attr_const(right);
208 if (imm->symconst != NULL || imm->offset != 0)
211 dbgi = get_irn_dbg_info(node);
212 irg = current_ir_graph;
213 block = get_nodes_block(node);
214 noreg = ia32_new_NoReg_gp(cg);
215 nomem = get_irg_no_mem(irg);
216 op = get_irn_n(node, n_ia32_Cmp_left);
217 attr = get_irn_generic_attr(node);
218 ins_permuted = attr->data.ins_permuted;
219 cmp_unsigned = attr->data.cmp_unsigned;
221 if (is_ia32_Cmp(node)) {
222 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
223 op, op, ins_permuted, cmp_unsigned);
225 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
226 op, op, ins_permuted, cmp_unsigned);
228 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
230 reg = arch_get_irn_register(arch_env, node);
231 arch_set_irn_register(arch_env, test, reg);
233 foreach_out_edge_safe(node, edge, tmp) {
234 ir_node *const user = get_edge_src_irn(edge);
237 exchange(user, test);
240 sched_add_before(node, test);
241 copy_mark(node, test);
242 be_peephole_exchange(node, test);
246 * Peephole optimization for Test instructions.
247 * We can remove the Test, if a zero flags was produced which is still
250 static void peephole_ia32_Test(ir_node *node)
252 ir_node *left = get_irn_n(node, n_ia32_Test_left);
253 ir_node *right = get_irn_n(node, n_ia32_Test_right);
257 int pn = pn_ia32_res;
259 const ir_edge_t *edge;
261 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
262 && n_ia32_Test_right == n_ia32_Test8Bit_right);
264 /* we need a test for 0 */
268 block = get_nodes_block(node);
269 if(get_nodes_block(left) != block)
273 pn = get_Proj_proj(left);
274 left = get_Proj_pred(left);
277 /* happens rarely, but if it does code will panic' */
278 if (is_ia32_Unknown_GP(left))
281 /* walk schedule up and abort when we find left or some other node destroys
285 schedpoint = sched_prev(schedpoint);
286 if (schedpoint == left)
288 if (arch_irn_is(arch_env, schedpoint, modify_flags))
290 if (schedpoint == block)
291 panic("couldn't find left");
294 /* make sure only Lg/Eq tests are used */
295 foreach_out_edge(node, edge) {
296 ir_node *user = get_edge_src_irn(edge);
297 int pnc = get_ia32_condcode(user);
299 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
304 switch (produces_test_flag(left, pn)) {
305 case produces_flag_zero:
308 case produces_flag_carry:
309 foreach_out_edge(node, edge) {
310 ir_node *user = get_edge_src_irn(edge);
311 int pnc = get_ia32_condcode(user);
314 case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
315 case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
316 default: panic("unexpected pn");
318 set_ia32_condcode(user, pnc);
326 left = turn_into_mode_t(left);
328 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
329 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
331 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
333 assert(get_irn_mode(node) != mode_T);
335 be_peephole_exchange(node, flags_proj);
339 * AMD Athlon works faster when RET is not destination of
340 * conditional jump or directly preceded by other jump instruction.
341 * Can be avoided by placing a Rep prefix before the return.
343 static void peephole_ia32_Return(ir_node *node) {
344 ir_node *block, *irn;
346 if (!ia32_cg_config.use_pad_return)
349 block = get_nodes_block(node);
351 /* check if this return is the first on the block */
352 sched_foreach_reverse_from(node, irn) {
353 switch (get_irn_opcode(irn)) {
355 /* the return node itself, ignore */
360 /* ignore no code generated */
363 /* arg, IncSP 0 nodes might occur, ignore these */
364 if (be_get_IncSP_offset(irn) == 0)
374 /* ensure, that the 3 byte return is generated */
375 be_Return_set_emit_pop(node, 1);
378 /* only optimize up to 48 stores behind IncSPs */
379 #define MAXPUSH_OPTIMIZE 48
382 * Tries to create Push's from IncSP, Store combinations.
383 * The Stores are replaced by Push's, the IncSP is modified
384 * (possibly into IncSP 0, but not removed).
386 static void peephole_IncSP_Store_to_push(ir_node *irn)
392 ir_node *stores[MAXPUSH_OPTIMIZE];
397 ir_node *first_push = NULL;
398 ir_edge_t const *edge;
399 ir_edge_t const *next;
401 memset(stores, 0, sizeof(stores));
403 assert(be_is_IncSP(irn));
405 inc_ofs = be_get_IncSP_offset(irn);
410 * We first walk the schedule after the IncSP node as long as we find
411 * suitable Stores that could be transformed to a Push.
412 * We save them into the stores array which is sorted by the frame offset/4
413 * attached to the node
416 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
421 /* it has to be a Store */
422 if (!is_ia32_Store(node))
425 /* it has to use our sp value */
426 if (get_irn_n(node, n_ia32_base) != irn)
428 /* Store has to be attached to NoMem */
429 mem = get_irn_n(node, n_ia32_mem);
433 /* unfortunately we can't support the full AMs possible for push at the
434 * moment. TODO: fix this */
435 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
438 offset = get_ia32_am_offs_int(node);
439 /* we should NEVER access uninitialized stack BELOW the current SP */
442 /* storing at half-slots is bad */
443 if ((offset & 3) != 0)
446 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
448 storeslot = offset >> 2;
450 /* storing into the same slot twice is bad (and shouldn't happen...) */
451 if (stores[storeslot] != NULL)
454 stores[storeslot] = node;
455 if (storeslot > maxslot)
461 for (i = -1; i < maxslot; ++i) {
462 if (stores[i + 1] == NULL)
466 /* walk through the Stores and create Pushs for them */
467 block = get_nodes_block(irn);
468 spmode = get_irn_mode(irn);
470 for (; i >= 0; --i) {
471 const arch_register_t *spreg;
473 ir_node *val, *mem, *mem_proj;
474 ir_node *store = stores[i];
475 ir_node *noreg = ia32_new_NoReg_gp(cg);
477 val = get_irn_n(store, n_ia32_unary_op);
478 mem = get_irn_n(store, n_ia32_mem);
479 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
481 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
482 copy_mark(store, push);
484 if (first_push == NULL)
487 sched_add_after(curr_sp, push);
489 /* create stackpointer Proj */
490 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
491 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
493 /* create memory Proj */
494 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
496 /* use the memproj now */
497 be_peephole_exchange(store, mem_proj);
502 foreach_out_edge_safe(irn, edge, next) {
503 ir_node *const src = get_edge_src_irn(edge);
504 int const pos = get_edge_src_pos(edge);
506 if (src == first_push)
509 set_irn_n(src, pos, curr_sp);
512 be_set_IncSP_offset(irn, inc_ofs);
516 static void peephole_store_incsp(ir_node *store)
525 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
526 if (!be_is_IncSP(am_base)
527 || get_nodes_block(am_base) != get_nodes_block(store))
529 mem = get_irn_n(store, n_ia32_Store_mem);
530 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
534 int incsp_offset = be_get_IncSP_offset(am_base);
535 if (incsp_offset <= 0)
538 /* we have to be at offset 0 */
539 int my_offset = get_ia32_am_offs_int(store);
540 if (my_offset != 0) {
541 /* TODO here: find out wether there is a store with offset 0 before
542 * us and wether we can move it down to our place */
545 ir_mode *ls_mode = get_ia32_ls_mode(store);
546 int my_store_size = get_mode_size_bytes(ls_mode);
548 if (my_offset + my_store_size > incsp_offset)
551 /* correctness checking:
552 - noone else must write to that stackslot
553 (because after translation incsp won't allocate it anymore)
555 sched_foreach_reverse_from(store, node) {
561 /* make sure noone else can use the space on the stack */
562 arity = get_irn_arity(node);
563 for (i = 0; i < arity; ++i) {
564 ir_node *pred = get_irn_n(node, i);
568 if (i == n_ia32_base &&
569 (get_ia32_op_type(node) == ia32_AddrModeS
570 || get_ia32_op_type(node) == ia32_AddrModeD)) {
571 int node_offset = get_ia32_am_offs_int(node);
572 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
573 int node_size = get_mode_size_bytes(node);
574 /* overlapping with our position? abort */
575 if (node_offset < my_offset + my_store_size
576 && node_offset + node_size >= my_offset)
578 /* otherwise it's fine */
582 /* strange use of esp: abort */
587 /* all ok, change to push */
588 dbgi = get_irn_dbg_info(store);
589 block = get_nodes_block(store);
590 noreg = ia32_new_NoReg_gp(cg);
593 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem,
595 create_push(dbgi, current_ir_graph, block, am_base, store);
600 * Return true if a mode can be stored in the GP register set
602 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
603 if (mode == mode_fpcw)
605 if (get_mode_size_bits(mode) > 32)
607 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
611 * Tries to create Pops from Load, IncSP combinations.
612 * The Loads are replaced by Pops, the IncSP is modified
613 * (possibly into IncSP 0, but not removed).
615 static void peephole_Load_IncSP_to_pop(ir_node *irn)
617 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
618 int i, maxslot, inc_ofs, ofs;
619 ir_node *node, *pred_sp, *block;
620 ir_node *loads[MAXPUSH_OPTIMIZE];
622 unsigned regmask = 0;
623 unsigned copymask = ~0;
625 memset(loads, 0, sizeof(loads));
626 assert(be_is_IncSP(irn));
628 inc_ofs = -be_get_IncSP_offset(irn);
633 * We first walk the schedule before the IncSP node as long as we find
634 * suitable Loads that could be transformed to a Pop.
635 * We save them into the stores array which is sorted by the frame offset/4
636 * attached to the node
639 pred_sp = be_get_IncSP_pred(irn);
640 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
643 const arch_register_t *sreg, *dreg;
645 /* it has to be a Load */
646 if (!is_ia32_Load(node)) {
647 if (be_is_Copy(node)) {
648 if (!mode_needs_gp_reg(get_irn_mode(node))) {
649 /* not a GP copy, ignore */
652 dreg = arch_get_irn_register(arch_env, node);
653 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
654 if (regmask & copymask & (1 << sreg->index)) {
657 if (regmask & copymask & (1 << dreg->index)) {
660 /* we CAN skip Copies if neither the destination nor the source
661 * is not in our regmask, ie none of our future Pop will overwrite it */
662 regmask |= (1 << dreg->index) | (1 << sreg->index);
663 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
669 /* we can handle only GP loads */
670 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
673 /* it has to use our predecessor sp value */
674 if (get_irn_n(node, n_ia32_base) != pred_sp) {
675 /* it would be ok if this load does not use a Pop result,
676 * but we do not check this */
680 /* should have NO index */
681 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
684 offset = get_ia32_am_offs_int(node);
685 /* we should NEVER access uninitialized stack BELOW the current SP */
688 /* storing at half-slots is bad */
689 if ((offset & 3) != 0)
692 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
694 /* ignore those outside the possible windows */
695 if (offset > inc_ofs - 4)
697 loadslot = offset >> 2;
699 /* loading from the same slot twice is bad (and shouldn't happen...) */
700 if (loads[loadslot] != NULL)
703 dreg = arch_get_irn_register(arch_env, node);
704 if (regmask & (1 << dreg->index)) {
705 /* this register is already used */
708 regmask |= 1 << dreg->index;
710 loads[loadslot] = node;
711 if (loadslot > maxslot)
718 /* find the first slot */
719 for (i = maxslot; i >= 0; --i) {
720 ir_node *load = loads[i];
726 ofs = inc_ofs - (maxslot + 1) * 4;
729 /* create a new IncSP if needed */
730 block = get_nodes_block(irn);
733 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
734 sched_add_before(irn, pred_sp);
737 /* walk through the Loads and create Pops for them */
738 for (++i; i <= maxslot; ++i) {
739 ir_node *load = loads[i];
741 const ir_edge_t *edge, *tmp;
742 const arch_register_t *reg;
744 mem = get_irn_n(load, n_ia32_mem);
745 reg = arch_get_irn_register(arch_env, load);
747 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
748 arch_set_irn_register(arch_env, pop, reg);
750 copy_mark(load, pop);
752 /* create stackpointer Proj */
753 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
754 arch_set_irn_register(arch_env, pred_sp, esp);
756 sched_add_before(irn, pop);
759 foreach_out_edge_safe(load, edge, tmp) {
760 ir_node *proj = get_edge_src_irn(edge);
762 set_Proj_pred(proj, pop);
765 /* we can remove the Load now */
770 be_set_IncSP_offset(irn, -ofs);
771 be_set_IncSP_pred(irn, pred_sp);
776 * Find a free GP register if possible, else return NULL.
778 static const arch_register_t *get_free_gp_reg(void)
782 for(i = 0; i < N_ia32_gp_REGS; ++i) {
783 const arch_register_t *reg = &ia32_gp_regs[i];
784 if(arch_register_type_is(reg, ignore))
787 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
788 return &ia32_gp_regs[i];
795 * Creates a Pop instruction before the given schedule point.
797 * @param dbgi debug info
798 * @param irg the graph
799 * @param block the block
800 * @param stack the previous stack value
801 * @param schedpoint the new node is added before this node
802 * @param reg the register to pop
804 * @return the new stack value
806 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
807 ir_node *stack, ir_node *schedpoint,
808 const arch_register_t *reg)
810 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
816 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
818 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
819 arch_set_irn_register(arch_env, stack, esp);
820 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
821 arch_set_irn_register(arch_env, val, reg);
823 sched_add_before(schedpoint, pop);
826 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
827 sched_add_before(schedpoint, keep);
833 * Creates a Push instruction before the given schedule point.
835 * @param dbgi debug info
836 * @param irg the graph
837 * @param block the block
838 * @param stack the previous stack value
839 * @param schedpoint the new node is added before this node
840 * @param reg the register to pop
842 * @return the new stack value
844 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
845 ir_node *stack, ir_node *schedpoint)
847 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
849 ir_node *val = ia32_new_Unknown_gp(cg);
850 ir_node *noreg = ia32_new_NoReg_gp(cg);
851 ir_node *nomem = get_irg_no_mem(irg);
852 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
853 sched_add_before(schedpoint, push);
855 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
856 arch_set_irn_register(arch_env, stack, esp);
862 * Optimize an IncSp by replacing it with Push/Pop.
864 static void peephole_be_IncSP(ir_node *node)
866 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
867 const arch_register_t *reg;
868 ir_graph *irg = current_ir_graph;
874 /* first optimize incsp->incsp combinations */
875 node = be_peephole_IncSP_IncSP(node);
877 /* transform IncSP->Store combinations to Push where possible */
878 peephole_IncSP_Store_to_push(node);
880 /* transform Load->IncSP combinations to Pop where possible */
881 peephole_Load_IncSP_to_pop(node);
883 if (arch_get_irn_register(arch_env, node) != esp)
886 /* replace IncSP -4 by Pop freereg when possible */
887 offset = be_get_IncSP_offset(node);
888 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
889 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
890 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
891 (offset != +8 || ia32_cg_config.use_sub_esp_8))
895 /* we need a free register for pop */
896 reg = get_free_gp_reg();
900 dbgi = get_irn_dbg_info(node);
901 block = get_nodes_block(node);
902 stack = be_get_IncSP_pred(node);
904 stack = create_pop(dbgi, irg, block, stack, node, reg);
907 stack = create_pop(dbgi, irg, block, stack, node, reg);
910 dbgi = get_irn_dbg_info(node);
911 block = get_nodes_block(node);
912 stack = be_get_IncSP_pred(node);
913 stack = create_push(dbgi, irg, block, stack, node);
916 stack = create_push(dbgi, irg, block, stack, node);
920 be_peephole_exchange(node, stack);
924 * Peephole optimisation for ia32_Const's
926 static void peephole_ia32_Const(ir_node *node)
928 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
929 const arch_register_t *reg;
930 ir_graph *irg = current_ir_graph;
937 /* try to transform a mov 0, reg to xor reg reg */
938 if (attr->offset != 0 || attr->symconst != NULL)
940 if (ia32_cg_config.use_mov_0)
942 /* xor destroys the flags, so no-one must be using them */
943 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
946 reg = arch_get_irn_register(arch_env, node);
947 assert(be_peephole_get_reg_value(reg) == NULL);
949 /* create xor(produceval, produceval) */
950 block = get_nodes_block(node);
951 dbgi = get_irn_dbg_info(node);
952 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
953 arch_set_irn_register(arch_env, produceval, reg);
955 noreg = ia32_new_NoReg_gp(cg);
956 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
957 produceval, produceval);
958 arch_set_irn_register(arch_env, xor, reg);
960 sched_add_before(node, produceval);
961 sched_add_before(node, xor);
963 copy_mark(node, xor);
964 be_peephole_exchange(node, xor);
967 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
969 return node == cg->noreg_gp;
972 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
974 ir_graph *irg = current_ir_graph;
975 ir_node *start_block = get_irg_start_block(irg);
976 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
978 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
983 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
986 ir_graph *irg = get_irn_irg(node);
987 ir_node *block = get_nodes_block(node);
988 int offset = get_ia32_am_offs_int(node);
989 int sc_sign = is_ia32_am_sc_sign(node);
990 ir_entity *entity = get_ia32_am_sc(node);
993 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
994 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
998 static int is_am_one(const ir_node *node)
1000 int offset = get_ia32_am_offs_int(node);
1001 ir_entity *entity = get_ia32_am_sc(node);
1003 return offset == 1 && entity == NULL;
1006 static int is_am_minus_one(const ir_node *node)
1008 int offset = get_ia32_am_offs_int(node);
1009 ir_entity *entity = get_ia32_am_sc(node);
1011 return offset == -1 && entity == NULL;
1015 * Transforms a LEA into an Add or SHL if possible.
1017 static void peephole_ia32_Lea(ir_node *node)
1019 const arch_env_t *arch_env = cg->arch_env;
1020 ir_graph *irg = current_ir_graph;
1023 const arch_register_t *base_reg;
1024 const arch_register_t *index_reg;
1025 const arch_register_t *out_reg;
1036 assert(is_ia32_Lea(node));
1038 /* we can only do this if are allowed to globber the flags */
1039 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1042 base = get_irn_n(node, n_ia32_Lea_base);
1043 index = get_irn_n(node, n_ia32_Lea_index);
1045 if(is_noreg(cg, base)) {
1049 base_reg = arch_get_irn_register(arch_env, base);
1051 if(is_noreg(cg, index)) {
1055 index_reg = arch_get_irn_register(arch_env, index);
1058 if(base == NULL && index == NULL) {
1059 /* we shouldn't construct these in the first place... */
1060 #ifdef DEBUG_libfirm
1061 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1066 out_reg = arch_get_irn_register(arch_env, node);
1067 scale = get_ia32_am_scale(node);
1068 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1069 /* check if we have immediates values (frame entities should already be
1070 * expressed in the offsets) */
1071 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1077 /* we can transform leas where the out register is the same as either the
1078 * base or index register back to an Add or Shl */
1079 if(out_reg == base_reg) {
1081 #ifdef DEBUG_libfirm
1082 if(!has_immediates) {
1083 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1088 goto make_add_immediate;
1090 if(scale == 0 && !has_immediates) {
1095 /* can't create an add */
1097 } else if(out_reg == index_reg) {
1099 if(has_immediates && scale == 0) {
1101 goto make_add_immediate;
1102 } else if(!has_immediates && scale > 0) {
1104 op2 = create_immediate_from_int(cg, scale);
1106 } else if(!has_immediates) {
1107 #ifdef DEBUG_libfirm
1108 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1112 } else if(scale == 0 && !has_immediates) {
1117 /* can't create an add */
1120 /* can't create an add */
1125 if(ia32_cg_config.use_incdec) {
1126 if(is_am_one(node)) {
1127 dbgi = get_irn_dbg_info(node);
1128 block = get_nodes_block(node);
1129 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
1130 arch_set_irn_register(arch_env, res, out_reg);
1133 if(is_am_minus_one(node)) {
1134 dbgi = get_irn_dbg_info(node);
1135 block = get_nodes_block(node);
1136 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
1137 arch_set_irn_register(arch_env, res, out_reg);
1141 op2 = create_immediate_from_am(cg, node);
1144 dbgi = get_irn_dbg_info(node);
1145 block = get_nodes_block(node);
1146 noreg = ia32_new_NoReg_gp(cg);
1147 nomem = new_NoMem();
1148 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1149 arch_set_irn_register(arch_env, res, out_reg);
1150 set_ia32_commutative(res);
1154 dbgi = get_irn_dbg_info(node);
1155 block = get_nodes_block(node);
1156 noreg = ia32_new_NoReg_gp(cg);
1157 nomem = new_NoMem();
1158 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1159 arch_set_irn_register(arch_env, res, out_reg);
1163 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1165 /* add new ADD/SHL to schedule */
1166 DBG_OPT_LEA2ADD(node, res);
1168 /* exchange the Add and the LEA */
1169 sched_add_before(node, res);
1170 copy_mark(node, res);
1171 be_peephole_exchange(node, res);
1175 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1177 static void peephole_ia32_Imul_split(ir_node *imul)
1179 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1180 const arch_register_t *reg;
1183 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1184 /* no memory, imm form ignore */
1187 /* we need a free register */
1188 reg = get_free_gp_reg();
1192 /* fine, we can rebuild it */
1193 res = turn_back_am(imul);
1194 arch_set_irn_register(arch_env, res, reg);
1198 * Replace xorps r,r and xorpd r,r by pxor r,r
1200 static void peephole_ia32_xZero(ir_node *xor) {
1201 set_irn_op(xor, op_ia32_xPzero);
1205 * Register a peephole optimisation function.
1207 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1208 assert(op->ops.generic == NULL);
1209 op->ops.generic = (op_func)func;
1212 /* Perform peephole-optimizations. */
1213 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1216 arch_env = cg->arch_env;
1218 /* register peephole optimisations */
1219 clear_irp_opcodes_generic_func();
1220 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1221 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1222 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1223 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1224 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1225 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1226 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1227 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1228 if (! ia32_cg_config.use_imul_mem_imm32)
1229 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1230 if (ia32_cg_config.use_pxor)
1231 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1233 be_peephole_opt(cg->birg);
1237 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1238 * all it's Projs are removed as well.
1239 * @param irn The irn to be removed from schedule
1241 static INLINE void try_kill(ir_node *node)
1243 if(get_irn_mode(node) == mode_T) {
1244 const ir_edge_t *edge, *next;
1245 foreach_out_edge_safe(node, edge, next) {
1246 ir_node *proj = get_edge_src_irn(edge);
1251 if(get_irn_n_edges(node) != 0)
1254 if (sched_is_scheduled(node)) {
1261 static void optimize_conv_store(ir_node *node)
1266 ir_mode *store_mode;
1268 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1271 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1272 pred_proj = get_irn_n(node, n_ia32_Store_val);
1273 if(is_Proj(pred_proj)) {
1274 pred = get_Proj_pred(pred_proj);
1278 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1280 if(get_ia32_op_type(pred) != ia32_Normal)
1283 /* the store only stores the lower bits, so we only need the conv
1284 * it it shrinks the mode */
1285 conv_mode = get_ia32_ls_mode(pred);
1286 store_mode = get_ia32_ls_mode(node);
1287 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1290 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1291 if(get_irn_n_edges(pred_proj) == 0) {
1292 kill_node(pred_proj);
1293 if(pred != pred_proj)
1298 static void optimize_load_conv(ir_node *node)
1300 ir_node *pred, *predpred;
1304 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1307 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1308 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1312 predpred = get_Proj_pred(pred);
1313 if(!is_ia32_Load(predpred))
1316 /* the load is sign extending the upper bits, so we only need the conv
1317 * if it shrinks the mode */
1318 load_mode = get_ia32_ls_mode(predpred);
1319 conv_mode = get_ia32_ls_mode(node);
1320 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1323 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1324 /* change the load if it has only 1 user */
1325 if(get_irn_n_edges(pred) == 1) {
1327 if(get_mode_sign(conv_mode)) {
1328 newmode = find_signed_mode(load_mode);
1330 newmode = find_unsigned_mode(load_mode);
1332 assert(newmode != NULL);
1333 set_ia32_ls_mode(predpred, newmode);
1335 /* otherwise we have to keep the conv */
1341 exchange(node, pred);
1344 static void optimize_conv_conv(ir_node *node)
1346 ir_node *pred_proj, *pred, *result_conv;
1347 ir_mode *pred_mode, *conv_mode;
1351 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1354 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1355 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1356 if(is_Proj(pred_proj))
1357 pred = get_Proj_pred(pred_proj);
1361 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1364 /* we know that after a conv, the upper bits are sign extended
1365 * so we only need the 2nd conv if it shrinks the mode */
1366 conv_mode = get_ia32_ls_mode(node);
1367 conv_mode_bits = get_mode_size_bits(conv_mode);
1368 pred_mode = get_ia32_ls_mode(pred);
1369 pred_mode_bits = get_mode_size_bits(pred_mode);
1371 if(conv_mode_bits == pred_mode_bits
1372 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1373 result_conv = pred_proj;
1374 } else if(conv_mode_bits <= pred_mode_bits) {
1375 /* if 2nd conv is smaller then first conv, then we can always take the
1377 if(get_irn_n_edges(pred_proj) == 1) {
1378 result_conv = pred_proj;
1379 set_ia32_ls_mode(pred, conv_mode);
1381 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1382 if (get_mode_size_bits(conv_mode) == 8) {
1383 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1384 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1387 /* we don't want to end up with 2 loads, so we better do nothing */
1388 if(get_irn_mode(pred) == mode_T) {
1392 result_conv = exact_copy(pred);
1393 set_ia32_ls_mode(result_conv, conv_mode);
1395 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1396 if (get_mode_size_bits(conv_mode) == 8) {
1397 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1398 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1402 /* if both convs have the same sign, then we can take the smaller one */
1403 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1404 result_conv = pred_proj;
1406 /* no optimisation possible if smaller conv is sign-extend */
1407 if(mode_is_signed(pred_mode)) {
1410 /* we can take the smaller conv if it is unsigned */
1411 result_conv = pred_proj;
1416 exchange(node, result_conv);
1418 if(get_irn_n_edges(pred_proj) == 0) {
1419 kill_node(pred_proj);
1420 if(pred != pred_proj)
1423 optimize_conv_conv(result_conv);
1426 static void optimize_node(ir_node *node, void *env)
1430 optimize_load_conv(node);
1431 optimize_conv_store(node);
1432 optimize_conv_conv(node);
1436 * Performs conv and address mode optimization.
1438 void ia32_optimize_graph(ia32_code_gen_t *cg)
1440 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1443 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1446 void ia32_init_optimize(void)
1448 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");