2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_common_transform.h"
55 #include "ia32_transform.h"
56 #include "ia32_dbg_stat.h"
57 #include "ia32_util.h"
58 #include "ia32_architecture.h"
60 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
62 static const arch_env_t *arch_env;
63 static ia32_code_gen_t *cg;
66 * Returns non-zero if the given node produces
69 * @param node the node to check
70 * @param pn if >= 0, the projection number of the used result
72 static int produces_zero_flag(ir_node *node, int pn)
75 const ia32_immediate_attr_t *imm_attr;
77 if (!is_ia32_irn(node))
81 if (pn != pn_ia32_res)
85 switch (get_ia32_irn_opcode(node)) {
103 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
104 assert(n_ia32_Shl_count == n_ia32_Shr_count
105 && n_ia32_Shl_count == n_ia32_Sar_count);
106 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
107 count = get_irn_n(node, n_ia32_ShlD_count);
109 count = get_irn_n(node, n_ia32_Shl_count);
111 /* when shift count is zero the flags are not affected, so we can only
112 * do this for constants != 0 */
113 if (!is_ia32_Immediate(count))
116 imm_attr = get_ia32_immediate_attr_const(count);
117 if (imm_attr->symconst != NULL)
119 if ((imm_attr->offset & 0x1f) == 0)
130 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
132 * @param node the node to change
134 * @return the new mode_T node (if the mode was changed) or node itself
136 static ir_node *turn_into_mode_t(ir_node *node)
141 const arch_register_t *reg;
143 if(get_irn_mode(node) == mode_T)
146 assert(get_irn_mode(node) == mode_Iu);
148 new_node = exact_copy(node);
149 set_irn_mode(new_node, mode_T);
151 block = get_nodes_block(new_node);
152 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
155 reg = arch_get_irn_register(arch_env, node);
156 arch_set_irn_register(arch_env, res_proj, reg);
158 sched_add_before(node, new_node);
159 be_peephole_exchange(node, res_proj);
164 * Replace Cmp(x, 0) by a Test(x, x)
166 static void peephole_ia32_Cmp(ir_node *const node)
169 ia32_immediate_attr_t const *imm;
176 ia32_attr_t const *attr;
180 arch_register_t const *reg;
181 ir_edge_t const *edge;
182 ir_edge_t const *tmp;
184 if (get_ia32_op_type(node) != ia32_Normal)
187 right = get_irn_n(node, n_ia32_Cmp_right);
188 if (!is_ia32_Immediate(right))
191 imm = get_ia32_immediate_attr_const(right);
192 if (imm->symconst != NULL || imm->offset != 0)
195 dbgi = get_irn_dbg_info(node);
196 irg = current_ir_graph;
197 block = get_nodes_block(node);
198 noreg = ia32_new_NoReg_gp(cg);
199 nomem = get_irg_no_mem(irg);
200 op = get_irn_n(node, n_ia32_Cmp_left);
201 attr = get_irn_generic_attr(node);
202 ins_permuted = attr->data.ins_permuted;
203 cmp_unsigned = attr->data.cmp_unsigned;
205 if (is_ia32_Cmp(node)) {
206 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
207 op, op, ins_permuted, cmp_unsigned);
209 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
210 op, op, ins_permuted, cmp_unsigned);
212 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
214 reg = arch_get_irn_register(arch_env, node);
215 arch_set_irn_register(arch_env, test, reg);
217 foreach_out_edge_safe(node, edge, tmp) {
218 ir_node *const user = get_edge_src_irn(edge);
221 exchange(user, test);
224 sched_add_before(node, test);
225 be_peephole_exchange(node, test);
229 * Peephole optimization for Test instructions.
230 * We can remove the Test, if a zero flags was produced which is still
233 static void peephole_ia32_Test(ir_node *node)
235 ir_node *left = get_irn_n(node, n_ia32_Test_left);
236 ir_node *right = get_irn_n(node, n_ia32_Test_right);
242 const ir_edge_t *edge;
244 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
245 && n_ia32_Test_right == n_ia32_Test8Bit_right);
247 /* we need a test for 0 */
251 block = get_nodes_block(node);
252 if(get_nodes_block(left) != block)
256 pn = get_Proj_proj(left);
257 left = get_Proj_pred(left);
260 /* happens rarely, but if it does code will panic' */
261 if (is_ia32_Unknown_GP(left))
264 /* walk schedule up and abort when we find left or some other node destroys
266 schedpoint = sched_prev(node);
267 while(schedpoint != left) {
268 schedpoint = sched_prev(schedpoint);
269 if(arch_irn_is(arch_env, schedpoint, modify_flags))
271 if(schedpoint == block)
272 panic("couldn't find left");
275 /* make sure only Lg/Eq tests are used */
276 foreach_out_edge(node, edge) {
277 ir_node *user = get_edge_src_irn(edge);
278 int pnc = get_ia32_condcode(user);
280 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
285 if(!produces_zero_flag(left, pn))
288 left = turn_into_mode_t(left);
290 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
291 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
293 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
295 assert(get_irn_mode(node) != mode_T);
297 be_peephole_exchange(node, flags_proj);
301 * AMD Athlon works faster when RET is not destination of
302 * conditional jump or directly preceded by other jump instruction.
303 * Can be avoided by placing a Rep prefix before the return.
305 static void peephole_ia32_Return(ir_node *node) {
306 ir_node *block, *irn;
308 if (!ia32_cg_config.use_pad_return)
311 block = get_nodes_block(node);
313 /* check if this return is the first on the block */
314 sched_foreach_reverse_from(node, irn) {
315 switch (get_irn_opcode(irn)) {
317 /* the return node itself, ignore */
320 /* ignore the barrier, no code generated */
323 /* arg, IncSP 0 nodes might occur, ignore these */
324 if (be_get_IncSP_offset(irn) == 0)
334 /* ensure, that the 3 byte return is generated
335 * actually the emitter tests again if the block beginning has a label and
336 * isn't just a fallthrough */
337 be_Return_set_emit_pop(node, 1);
340 /* only optimize up to 48 stores behind IncSPs */
341 #define MAXPUSH_OPTIMIZE 48
344 * Tries to create Push's from IncSP, Store combinations.
345 * The Stores are replaced by Push's, the IncSP is modified
346 * (possibly into IncSP 0, but not removed).
348 static void peephole_IncSP_Store_to_push(ir_node *irn)
350 int i, maxslot, inc_ofs;
352 ir_node *stores[MAXPUSH_OPTIMIZE];
358 memset(stores, 0, sizeof(stores));
360 assert(be_is_IncSP(irn));
362 inc_ofs = be_get_IncSP_offset(irn);
367 * We first walk the schedule after the IncSP node as long as we find
368 * suitable Stores that could be transformed to a Push.
369 * We save them into the stores array which is sorted by the frame offset/4
370 * attached to the node
373 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
378 /* it has to be a Store */
379 if (!is_ia32_Store(node))
382 /* it has to use our sp value */
383 if (get_irn_n(node, n_ia32_base) != irn)
385 /* Store has to be attached to NoMem */
386 mem = get_irn_n(node, n_ia32_mem);
390 /* unfortunately we can't support the full AMs possible for push at the
391 * moment. TODO: fix this */
392 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
395 offset = get_ia32_am_offs_int(node);
396 /* we should NEVER access uninitialized stack BELOW the current SP */
399 offset = inc_ofs - 4 - offset;
401 /* storing at half-slots is bad */
402 if ((offset & 3) != 0)
405 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
407 storeslot = offset >> 2;
409 /* storing into the same slot twice is bad (and shouldn't happen...) */
410 if (stores[storeslot] != NULL)
413 stores[storeslot] = node;
414 if (storeslot > maxslot)
418 curr_sp = be_get_IncSP_pred(irn);
420 /* walk through the Stores and create Pushs for them */
421 block = get_nodes_block(irn);
422 spmode = get_irn_mode(irn);
424 for (i = 0; i <= maxslot; ++i) {
425 const arch_register_t *spreg;
427 ir_node *val, *mem, *mem_proj;
428 ir_node *store = stores[i];
429 ir_node *noreg = ia32_new_NoReg_gp(cg);
434 val = get_irn_n(store, n_ia32_unary_op);
435 mem = get_irn_n(store, n_ia32_mem);
436 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
438 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
440 sched_add_before(irn, push);
442 /* create stackpointer Proj */
443 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
444 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
446 /* create memory Proj */
447 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
449 /* use the memproj now */
450 be_peephole_exchange(store, mem_proj);
455 be_set_IncSP_offset(irn, inc_ofs);
456 be_set_IncSP_pred(irn, curr_sp);
460 * Return true if a mode can be stored in the GP register set
462 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
463 if (mode == mode_fpcw)
465 if (get_mode_size_bits(mode) > 32)
467 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
471 * Tries to create Pops from Load, IncSP combinations.
472 * The Loads are replaced by Pops, the IncSP is modified
473 * (possibly into IncSP 0, but not removed).
475 static void peephole_Load_IncSP_to_pop(ir_node *irn)
477 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
478 int i, maxslot, inc_ofs, ofs;
479 ir_node *node, *pred_sp, *block;
480 ir_node *loads[MAXPUSH_OPTIMIZE];
482 unsigned regmask = 0;
483 unsigned copymask = ~0;
485 memset(loads, 0, sizeof(loads));
486 assert(be_is_IncSP(irn));
488 inc_ofs = -be_get_IncSP_offset(irn);
493 * We first walk the schedule before the IncSP node as long as we find
494 * suitable Loads that could be transformed to a Pop.
495 * We save them into the stores array which is sorted by the frame offset/4
496 * attached to the node
499 pred_sp = be_get_IncSP_pred(irn);
500 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
504 const arch_register_t *sreg, *dreg;
506 /* it has to be a Load */
507 if (!is_ia32_Load(node)) {
508 if (be_is_Copy(node)) {
509 if (!mode_needs_gp_reg(get_irn_mode(node))) {
510 /* not a GP copy, ignore */
513 dreg = arch_get_irn_register(arch_env, node);
514 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
515 if (regmask & copymask & (1 << sreg->index)) {
518 if (regmask & copymask & (1 << dreg->index)) {
521 /* we CAN skip Copies if neither the destination nor the source
522 * is not in our regmask, ie none of our future Pop will overwrite it */
523 regmask |= (1 << dreg->index) | (1 << sreg->index);
524 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
530 /* we can handle only GP loads */
531 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
534 /* it has to use our predecessor sp value */
535 if (get_irn_n(node, n_ia32_base) != pred_sp) {
536 /* it would be ok if this load does not use a Pop result,
537 * but we do not check this */
540 /* Load has to be attached to Spill-Mem */
541 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
542 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
545 /* should have NO index */
546 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
549 offset = get_ia32_am_offs_int(node);
550 /* we should NEVER access uninitialized stack BELOW the current SP */
553 /* storing at half-slots is bad */
554 if ((offset & 3) != 0)
557 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
559 /* ignore those outside the possible windows */
560 if (offset > inc_ofs - 4)
562 loadslot = offset >> 2;
564 /* loading from the same slot twice is bad (and shouldn't happen...) */
565 if (loads[loadslot] != NULL)
568 dreg = arch_get_irn_register(arch_env, node);
569 if (regmask & (1 << dreg->index)) {
570 /* this register is already used */
573 regmask |= 1 << dreg->index;
575 loads[loadslot] = node;
576 if (loadslot > maxslot)
583 /* find the first slot */
584 for (i = maxslot; i >= 0; --i) {
585 ir_node *load = loads[i];
591 ofs = inc_ofs - (maxslot + 1) * 4;
594 /* create a new IncSP if needed */
595 block = get_nodes_block(irn);
598 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
599 sched_add_before(irn, pred_sp);
602 /* walk through the Loads and create Pops for them */
603 for (++i; i <= maxslot; ++i) {
604 ir_node *load = loads[i];
606 const ir_edge_t *edge, *tmp;
607 const arch_register_t *reg;
609 mem = get_irn_n(load, n_ia32_mem);
610 reg = arch_get_irn_register(arch_env, load);
612 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
613 arch_set_irn_register(arch_env, pop, reg);
615 /* create stackpointer Proj */
616 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
617 arch_set_irn_register(arch_env, pred_sp, esp);
619 sched_add_before(irn, pop);
622 foreach_out_edge_safe(load, edge, tmp) {
623 ir_node *proj = get_edge_src_irn(edge);
625 set_Proj_pred(proj, pop);
628 /* we can remove the Load now */
633 be_set_IncSP_offset(irn, -ofs);
634 be_set_IncSP_pred(irn, pred_sp);
639 * Find a free GP register if possible, else return NULL.
641 static const arch_register_t *get_free_gp_reg(void)
645 for(i = 0; i < N_ia32_gp_REGS; ++i) {
646 const arch_register_t *reg = &ia32_gp_regs[i];
647 if(arch_register_type_is(reg, ignore))
650 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
651 return &ia32_gp_regs[i];
658 * Creates a Pop instruction before the given schedule point.
660 * @param dbgi debug info
661 * @param irg the graph
662 * @param block the block
663 * @param stack the previous stack value
664 * @param schedpoint the new node is added before this node
665 * @param reg the register to pop
667 * @return the new stack value
669 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
670 ir_node *stack, ir_node *schedpoint,
671 const arch_register_t *reg)
673 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
679 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
681 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
682 arch_set_irn_register(arch_env, stack, esp);
683 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
684 arch_set_irn_register(arch_env, val, reg);
686 sched_add_before(schedpoint, pop);
689 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
690 sched_add_before(schedpoint, keep);
696 * Creates a Push instruction before the given schedule point.
698 * @param dbgi debug info
699 * @param irg the graph
700 * @param block the block
701 * @param stack the previous stack value
702 * @param schedpoint the new node is added before this node
703 * @param reg the register to pop
705 * @return the new stack value
707 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
708 ir_node *stack, ir_node *schedpoint)
710 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
712 ir_node *val = ia32_new_Unknown_gp(cg);
713 ir_node *noreg = ia32_new_NoReg_gp(cg);
714 ir_node *nomem = get_irg_no_mem(irg);
715 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
716 sched_add_before(schedpoint, push);
718 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
719 arch_set_irn_register(arch_env, stack, esp);
725 * Optimize an IncSp by replacing it with Push/Pop.
727 static void peephole_be_IncSP(ir_node *node)
729 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
730 const arch_register_t *reg;
731 ir_graph *irg = current_ir_graph;
737 /* first optimize incsp->incsp combinations */
738 node = be_peephole_IncSP_IncSP(node);
740 /* transform IncSP->Store combinations to Push where possible */
741 peephole_IncSP_Store_to_push(node);
743 /* transform Load->IncSP combinations to Pop where possible */
744 peephole_Load_IncSP_to_pop(node);
746 if (arch_get_irn_register(arch_env, node) != esp)
749 /* replace IncSP -4 by Pop freereg when possible */
750 offset = be_get_IncSP_offset(node);
751 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
752 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
753 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
754 (offset != +8 || ia32_cg_config.use_sub_esp_8))
758 /* we need a free register for pop */
759 reg = get_free_gp_reg();
763 dbgi = get_irn_dbg_info(node);
764 block = get_nodes_block(node);
765 stack = be_get_IncSP_pred(node);
767 stack = create_pop(dbgi, irg, block, stack, node, reg);
770 stack = create_pop(dbgi, irg, block, stack, node, reg);
773 dbgi = get_irn_dbg_info(node);
774 block = get_nodes_block(node);
775 stack = be_get_IncSP_pred(node);
776 stack = create_push(dbgi, irg, block, stack, node);
779 stack = create_push(dbgi, irg, block, stack, node);
783 be_peephole_exchange(node, stack);
787 * Peephole optimisation for ia32_Const's
789 static void peephole_ia32_Const(ir_node *node)
791 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
792 const arch_register_t *reg;
793 ir_graph *irg = current_ir_graph;
800 /* try to transform a mov 0, reg to xor reg reg */
801 if (attr->offset != 0 || attr->symconst != NULL)
803 if (ia32_cg_config.use_mov_0)
805 /* xor destroys the flags, so no-one must be using them */
806 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
809 reg = arch_get_irn_register(arch_env, node);
810 assert(be_peephole_get_reg_value(reg) == NULL);
812 /* create xor(produceval, produceval) */
813 block = get_nodes_block(node);
814 dbgi = get_irn_dbg_info(node);
815 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
816 arch_set_irn_register(arch_env, produceval, reg);
818 noreg = ia32_new_NoReg_gp(cg);
819 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
820 produceval, produceval);
821 arch_set_irn_register(arch_env, xor, reg);
823 sched_add_before(node, produceval);
824 sched_add_before(node, xor);
826 be_peephole_exchange(node, xor);
829 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
831 return node == cg->noreg_gp;
834 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
836 ir_graph *irg = current_ir_graph;
837 ir_node *start_block = get_irg_start_block(irg);
838 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
840 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
845 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
848 ir_graph *irg = get_irn_irg(node);
849 ir_node *block = get_nodes_block(node);
850 int offset = get_ia32_am_offs_int(node);
851 int sc_sign = is_ia32_am_sc_sign(node);
852 ir_entity *entity = get_ia32_am_sc(node);
855 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
856 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
860 static int is_am_one(const ir_node *node)
862 int offset = get_ia32_am_offs_int(node);
863 ir_entity *entity = get_ia32_am_sc(node);
865 return offset == 1 && entity == NULL;
868 static int is_am_minus_one(const ir_node *node)
870 int offset = get_ia32_am_offs_int(node);
871 ir_entity *entity = get_ia32_am_sc(node);
873 return offset == -1 && entity == NULL;
877 * Transforms a LEA into an Add or SHL if possible.
879 static void peephole_ia32_Lea(ir_node *node)
881 const arch_env_t *arch_env = cg->arch_env;
882 ir_graph *irg = current_ir_graph;
885 const arch_register_t *base_reg;
886 const arch_register_t *index_reg;
887 const arch_register_t *out_reg;
898 assert(is_ia32_Lea(node));
900 /* we can only do this if are allowed to globber the flags */
901 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
904 base = get_irn_n(node, n_ia32_Lea_base);
905 index = get_irn_n(node, n_ia32_Lea_index);
907 if(is_noreg(cg, base)) {
911 base_reg = arch_get_irn_register(arch_env, base);
913 if(is_noreg(cg, index)) {
917 index_reg = arch_get_irn_register(arch_env, index);
920 if(base == NULL && index == NULL) {
921 /* we shouldn't construct these in the first place... */
923 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
928 out_reg = arch_get_irn_register(arch_env, node);
929 scale = get_ia32_am_scale(node);
930 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
931 /* check if we have immediates values (frame entities should already be
932 * expressed in the offsets) */
933 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
939 /* we can transform leas where the out register is the same as either the
940 * base or index register back to an Add or Shl */
941 if(out_reg == base_reg) {
944 if(!has_immediates) {
945 ir_fprintf(stderr, "Optimisation warning: found lea which is "
950 goto make_add_immediate;
952 if(scale == 0 && !has_immediates) {
957 /* can't create an add */
959 } else if(out_reg == index_reg) {
961 if(has_immediates && scale == 0) {
963 goto make_add_immediate;
964 } else if(!has_immediates && scale > 0) {
966 op2 = create_immediate_from_int(cg, scale);
968 } else if(!has_immediates) {
970 ir_fprintf(stderr, "Optimisation warning: found lea which is "
974 } else if(scale == 0 && !has_immediates) {
979 /* can't create an add */
982 /* can't create an add */
987 if(ia32_cg_config.use_incdec) {
988 if(is_am_one(node)) {
989 dbgi = get_irn_dbg_info(node);
990 block = get_nodes_block(node);
991 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
992 arch_set_irn_register(arch_env, res, out_reg);
995 if(is_am_minus_one(node)) {
996 dbgi = get_irn_dbg_info(node);
997 block = get_nodes_block(node);
998 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
999 arch_set_irn_register(arch_env, res, out_reg);
1003 op2 = create_immediate_from_am(cg, node);
1006 dbgi = get_irn_dbg_info(node);
1007 block = get_nodes_block(node);
1008 noreg = ia32_new_NoReg_gp(cg);
1009 nomem = new_NoMem();
1010 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1011 arch_set_irn_register(arch_env, res, out_reg);
1012 set_ia32_commutative(res);
1016 dbgi = get_irn_dbg_info(node);
1017 block = get_nodes_block(node);
1018 noreg = ia32_new_NoReg_gp(cg);
1019 nomem = new_NoMem();
1020 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1021 arch_set_irn_register(arch_env, res, out_reg);
1025 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1027 /* add new ADD/SHL to schedule */
1028 DBG_OPT_LEA2ADD(node, res);
1030 /* exchange the Add and the LEA */
1031 sched_add_before(node, res);
1032 be_peephole_exchange(node, res);
1036 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1038 static void peephole_ia32_Imul_split(ir_node *imul) {
1039 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1040 const arch_register_t *reg;
1041 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
1045 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1046 /* no memory, imm form ignore */
1049 /* we need a free register */
1050 reg = get_free_gp_reg();
1054 /* fine, we can rebuild it */
1055 dbgi = get_irn_dbg_info(imul);
1056 block = get_nodes_block(imul);
1057 irg = current_ir_graph;
1058 base = get_irn_n(imul, n_ia32_IMul_base);
1059 index = get_irn_n(imul, n_ia32_IMul_index);
1060 mem = get_irn_n(imul, n_ia32_IMul_mem);
1061 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
1063 /* copy all attributes */
1064 set_irn_pinned(load, get_irn_pinned(imul));
1065 set_ia32_op_type(load, ia32_AddrModeS);
1066 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1068 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1069 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1070 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1071 if (is_ia32_am_sc_sign(imul))
1072 set_ia32_am_sc_sign(load);
1073 if (is_ia32_use_frame(imul))
1074 set_ia32_use_frame(load);
1075 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1077 sched_add_before(imul, load);
1079 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1080 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1082 arch_set_irn_register(arch_env, res, reg);
1083 be_peephole_new_node(res);
1085 set_irn_n(imul, n_ia32_IMul_mem, mem);
1086 noreg = get_irn_n(imul, n_ia32_IMul_left);
1087 set_irn_n(imul, n_ia32_IMul_left, res);
1088 set_ia32_op_type(imul, ia32_Normal);
1092 * Replace xorps r,r and xorpd r,r by pxor r,r
1094 static void peephole_ia32_xZero(ir_node *xor) {
1095 set_irn_op(xor, op_ia32_xPzero);
1099 * Register a peephole optimisation function.
1101 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1102 assert(op->ops.generic == NULL);
1103 op->ops.generic = (op_func)func;
1106 /* Perform peephole-optimizations. */
1107 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1110 arch_env = cg->arch_env;
1112 /* register peephole optimisations */
1113 clear_irp_opcodes_generic_func();
1114 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1115 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1116 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1117 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1118 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1119 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1120 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1121 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1122 if (! ia32_cg_config.use_imul_mem_imm32)
1123 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1124 if (ia32_cg_config.use_pxor)
1125 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1127 be_peephole_opt(cg->birg);
1131 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1132 * all it's Projs are removed as well.
1133 * @param irn The irn to be removed from schedule
1135 static INLINE void try_kill(ir_node *node)
1137 if(get_irn_mode(node) == mode_T) {
1138 const ir_edge_t *edge, *next;
1139 foreach_out_edge_safe(node, edge, next) {
1140 ir_node *proj = get_edge_src_irn(edge);
1145 if(get_irn_n_edges(node) != 0)
1148 if (sched_is_scheduled(node)) {
1155 static void optimize_conv_store(ir_node *node)
1160 ir_mode *store_mode;
1162 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1165 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1166 pred_proj = get_irn_n(node, n_ia32_Store_val);
1167 if(is_Proj(pred_proj)) {
1168 pred = get_Proj_pred(pred_proj);
1172 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1174 if(get_ia32_op_type(pred) != ia32_Normal)
1177 /* the store only stores the lower bits, so we only need the conv
1178 * it it shrinks the mode */
1179 conv_mode = get_ia32_ls_mode(pred);
1180 store_mode = get_ia32_ls_mode(node);
1181 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1184 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1185 if(get_irn_n_edges(pred_proj) == 0) {
1186 kill_node(pred_proj);
1187 if(pred != pred_proj)
1192 static void optimize_load_conv(ir_node *node)
1194 ir_node *pred, *predpred;
1198 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1201 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1202 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1206 predpred = get_Proj_pred(pred);
1207 if(!is_ia32_Load(predpred))
1210 /* the load is sign extending the upper bits, so we only need the conv
1211 * if it shrinks the mode */
1212 load_mode = get_ia32_ls_mode(predpred);
1213 conv_mode = get_ia32_ls_mode(node);
1214 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1217 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1218 /* change the load if it has only 1 user */
1219 if(get_irn_n_edges(pred) == 1) {
1221 if(get_mode_sign(conv_mode)) {
1222 newmode = find_signed_mode(load_mode);
1224 newmode = find_unsigned_mode(load_mode);
1226 assert(newmode != NULL);
1227 set_ia32_ls_mode(predpred, newmode);
1229 /* otherwise we have to keep the conv */
1235 exchange(node, pred);
1238 static void optimize_conv_conv(ir_node *node)
1240 ir_node *pred_proj, *pred, *result_conv;
1241 ir_mode *pred_mode, *conv_mode;
1245 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1248 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1249 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1250 if(is_Proj(pred_proj))
1251 pred = get_Proj_pred(pred_proj);
1255 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1258 /* we know that after a conv, the upper bits are sign extended
1259 * so we only need the 2nd conv if it shrinks the mode */
1260 conv_mode = get_ia32_ls_mode(node);
1261 conv_mode_bits = get_mode_size_bits(conv_mode);
1262 pred_mode = get_ia32_ls_mode(pred);
1263 pred_mode_bits = get_mode_size_bits(pred_mode);
1265 if(conv_mode_bits == pred_mode_bits
1266 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1267 result_conv = pred_proj;
1268 } else if(conv_mode_bits <= pred_mode_bits) {
1269 /* if 2nd conv is smaller then first conv, then we can always take the
1271 if(get_irn_n_edges(pred_proj) == 1) {
1272 result_conv = pred_proj;
1273 set_ia32_ls_mode(pred, conv_mode);
1275 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1276 if (get_mode_size_bits(conv_mode) == 8) {
1277 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1278 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1281 /* we don't want to end up with 2 loads, so we better do nothing */
1282 if(get_irn_mode(pred) == mode_T) {
1286 result_conv = exact_copy(pred);
1287 set_ia32_ls_mode(result_conv, conv_mode);
1289 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1290 if (get_mode_size_bits(conv_mode) == 8) {
1291 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1292 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1296 /* if both convs have the same sign, then we can take the smaller one */
1297 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1298 result_conv = pred_proj;
1300 /* no optimisation possible if smaller conv is sign-extend */
1301 if(mode_is_signed(pred_mode)) {
1304 /* we can take the smaller conv if it is unsigned */
1305 result_conv = pred_proj;
1310 exchange(node, result_conv);
1312 if(get_irn_n_edges(pred_proj) == 0) {
1313 kill_node(pred_proj);
1314 if(pred != pred_proj)
1317 optimize_conv_conv(result_conv);
1320 static void optimize_node(ir_node *node, void *env)
1324 optimize_load_conv(node);
1325 optimize_conv_store(node);
1326 optimize_conv_conv(node);
1330 * Performs conv and address mode optimization.
1332 void ia32_optimize_graph(ia32_code_gen_t *cg)
1334 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1337 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1340 void ia32_init_optimize(void)
1342 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");