2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
45 #include "../benode.h"
46 #include "../besched.h"
47 #include "../bepeephole.h"
49 #include "ia32_new_nodes.h"
50 #include "ia32_optimize.h"
51 #include "bearch_ia32_t.h"
52 #include "gen_ia32_regalloc_if.h"
53 #include "ia32_common_transform.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static void copy_mark(const ir_node *old, ir_node *newn)
62 if (is_ia32_is_reload(old))
63 set_ia32_is_reload(newn);
64 if (is_ia32_is_spill(old))
65 set_ia32_is_spill(newn);
66 if (is_ia32_is_remat(old))
67 set_ia32_is_remat(newn);
70 typedef enum produces_flag_t {
77 * Return which usable flag the given node produces
79 * @param node the node to check
80 * @param pn the projection number of the used result
82 static produces_flag_t produces_test_flag(ir_node *node, int pn)
85 const ia32_immediate_attr_t *imm_attr;
87 if (!is_ia32_irn(node))
88 return produces_no_flag;
90 switch (get_ia32_irn_opcode(node)) {
105 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
106 count = get_irn_n(node, n_ia32_ShlD_count);
107 goto check_shift_amount;
112 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
113 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
114 count = get_irn_n(node, n_ia32_Shl_count);
116 /* when shift count is zero the flags are not affected, so we can only
117 * do this for constants != 0 */
118 if (!is_ia32_Immediate(count))
119 return produces_no_flag;
121 imm_attr = get_ia32_immediate_attr_const(count);
122 if (imm_attr->symconst != NULL)
123 return produces_no_flag;
124 if ((imm_attr->offset & 0x1f) == 0)
125 return produces_no_flag;
129 return pn == pn_ia32_Mul_res_high ?
130 produces_flag_carry : produces_no_flag;
133 return produces_no_flag;
136 return pn == pn_ia32_res ?
137 produces_flag_zero : produces_no_flag;
141 * Replace Cmp(x, 0) by a Test(x, x)
143 static void peephole_ia32_Cmp(ir_node *const node)
147 ia32_immediate_attr_t const *imm;
153 ia32_attr_t const *attr;
156 arch_register_t const *reg;
157 ir_edge_t const *edge;
158 ir_edge_t const *tmp;
160 if (get_ia32_op_type(node) != ia32_Normal)
163 right = get_irn_n(node, n_ia32_Cmp_right);
164 if (!is_ia32_Immediate(right))
167 imm = get_ia32_immediate_attr_const(right);
168 if (imm->symconst != NULL || imm->offset != 0)
171 dbgi = get_irn_dbg_info(node);
172 irg = get_irn_irg(node);
173 block = get_nodes_block(node);
174 noreg = ia32_new_NoReg_gp(irg);
175 nomem = get_irg_no_mem(current_ir_graph);
176 op = get_irn_n(node, n_ia32_Cmp_left);
177 attr = get_ia32_attr(node);
178 ins_permuted = attr->data.ins_permuted;
180 if (is_ia32_Cmp(node)) {
181 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
182 op, op, ins_permuted);
184 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
185 op, op, ins_permuted);
187 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
189 reg = arch_irn_get_register(node, pn_ia32_Cmp_eflags);
190 arch_irn_set_register(test, pn_ia32_Test_eflags, reg);
192 foreach_out_edge_safe(node, edge, tmp) {
193 ir_node *const user = get_edge_src_irn(edge);
196 exchange(user, test);
199 sched_add_before(node, test);
200 copy_mark(node, test);
201 be_peephole_exchange(node, test);
205 * Peephole optimization for Test instructions.
206 * - Remove the Test, if an appropriate flag was produced which is still live
207 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
209 static void peephole_ia32_Test(ir_node *node)
211 ir_node *left = get_irn_n(node, n_ia32_Test_left);
212 ir_node *right = get_irn_n(node, n_ia32_Test_right);
214 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
215 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
217 if (left == right) { /* we need a test for 0 */
218 ir_node *block = get_nodes_block(node);
219 int pn = pn_ia32_res;
224 const ir_edge_t *edge;
226 if (get_nodes_block(left) != block)
230 pn = get_Proj_proj(op);
231 op = get_Proj_pred(op);
234 /* walk schedule up and abort when we find left or some other node
235 * destroys the flags */
238 schedpoint = sched_prev(schedpoint);
239 if (schedpoint == op)
241 if (arch_irn_is(schedpoint, modify_flags))
243 if (schedpoint == block)
244 panic("couldn't find left");
247 /* make sure only Lg/Eq tests are used */
248 foreach_out_edge(node, edge) {
249 ir_node *user = get_edge_src_irn(edge);
250 ia32_condition_code_t cc = get_ia32_condcode(user);
252 if (cc != ia32_cc_equal && cc != ia32_cc_not_equal) {
257 switch (produces_test_flag(op, pn)) {
258 case produces_flag_zero:
261 case produces_flag_carry:
262 foreach_out_edge(node, edge) {
263 ir_node *user = get_edge_src_irn(edge);
264 ia32_condition_code_t cc = get_ia32_condcode(user);
267 case ia32_cc_equal: cc = ia32_cc_above_equal; break; /* CF = 0 */
268 case ia32_cc_not_equal: cc = ia32_cc_below; break; /* CF = 1 */
269 default: panic("unexpected pn");
271 set_ia32_condcode(user, cc);
279 if (get_irn_mode(op) != mode_T) {
280 set_irn_mode(op, mode_T);
282 /* If there are other users, reroute them to result proj */
283 if (get_irn_n_edges(op) != 2) {
284 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
286 edges_reroute(op, res);
287 /* Reattach the result proj to left */
288 set_Proj_pred(res, op);
291 if (get_irn_n_edges(left) == 2)
295 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
296 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
297 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
299 assert(get_irn_mode(node) != mode_T);
301 be_peephole_exchange(node, flags_proj);
302 } else if (is_ia32_Immediate(right)) {
303 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
306 /* A test with a symconst is rather strange, but better safe than sorry */
307 if (imm->symconst != NULL)
310 offset = imm->offset;
311 if (get_ia32_op_type(node) == ia32_AddrModeS) {
312 ia32_attr_t *const attr = get_ia32_attr(node);
314 if ((offset & 0xFFFFFF00) == 0) {
315 /* attr->am_offs += 0; */
316 } else if ((offset & 0xFFFF00FF) == 0) {
317 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 8);
318 set_irn_n(node, n_ia32_Test_right, imm);
320 } else if ((offset & 0xFF00FFFF) == 0) {
321 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 16);
322 set_irn_n(node, n_ia32_Test_right, imm);
324 } else if ((offset & 0x00FFFFFF) == 0) {
325 ir_node *imm = ia32_create_Immediate(NULL, 0, offset >> 24);
326 set_irn_n(node, n_ia32_Test_right, imm);
331 } else if (offset < 256) {
332 arch_register_t const* const reg = arch_get_irn_register(left);
334 if (reg != &ia32_registers[REG_EAX] &&
335 reg != &ia32_registers[REG_EBX] &&
336 reg != &ia32_registers[REG_ECX] &&
337 reg != &ia32_registers[REG_EDX]) {
344 /* Technically we should build a Test8Bit because of the register
345 * constraints, but nobody changes registers at this point anymore. */
346 set_ia32_ls_mode(node, mode_Bu);
351 * AMD Athlon works faster when RET is not destination of
352 * conditional jump or directly preceded by other jump instruction.
353 * Can be avoided by placing a Rep prefix before the return.
355 static void peephole_ia32_Return(ir_node *node)
359 if (!ia32_cg_config.use_pad_return)
362 /* check if this return is the first on the block */
363 sched_foreach_reverse_from(node, irn) {
364 switch (get_irn_opcode(irn)) {
366 /* the return node itself, ignore */
370 /* ignore no code generated */
373 /* arg, IncSP 0 nodes might occur, ignore these */
374 if (be_get_IncSP_offset(irn) == 0)
384 /* ensure, that the 3 byte return is generated */
385 be_Return_set_emit_pop(node, 1);
388 /* only optimize up to 48 stores behind IncSPs */
389 #define MAXPUSH_OPTIMIZE 48
392 * Tries to create Push's from IncSP, Store combinations.
393 * The Stores are replaced by Push's, the IncSP is modified
394 * (possibly into IncSP 0, but not removed).
396 static void peephole_IncSP_Store_to_push(ir_node *irn)
402 ir_node *stores[MAXPUSH_OPTIMIZE];
407 ir_node *first_push = NULL;
408 ir_edge_t const *edge;
409 ir_edge_t const *next;
411 memset(stores, 0, sizeof(stores));
413 assert(be_is_IncSP(irn));
415 inc_ofs = be_get_IncSP_offset(irn);
420 * We first walk the schedule after the IncSP node as long as we find
421 * suitable Stores that could be transformed to a Push.
422 * We save them into the stores array which is sorted by the frame offset/4
423 * attached to the node
426 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
431 /* it has to be a Store */
432 if (!is_ia32_Store(node))
435 /* it has to use our sp value */
436 if (get_irn_n(node, n_ia32_base) != irn)
438 /* Store has to be attached to NoMem */
439 mem = get_irn_n(node, n_ia32_mem);
443 /* unfortunately we can't support the full AMs possible for push at the
444 * moment. TODO: fix this */
445 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
448 offset = get_ia32_am_offs_int(node);
449 /* we should NEVER access uninitialized stack BELOW the current SP */
452 /* storing at half-slots is bad */
453 if ((offset & 3) != 0)
456 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
458 storeslot = offset >> 2;
460 /* storing into the same slot twice is bad (and shouldn't happen...) */
461 if (stores[storeslot] != NULL)
464 stores[storeslot] = node;
465 if (storeslot > maxslot)
471 for (i = -1; i < maxslot; ++i) {
472 if (stores[i + 1] == NULL)
476 /* walk through the Stores and create Pushs for them */
477 block = get_nodes_block(irn);
478 spmode = get_irn_mode(irn);
479 irg = get_irn_irg(irn);
480 for (; i >= 0; --i) {
481 const arch_register_t *spreg;
483 ir_node *val, *mem, *mem_proj;
484 ir_node *store = stores[i];
485 ir_node *noreg = ia32_new_NoReg_gp(irg);
487 val = get_irn_n(store, n_ia32_unary_op);
488 mem = get_irn_n(store, n_ia32_mem);
489 spreg = arch_get_irn_register(curr_sp);
491 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg, mem, val, curr_sp);
492 copy_mark(store, push);
494 if (first_push == NULL)
497 sched_add_after(skip_Proj(curr_sp), push);
499 /* create stackpointer Proj */
500 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
501 arch_set_irn_register(curr_sp, spreg);
503 /* create memory Proj */
504 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
506 /* use the memproj now */
507 be_peephole_exchange(store, mem_proj);
512 foreach_out_edge_safe(irn, edge, next) {
513 ir_node *const src = get_edge_src_irn(edge);
514 int const pos = get_edge_src_pos(edge);
516 if (src == first_push)
519 set_irn_n(src, pos, curr_sp);
522 be_set_IncSP_offset(irn, inc_ofs);
527 * Creates a Push instruction before the given schedule point.
529 * @param dbgi debug info
530 * @param block the block
531 * @param stack the previous stack value
532 * @param schedpoint the new node is added before this node
533 * @param reg the register to pop
535 * @return the new stack value
537 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
538 ir_node *stack, ir_node *schedpoint)
540 const arch_register_t *esp = &ia32_registers[REG_ESP];
542 ir_node *val = ia32_new_NoReg_gp(cg);
543 ir_node *noreg = ia32_new_NoReg_gp(cg);
544 ir_graph *irg = get_irn_irg(block);
545 ir_node *nomem = get_irg_no_mem(irg);
546 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
547 sched_add_before(schedpoint, push);
549 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
550 arch_set_irn_register(stack, esp);
555 static void peephole_store_incsp(ir_node *store)
566 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
567 if (!be_is_IncSP(am_base)
568 || get_nodes_block(am_base) != get_nodes_block(store))
570 mem = get_irn_n(store, n_ia32_Store_mem);
571 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
575 int incsp_offset = be_get_IncSP_offset(am_base);
576 if (incsp_offset <= 0)
579 /* we have to be at offset 0 */
580 int my_offset = get_ia32_am_offs_int(store);
581 if (my_offset != 0) {
582 /* TODO here: find out whether there is a store with offset 0 before
583 * us and whether we can move it down to our place */
586 ir_mode *ls_mode = get_ia32_ls_mode(store);
587 int my_store_size = get_mode_size_bytes(ls_mode);
589 if (my_offset + my_store_size > incsp_offset)
592 /* correctness checking:
593 - noone else must write to that stackslot
594 (because after translation incsp won't allocate it anymore)
596 sched_foreach_reverse_from(store, node) {
602 /* make sure noone else can use the space on the stack */
603 arity = get_irn_arity(node);
604 for (i = 0; i < arity; ++i) {
605 ir_node *pred = get_irn_n(node, i);
609 if (i == n_ia32_base &&
610 (get_ia32_op_type(node) == ia32_AddrModeS
611 || get_ia32_op_type(node) == ia32_AddrModeD)) {
612 int node_offset = get_ia32_am_offs_int(node);
613 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
614 int node_size = get_mode_size_bytes(node_ls_mode);
615 /* overlapping with our position? abort */
616 if (node_offset < my_offset + my_store_size
617 && node_offset + node_size >= my_offset)
619 /* otherwise it's fine */
623 /* strange use of esp: abort */
628 /* all ok, change to push */
629 dbgi = get_irn_dbg_info(store);
630 block = get_nodes_block(store);
631 noreg = ia32_new_NoReg_gp(cg);
632 val = get_irn_n(store, n_ia32_Store_val);
634 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
636 create_push(dbgi, current_ir_graph, block, am_base, store);
641 * Return true if a mode can be stored in the GP register set
643 static inline int mode_needs_gp_reg(ir_mode *mode)
645 if (mode == ia32_mode_fpcw)
647 if (get_mode_size_bits(mode) > 32)
649 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
653 * Tries to create Pops from Load, IncSP combinations.
654 * The Loads are replaced by Pops, the IncSP is modified
655 * (possibly into IncSP 0, but not removed).
657 static void peephole_Load_IncSP_to_pop(ir_node *irn)
659 const arch_register_t *esp = &ia32_registers[REG_ESP];
660 int i, maxslot, inc_ofs, ofs;
661 ir_node *node, *pred_sp, *block;
662 ir_node *loads[MAXPUSH_OPTIMIZE];
663 unsigned regmask = 0;
664 unsigned copymask = ~0;
666 memset(loads, 0, sizeof(loads));
667 assert(be_is_IncSP(irn));
669 inc_ofs = -be_get_IncSP_offset(irn);
674 * We first walk the schedule before the IncSP node as long as we find
675 * suitable Loads that could be transformed to a Pop.
676 * We save them into the stores array which is sorted by the frame offset/4
677 * attached to the node
680 pred_sp = be_get_IncSP_pred(irn);
681 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
684 const arch_register_t *sreg, *dreg;
686 /* it has to be a Load */
687 if (!is_ia32_Load(node)) {
688 if (be_is_Copy(node)) {
689 if (!mode_needs_gp_reg(get_irn_mode(node))) {
690 /* not a GP copy, ignore */
693 dreg = arch_get_irn_register(node);
694 sreg = arch_get_irn_register(be_get_Copy_op(node));
695 if (regmask & copymask & (1 << sreg->index)) {
698 if (regmask & copymask & (1 << dreg->index)) {
701 /* we CAN skip Copies if neither the destination nor the source
702 * is not in our regmask, ie none of our future Pop will overwrite it */
703 regmask |= (1 << dreg->index) | (1 << sreg->index);
704 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
710 /* we can handle only GP loads */
711 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
714 /* it has to use our predecessor sp value */
715 if (get_irn_n(node, n_ia32_base) != pred_sp) {
716 /* it would be ok if this load does not use a Pop result,
717 * but we do not check this */
721 /* should have NO index */
722 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
725 offset = get_ia32_am_offs_int(node);
726 /* we should NEVER access uninitialized stack BELOW the current SP */
729 /* storing at half-slots is bad */
730 if ((offset & 3) != 0)
733 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
735 /* ignore those outside the possible windows */
736 if (offset > inc_ofs - 4)
738 loadslot = offset >> 2;
740 /* loading from the same slot twice is bad (and shouldn't happen...) */
741 if (loads[loadslot] != NULL)
744 dreg = arch_irn_get_register(node, pn_ia32_Load_res);
745 if (regmask & (1 << dreg->index)) {
746 /* this register is already used */
749 regmask |= 1 << dreg->index;
751 loads[loadslot] = node;
752 if (loadslot > maxslot)
759 /* find the first slot */
760 for (i = maxslot; i >= 0; --i) {
761 ir_node *load = loads[i];
767 ofs = inc_ofs - (maxslot + 1) * 4;
770 /* create a new IncSP if needed */
771 block = get_nodes_block(irn);
773 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
774 sched_add_before(irn, pred_sp);
777 /* walk through the Loads and create Pops for them */
778 for (++i; i <= maxslot; ++i) {
779 ir_node *load = loads[i];
781 const ir_edge_t *edge, *tmp;
782 const arch_register_t *reg;
784 mem = get_irn_n(load, n_ia32_mem);
785 reg = arch_irn_get_register(load, pn_ia32_Load_res);
787 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
788 arch_irn_set_register(pop, pn_ia32_Load_res, reg);
790 copy_mark(load, pop);
792 /* create stackpointer Proj */
793 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
794 arch_set_irn_register(pred_sp, esp);
796 sched_add_before(irn, pop);
799 foreach_out_edge_safe(load, edge, tmp) {
800 ir_node *proj = get_edge_src_irn(edge);
802 set_Proj_pred(proj, pop);
805 /* we can remove the Load now */
810 be_set_IncSP_offset(irn, -ofs);
811 be_set_IncSP_pred(irn, pred_sp);
816 * Find a free GP register if possible, else return NULL.
818 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
820 be_irg_t *birg = be_birg_from_irg(irg);
823 for (i = 0; i < N_ia32_gp_REGS; ++i) {
824 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
825 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
828 if (be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
836 * Creates a Pop instruction before the given schedule point.
838 * @param dbgi debug info
839 * @param block the block
840 * @param stack the previous stack value
841 * @param schedpoint the new node is added before this node
842 * @param reg the register to pop
844 * @return the new stack value
846 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
847 ir_node *stack, ir_node *schedpoint,
848 const arch_register_t *reg)
850 const arch_register_t *esp = &ia32_registers[REG_ESP];
851 ir_graph *irg = get_irn_irg(block);
857 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
859 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
860 arch_set_irn_register(stack, esp);
861 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
862 arch_set_irn_register(val, reg);
864 sched_add_before(schedpoint, pop);
867 keep = be_new_Keep(block, 1, in);
868 sched_add_before(schedpoint, keep);
874 * Optimize an IncSp by replacing it with Push/Pop.
876 static void peephole_be_IncSP(ir_node *node)
878 const arch_register_t *esp = &ia32_registers[REG_ESP];
879 const arch_register_t *reg;
885 /* first optimize incsp->incsp combinations */
886 node = be_peephole_IncSP_IncSP(node);
888 /* transform IncSP->Store combinations to Push where possible */
889 peephole_IncSP_Store_to_push(node);
891 /* transform Load->IncSP combinations to Pop where possible */
892 peephole_Load_IncSP_to_pop(node);
894 if (arch_get_irn_register(node) != esp)
897 /* replace IncSP -4 by Pop freereg when possible */
898 offset = be_get_IncSP_offset(node);
899 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
900 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
901 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
902 (offset != +8 || ia32_cg_config.use_sub_esp_8))
906 /* we need a free register for pop */
907 reg = get_free_gp_reg(get_irn_irg(node));
911 dbgi = get_irn_dbg_info(node);
912 block = get_nodes_block(node);
913 stack = be_get_IncSP_pred(node);
915 stack = create_pop(dbgi, block, stack, node, reg);
918 stack = create_pop(dbgi, block, stack, node, reg);
921 dbgi = get_irn_dbg_info(node);
922 block = get_nodes_block(node);
923 stack = be_get_IncSP_pred(node);
924 stack = new_bd_ia32_PushEax(dbgi, block, stack);
925 arch_set_irn_register(stack, esp);
926 sched_add_before(node, stack);
929 stack = new_bd_ia32_PushEax(dbgi, block, stack);
930 arch_set_irn_register(stack, esp);
931 sched_add_before(node, stack);
935 be_peephole_exchange(node, stack);
939 * Peephole optimisation for ia32_Const's
941 static void peephole_ia32_Const(ir_node *node)
943 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
944 const arch_register_t *reg;
949 /* try to transform a mov 0, reg to xor reg reg */
950 if (attr->offset != 0 || attr->symconst != NULL)
952 if (ia32_cg_config.use_mov_0)
954 /* xor destroys the flags, so no-one must be using them */
955 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
958 reg = arch_get_irn_register(node);
959 assert(be_peephole_get_reg_value(reg) == NULL);
961 /* create xor(produceval, produceval) */
962 block = get_nodes_block(node);
963 dbgi = get_irn_dbg_info(node);
964 xorn = new_bd_ia32_Xor0(dbgi, block);
965 arch_set_irn_register(xorn, reg);
967 sched_add_before(node, xorn);
969 copy_mark(node, xorn);
970 be_peephole_exchange(node, xorn);
973 static inline int is_noreg(const ir_node *node)
975 return is_ia32_NoReg_GP(node);
978 ir_node *ia32_immediate_from_long(long val)
980 ir_graph *irg = current_ir_graph;
981 ir_node *start_block = get_irg_start_block(irg);
983 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
984 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
989 static ir_node *create_immediate_from_am(const ir_node *node)
991 ir_node *block = get_nodes_block(node);
992 int offset = get_ia32_am_offs_int(node);
993 int sc_sign = is_ia32_am_sc_sign(node);
994 const ia32_attr_t *attr = get_ia32_attr_const(node);
995 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
996 ir_entity *entity = get_ia32_am_sc(node);
999 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1001 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1005 static int is_am_one(const ir_node *node)
1007 int offset = get_ia32_am_offs_int(node);
1008 ir_entity *entity = get_ia32_am_sc(node);
1010 return offset == 1 && entity == NULL;
1013 static int is_am_minus_one(const ir_node *node)
1015 int offset = get_ia32_am_offs_int(node);
1016 ir_entity *entity = get_ia32_am_sc(node);
1018 return offset == -1 && entity == NULL;
1022 * Transforms a LEA into an Add or SHL if possible.
1024 static void peephole_ia32_Lea(ir_node *node)
1029 const arch_register_t *base_reg;
1030 const arch_register_t *index_reg;
1031 const arch_register_t *out_reg;
1042 assert(is_ia32_Lea(node));
1044 /* we can only do this if it is allowed to clobber the flags */
1045 if (be_peephole_get_value(CLASS_ia32_flags, REG_FLAGS_EFLAGS) != NULL)
1048 base = get_irn_n(node, n_ia32_Lea_base);
1049 index = get_irn_n(node, n_ia32_Lea_index);
1051 if (is_noreg(base)) {
1055 base_reg = arch_get_irn_register(base);
1057 if (is_noreg(index)) {
1061 index_reg = arch_get_irn_register(index);
1064 if (base == NULL && index == NULL) {
1065 /* we shouldn't construct these in the first place... */
1066 #ifdef DEBUG_libfirm
1067 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1072 out_reg = arch_get_irn_register(node);
1073 scale = get_ia32_am_scale(node);
1074 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1075 /* check if we have immediates values (frame entities should already be
1076 * expressed in the offsets) */
1077 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1083 /* we can transform leas where the out register is the same as either the
1084 * base or index register back to an Add or Shl */
1085 if (out_reg == base_reg) {
1086 if (index == NULL) {
1087 #ifdef DEBUG_libfirm
1088 if (!has_immediates) {
1089 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1094 goto make_add_immediate;
1096 if (scale == 0 && !has_immediates) {
1101 /* can't create an add */
1103 } else if (out_reg == index_reg) {
1105 if (has_immediates && scale == 0) {
1107 goto make_add_immediate;
1108 } else if (!has_immediates && scale > 0) {
1110 op2 = ia32_immediate_from_long(scale);
1112 } else if (!has_immediates) {
1113 #ifdef DEBUG_libfirm
1114 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1118 } else if (scale == 0 && !has_immediates) {
1123 /* can't create an add */
1126 /* can't create an add */
1131 if (ia32_cg_config.use_incdec) {
1132 if (is_am_one(node)) {
1133 dbgi = get_irn_dbg_info(node);
1134 block = get_nodes_block(node);
1135 res = new_bd_ia32_Inc(dbgi, block, op1);
1136 arch_set_irn_register(res, out_reg);
1139 if (is_am_minus_one(node)) {
1140 dbgi = get_irn_dbg_info(node);
1141 block = get_nodes_block(node);
1142 res = new_bd_ia32_Dec(dbgi, block, op1);
1143 arch_set_irn_register(res, out_reg);
1147 op2 = create_immediate_from_am(node);
1150 dbgi = get_irn_dbg_info(node);
1151 block = get_nodes_block(node);
1152 irg = get_irn_irg(node);
1153 noreg = ia32_new_NoReg_gp(irg);
1154 nomem = get_irg_no_mem(irg);
1155 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1156 arch_set_irn_register(res, out_reg);
1157 set_ia32_commutative(res);
1161 dbgi = get_irn_dbg_info(node);
1162 block = get_nodes_block(node);
1163 irg = get_irn_irg(node);
1164 noreg = ia32_new_NoReg_gp(irg);
1165 nomem = get_irg_no_mem(irg);
1166 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1167 arch_set_irn_register(res, out_reg);
1171 SET_IA32_ORIG_NODE(res, node);
1173 /* add new ADD/SHL to schedule */
1174 DBG_OPT_LEA2ADD(node, res);
1176 /* exchange the Add and the LEA */
1177 sched_add_before(node, res);
1178 copy_mark(node, res);
1179 be_peephole_exchange(node, res);
1183 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1185 static void peephole_ia32_Imul_split(ir_node *imul)
1187 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1188 const arch_register_t *reg;
1191 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1192 /* no memory, imm form ignore */
1195 /* we need a free register */
1196 reg = get_free_gp_reg(get_irn_irg(imul));
1200 /* fine, we can rebuild it */
1201 res = ia32_turn_back_am(imul);
1202 arch_set_irn_register(res, reg);
1206 * Replace xorps r,r and xorpd r,r by pxor r,r
1208 static void peephole_ia32_xZero(ir_node *xorn)
1210 set_irn_op(xorn, op_ia32_xPzero);
1214 * Replace 16bit sign extension from ax to eax by shorter cwtl
1216 static void peephole_ia32_Conv_I2I(ir_node *node)
1218 const arch_register_t *eax = &ia32_registers[REG_EAX];
1219 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1220 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1225 if (get_mode_size_bits(smaller_mode) != 16 ||
1226 !mode_is_signed(smaller_mode) ||
1227 eax != arch_get_irn_register(val) ||
1228 eax != arch_irn_get_register(node, pn_ia32_Conv_I2I_res))
1231 dbgi = get_irn_dbg_info(node);
1232 block = get_nodes_block(node);
1233 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1234 arch_set_irn_register(cwtl, eax);
1235 sched_add_before(node, cwtl);
1236 be_peephole_exchange(node, cwtl);
1240 * Register a peephole optimisation function.
1242 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1244 assert(op->ops.generic == NULL);
1245 op->ops.generic = (op_func)func;
1248 /* Perform peephole-optimizations. */
1249 void ia32_peephole_optimization(ir_graph *irg)
1251 /* register peephole optimisations */
1252 clear_irp_opcodes_generic_func();
1253 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1254 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1255 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1256 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1257 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1258 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1259 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1260 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1261 if (! ia32_cg_config.use_imul_mem_imm32)
1262 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1263 if (ia32_cg_config.use_pxor)
1264 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1265 if (ia32_cg_config.use_short_sex_eax)
1266 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1268 be_peephole_opt(irg);
1272 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1273 * all its Projs are removed as well.
1274 * @param irn The irn to be removed from schedule
1276 static inline void try_kill(ir_node *node)
1278 if (get_irn_mode(node) == mode_T) {
1279 const ir_edge_t *edge, *next;
1280 foreach_out_edge_safe(node, edge, next) {
1281 ir_node *proj = get_edge_src_irn(edge);
1286 if (get_irn_n_edges(node) != 0)
1289 if (sched_is_scheduled(node)) {
1296 static void optimize_conv_store(ir_node *node)
1301 ir_mode *store_mode;
1303 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1306 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1307 pred_proj = get_irn_n(node, n_ia32_Store_val);
1308 if (is_Proj(pred_proj)) {
1309 pred = get_Proj_pred(pred_proj);
1313 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1315 if (get_ia32_op_type(pred) != ia32_Normal)
1318 /* the store only stores the lower bits, so we only need the conv
1319 * it it shrinks the mode */
1320 conv_mode = get_ia32_ls_mode(pred);
1321 store_mode = get_ia32_ls_mode(node);
1322 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1325 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1326 if (get_irn_n_edges(pred_proj) == 0) {
1327 kill_node(pred_proj);
1328 if (pred != pred_proj)
1333 static void optimize_load_conv(ir_node *node)
1335 ir_node *pred, *predpred;
1339 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1342 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1343 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1347 predpred = get_Proj_pred(pred);
1348 if (!is_ia32_Load(predpred))
1351 /* the load is sign extending the upper bits, so we only need the conv
1352 * if it shrinks the mode */
1353 load_mode = get_ia32_ls_mode(predpred);
1354 conv_mode = get_ia32_ls_mode(node);
1355 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1358 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1359 /* change the load if it has only 1 user */
1360 if (get_irn_n_edges(pred) == 1) {
1362 if (get_mode_sign(conv_mode)) {
1363 newmode = find_signed_mode(load_mode);
1365 newmode = find_unsigned_mode(load_mode);
1367 assert(newmode != NULL);
1368 set_ia32_ls_mode(predpred, newmode);
1370 /* otherwise we have to keep the conv */
1376 exchange(node, pred);
1379 static void optimize_conv_conv(ir_node *node)
1381 ir_node *pred_proj, *pred, *result_conv;
1382 ir_mode *pred_mode, *conv_mode;
1386 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1389 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1390 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1391 if (is_Proj(pred_proj))
1392 pred = get_Proj_pred(pred_proj);
1396 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1399 /* we know that after a conv, the upper bits are sign extended
1400 * so we only need the 2nd conv if it shrinks the mode */
1401 conv_mode = get_ia32_ls_mode(node);
1402 conv_mode_bits = get_mode_size_bits(conv_mode);
1403 pred_mode = get_ia32_ls_mode(pred);
1404 pred_mode_bits = get_mode_size_bits(pred_mode);
1406 if (conv_mode_bits == pred_mode_bits
1407 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1408 result_conv = pred_proj;
1409 } else if (conv_mode_bits <= pred_mode_bits) {
1410 /* if 2nd conv is smaller then first conv, then we can always take the
1412 if (get_irn_n_edges(pred_proj) == 1) {
1413 result_conv = pred_proj;
1414 set_ia32_ls_mode(pred, conv_mode);
1416 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1417 if (get_mode_size_bits(conv_mode) == 8) {
1418 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1419 arch_set_in_register_reqs(pred,
1420 arch_get_in_register_reqs(node));
1423 /* we don't want to end up with 2 loads, so we better do nothing */
1424 if (get_irn_mode(pred) == mode_T) {
1428 result_conv = exact_copy(pred);
1429 set_ia32_ls_mode(result_conv, conv_mode);
1431 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1432 if (get_mode_size_bits(conv_mode) == 8) {
1433 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1434 arch_set_in_register_reqs(result_conv,
1435 arch_get_in_register_reqs(node));
1439 /* if both convs have the same sign, then we can take the smaller one */
1440 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1441 result_conv = pred_proj;
1443 /* no optimisation possible if smaller conv is sign-extend */
1444 if (mode_is_signed(pred_mode)) {
1447 /* we can take the smaller conv if it is unsigned */
1448 result_conv = pred_proj;
1452 /* Some user (like Phis) won't be happy if we change the mode. */
1453 set_irn_mode(result_conv, get_irn_mode(node));
1456 exchange(node, result_conv);
1458 if (get_irn_n_edges(pred_proj) == 0) {
1459 kill_node(pred_proj);
1460 if (pred != pred_proj)
1463 optimize_conv_conv(result_conv);
1466 static void optimize_node(ir_node *node, void *env)
1470 optimize_load_conv(node);
1471 optimize_conv_store(node);
1472 optimize_conv_conv(node);
1476 * Performs conv and address mode optimization.
1478 void ia32_optimize_graph(ir_graph *irg)
1480 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1483 void ia32_init_optimize(void)
1485 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");