2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
31 #include "firm_types.h"
45 #include "bepeephole.h"
47 #include "ia32_new_nodes.h"
48 #include "ia32_optimize.h"
49 #include "bearch_ia32_t.h"
50 #include "gen_ia32_regalloc_if.h"
51 #include "ia32_common_transform.h"
52 #include "ia32_transform.h"
53 #include "ia32_dbg_stat.h"
54 #include "ia32_architecture.h"
56 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
58 static void copy_mark(const ir_node *old, ir_node *newn)
60 if (is_ia32_is_reload(old))
61 set_ia32_is_reload(newn);
62 if (is_ia32_is_spill(old))
63 set_ia32_is_spill(newn);
64 if (is_ia32_is_remat(old))
65 set_ia32_is_remat(newn);
68 typedef enum produces_flag_t {
71 produces_zero_in_carry
75 * Return which usable flag the given node produces about the result.
76 * That is zero (ZF) and sign(SF).
77 * We do not check for carry (CF) or overflow (OF).
79 * @param node the node to check
80 * @param pn the projection number of the used result
82 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
85 const ia32_immediate_attr_t *imm_attr;
87 if (!is_ia32_irn(node))
88 return produces_no_flag;
90 switch (get_ia32_irn_opcode(node)) {
105 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
106 count = get_irn_n(node, n_ia32_ShlD_count);
107 goto check_shift_amount;
112 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
113 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
114 count = get_irn_n(node, n_ia32_Shl_count);
116 /* when shift count is zero the flags are not affected, so we can only
117 * do this for constants != 0 */
118 if (!is_ia32_Immediate(count))
119 return produces_no_flag;
121 imm_attr = get_ia32_immediate_attr_const(count);
122 if (imm_attr->symconst != NULL)
123 return produces_no_flag;
124 if ((imm_attr->offset & 0x1f) == 0)
125 return produces_no_flag;
129 return pn == pn_ia32_Mul_res_high ?
130 produces_zero_in_carry : produces_no_flag;
133 return produces_no_flag;
136 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
140 * Replace Cmp(x, 0) by a Test(x, x)
142 static void peephole_ia32_Cmp(ir_node *const node)
146 ia32_immediate_attr_t const *imm;
152 ia32_attr_t const *attr;
155 arch_register_t const *reg;
157 if (get_ia32_op_type(node) != ia32_Normal)
160 right = get_irn_n(node, n_ia32_Cmp_right);
161 if (!is_ia32_Immediate(right))
164 imm = get_ia32_immediate_attr_const(right);
165 if (imm->symconst != NULL || imm->offset != 0)
168 dbgi = get_irn_dbg_info(node);
169 irg = get_irn_irg(node);
170 block = get_nodes_block(node);
171 noreg = ia32_new_NoReg_gp(irg);
172 nomem = get_irg_no_mem(current_ir_graph);
173 op = get_irn_n(node, n_ia32_Cmp_left);
174 attr = get_ia32_attr(node);
175 ins_permuted = attr->data.ins_permuted;
177 if (is_ia32_Cmp(node)) {
178 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
179 op, op, ins_permuted);
181 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
182 op, op, ins_permuted);
184 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
186 reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
187 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
189 foreach_out_edge_safe(node, edge) {
190 ir_node *const user = get_edge_src_irn(edge);
193 exchange(user, test);
196 sched_add_before(node, test);
197 copy_mark(node, test);
198 be_peephole_exchange(node, test);
202 * Peephole optimization for Test instructions.
203 * - Remove the Test, if an appropriate flag was produced which is still live
204 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
206 static void peephole_ia32_Test(ir_node *node)
208 ir_node *left = get_irn_n(node, n_ia32_Test_left);
209 ir_node *right = get_irn_n(node, n_ia32_Test_right);
211 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
212 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
214 if (left == right) { /* we need a test for 0 */
215 ir_node *block = get_nodes_block(node);
216 int pn = pn_ia32_res;
222 produces_flag_t produced;
224 if (get_nodes_block(left) != block)
228 pn = get_Proj_proj(op);
229 op = get_Proj_pred(op);
232 /* walk schedule up and abort when we find left or some other node
233 * destroys the flags */
236 schedpoint = sched_prev(schedpoint);
237 if (schedpoint == op)
239 if (arch_irn_is(schedpoint, modify_flags))
241 if (schedpoint == block)
242 panic("couldn't find left");
245 produced = check_produces_zero_sign(op, pn);
246 if (produced == produces_no_flag)
249 /* make sure users only look at the sign/zero flag */
250 foreach_out_edge(node, edge) {
251 ir_node *user = get_edge_src_irn(edge);
252 ia32_condition_code_t cc = get_ia32_condcode(user);
254 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
256 if (produced == produces_zero_sign
257 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
263 op_mode = get_ia32_ls_mode(op);
265 op_mode = get_irn_mode(op);
267 /* Make sure we operate on the same bit size */
268 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
271 if (produced == produces_zero_in_carry) {
272 /* patch users to look at the carry instead of the zero flag */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 ia32_condition_code_t cc = get_ia32_condcode(user);
278 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
279 case ia32_cc_not_equal: cc = ia32_cc_below; break;
280 default: panic("unexpected pn");
282 set_ia32_condcode(user, cc);
286 if (get_irn_mode(op) != mode_T) {
287 set_irn_mode(op, mode_T);
289 /* If there are other users, reroute them to result proj */
290 if (get_irn_n_edges(op) != 2) {
291 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
293 edges_reroute(op, res);
294 /* Reattach the result proj to left */
295 set_Proj_pred(res, op);
298 if (get_irn_n_edges(left) == 2)
302 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
303 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
304 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
306 assert(get_irn_mode(node) != mode_T);
308 be_peephole_exchange(node, flags_proj);
309 } else if (is_ia32_Immediate(right)) {
310 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
313 /* A test with a symconst is rather strange, but better safe than sorry */
314 if (imm->symconst != NULL)
317 offset = imm->offset;
318 if (get_ia32_op_type(node) == ia32_AddrModeS) {
319 ia32_attr_t *const attr = get_ia32_attr(node);
321 if ((offset & 0xFFFFFF00) == 0) {
322 /* attr->am_offs += 0; */
323 } else if ((offset & 0xFFFF00FF) == 0) {
324 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8);
325 set_irn_n(node, n_ia32_Test_right, imm_node);
327 } else if ((offset & 0xFF00FFFF) == 0) {
328 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16);
329 set_irn_n(node, n_ia32_Test_right, imm_node);
331 } else if ((offset & 0x00FFFFFF) == 0) {
332 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24);
333 set_irn_n(node, n_ia32_Test_right, imm_node);
338 } else if (offset < 256) {
339 arch_register_t const* const reg = arch_get_irn_register(left);
341 if (reg != &ia32_registers[REG_EAX] &&
342 reg != &ia32_registers[REG_EBX] &&
343 reg != &ia32_registers[REG_ECX] &&
344 reg != &ia32_registers[REG_EDX]) {
351 /* Technically we should build a Test8Bit because of the register
352 * constraints, but nobody changes registers at this point anymore. */
353 set_ia32_ls_mode(node, mode_Bu);
358 * AMD Athlon works faster when RET is not destination of
359 * conditional jump or directly preceded by other jump instruction.
360 * Can be avoided by placing a Rep prefix before the return.
362 static void peephole_ia32_Return(ir_node *node)
364 if (!ia32_cg_config.use_pad_return)
367 /* check if this return is the first on the block */
368 sched_foreach_reverse_from(node, irn) {
369 switch (get_irn_opcode(irn)) {
371 /* the return node itself, ignore */
375 /* ignore no code generated */
378 /* arg, IncSP 0 nodes might occur, ignore these */
379 if (be_get_IncSP_offset(irn) == 0)
389 /* ensure, that the 3 byte return is generated */
390 be_Return_set_emit_pop(node, 1);
393 /* only optimize up to 48 stores behind IncSPs */
394 #define MAXPUSH_OPTIMIZE 48
397 * Tries to create Push's from IncSP, Store combinations.
398 * The Stores are replaced by Push's, the IncSP is modified
399 * (possibly into IncSP 0, but not removed).
401 static void peephole_IncSP_Store_to_push(ir_node *irn)
407 ir_node *stores[MAXPUSH_OPTIMIZE];
412 ir_node *first_push = NULL;
414 memset(stores, 0, sizeof(stores));
416 assert(be_is_IncSP(irn));
418 inc_ofs = be_get_IncSP_offset(irn);
423 * We first walk the schedule after the IncSP node as long as we find
424 * suitable Stores that could be transformed to a Push.
425 * We save them into the stores array which is sorted by the frame offset/4
426 * attached to the node
429 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
434 /* it has to be a Store */
435 if (!is_ia32_Store(node))
438 /* it has to use our sp value */
439 if (get_irn_n(node, n_ia32_base) != irn)
441 /* Store has to be attached to NoMem */
442 mem = get_irn_n(node, n_ia32_mem);
446 /* unfortunately we can't support the full AMs possible for push at the
447 * moment. TODO: fix this */
448 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
451 offset = get_ia32_am_offs_int(node);
452 /* we should NEVER access uninitialized stack BELOW the current SP */
455 /* storing at half-slots is bad */
456 if ((offset & 3) != 0)
459 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
461 storeslot = offset >> 2;
463 /* storing into the same slot twice is bad (and shouldn't happen...) */
464 if (stores[storeslot] != NULL)
467 stores[storeslot] = node;
468 if (storeslot > maxslot)
474 for (i = -1; i < maxslot; ++i) {
475 if (stores[i + 1] == NULL)
479 /* walk through the Stores and create Pushs for them */
480 block = get_nodes_block(irn);
481 spmode = get_irn_mode(irn);
482 irg = get_irn_irg(irn);
483 for (; i >= 0; --i) {
484 const arch_register_t *spreg;
486 ir_node *val, *mem, *mem_proj;
487 ir_node *store = stores[i];
488 ir_node *noreg = ia32_new_NoReg_gp(irg);
490 val = get_irn_n(store, n_ia32_unary_op);
491 mem = get_irn_n(store, n_ia32_mem);
492 spreg = arch_get_irn_register(curr_sp);
494 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
496 copy_mark(store, push);
498 if (first_push == NULL)
501 sched_add_after(skip_Proj(curr_sp), push);
503 /* create stackpointer Proj */
504 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
505 arch_set_irn_register(curr_sp, spreg);
507 /* create memory Proj */
508 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
510 /* rewire Store Projs */
511 foreach_out_edge_safe(store, edge) {
512 ir_node *proj = get_edge_src_irn(edge);
515 switch (get_Proj_proj(proj)) {
516 case pn_ia32_Store_M:
517 exchange(proj, mem_proj);
520 panic("unexpected Proj on Store->IncSp");
524 /* use the memproj now */
525 be_peephole_exchange(store, push);
530 foreach_out_edge_safe(irn, edge) {
531 ir_node *const src = get_edge_src_irn(edge);
532 int const pos = get_edge_src_pos(edge);
534 if (src == first_push)
537 set_irn_n(src, pos, curr_sp);
540 be_set_IncSP_offset(irn, inc_ofs);
545 * Creates a Push instruction before the given schedule point.
547 * @param dbgi debug info
548 * @param block the block
549 * @param stack the previous stack value
550 * @param schedpoint the new node is added before this node
551 * @param reg the register to pop
553 * @return the new stack value
555 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
556 ir_node *stack, ir_node *schedpoint)
558 const arch_register_t *esp = &ia32_registers[REG_ESP];
560 ir_node *val = ia32_new_NoReg_gp(cg);
561 ir_node *noreg = ia32_new_NoReg_gp(cg);
562 ir_graph *irg = get_irn_irg(block);
563 ir_node *nomem = get_irg_no_mem(irg);
564 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
565 sched_add_before(schedpoint, push);
567 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
568 arch_set_irn_register(stack, esp);
573 static void peephole_store_incsp(ir_node *store)
583 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
584 if (!be_is_IncSP(am_base)
585 || get_nodes_block(am_base) != get_nodes_block(store))
587 mem = get_irn_n(store, n_ia32_Store_mem);
588 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
592 int incsp_offset = be_get_IncSP_offset(am_base);
593 if (incsp_offset <= 0)
596 /* we have to be at offset 0 */
597 int my_offset = get_ia32_am_offs_int(store);
598 if (my_offset != 0) {
599 /* TODO here: find out whether there is a store with offset 0 before
600 * us and whether we can move it down to our place */
603 ir_mode *ls_mode = get_ia32_ls_mode(store);
604 int my_store_size = get_mode_size_bytes(ls_mode);
606 if (my_offset + my_store_size > incsp_offset)
609 /* correctness checking:
610 - noone else must write to that stackslot
611 (because after translation incsp won't allocate it anymore)
613 sched_foreach_reverse_from(store, node) {
619 /* make sure noone else can use the space on the stack */
620 arity = get_irn_arity(node);
621 for (i = 0; i < arity; ++i) {
622 ir_node *pred = get_irn_n(node, i);
626 if (i == n_ia32_base &&
627 (get_ia32_op_type(node) == ia32_AddrModeS
628 || get_ia32_op_type(node) == ia32_AddrModeD)) {
629 int node_offset = get_ia32_am_offs_int(node);
630 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
631 int node_size = get_mode_size_bytes(node_ls_mode);
632 /* overlapping with our position? abort */
633 if (node_offset < my_offset + my_store_size
634 && node_offset + node_size >= my_offset)
636 /* otherwise it's fine */
640 /* strange use of esp: abort */
645 /* all ok, change to push */
646 dbgi = get_irn_dbg_info(store);
647 block = get_nodes_block(store);
648 noreg = ia32_new_NoReg_gp(cg);
649 val = get_irn_n(store, n_ia32_Store_val);
651 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
653 create_push(dbgi, current_ir_graph, block, am_base, store);
658 * Return true if a mode can be stored in the GP register set
660 static inline int mode_needs_gp_reg(ir_mode *mode)
662 if (mode == ia32_mode_fpcw)
664 if (get_mode_size_bits(mode) > 32)
666 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
670 * Tries to create Pops from Load, IncSP combinations.
671 * The Loads are replaced by Pops, the IncSP is modified
672 * (possibly into IncSP 0, but not removed).
674 static void peephole_Load_IncSP_to_pop(ir_node *irn)
676 const arch_register_t *esp = &ia32_registers[REG_ESP];
677 int i, maxslot, inc_ofs, ofs;
678 ir_node *node, *pred_sp, *block;
679 ir_node *loads[MAXPUSH_OPTIMIZE];
680 unsigned regmask = 0;
681 unsigned copymask = ~0;
683 memset(loads, 0, sizeof(loads));
684 assert(be_is_IncSP(irn));
686 inc_ofs = -be_get_IncSP_offset(irn);
691 * We first walk the schedule before the IncSP node as long as we find
692 * suitable Loads that could be transformed to a Pop.
693 * We save them into the stores array which is sorted by the frame offset/4
694 * attached to the node
697 pred_sp = be_get_IncSP_pred(irn);
698 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
701 const arch_register_t *sreg, *dreg;
703 /* it has to be a Load */
704 if (!is_ia32_Load(node)) {
705 if (be_is_Copy(node)) {
706 if (!mode_needs_gp_reg(get_irn_mode(node))) {
707 /* not a GP copy, ignore */
710 dreg = arch_get_irn_register(node);
711 sreg = arch_get_irn_register(be_get_Copy_op(node));
712 if (regmask & copymask & (1 << sreg->index)) {
715 if (regmask & copymask & (1 << dreg->index)) {
718 /* we CAN skip Copies if neither the destination nor the source
719 * is not in our regmask, ie none of our future Pop will overwrite it */
720 regmask |= (1 << dreg->index) | (1 << sreg->index);
721 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
727 /* we can handle only GP loads */
728 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
731 /* it has to use our predecessor sp value */
732 if (get_irn_n(node, n_ia32_base) != pred_sp) {
733 /* it would be ok if this load does not use a Pop result,
734 * but we do not check this */
738 /* should have NO index */
739 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
742 offset = get_ia32_am_offs_int(node);
743 /* we should NEVER access uninitialized stack BELOW the current SP */
746 /* storing at half-slots is bad */
747 if ((offset & 3) != 0)
750 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
752 /* ignore those outside the possible windows */
753 if (offset > inc_ofs - 4)
755 loadslot = offset >> 2;
757 /* loading from the same slot twice is bad (and shouldn't happen...) */
758 if (loads[loadslot] != NULL)
761 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
762 if (regmask & (1 << dreg->index)) {
763 /* this register is already used */
766 regmask |= 1 << dreg->index;
768 loads[loadslot] = node;
769 if (loadslot > maxslot)
776 /* find the first slot */
777 for (i = maxslot; i >= 0; --i) {
778 ir_node *load = loads[i];
784 ofs = inc_ofs - (maxslot + 1) * 4;
787 /* create a new IncSP if needed */
788 block = get_nodes_block(irn);
790 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
791 sched_add_before(irn, pred_sp);
794 /* walk through the Loads and create Pops for them */
795 for (++i; i <= maxslot; ++i) {
796 ir_node *load = loads[i];
798 const arch_register_t *reg;
800 mem = get_irn_n(load, n_ia32_mem);
801 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
803 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
804 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
806 copy_mark(load, pop);
808 /* create stackpointer Proj */
809 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
810 arch_set_irn_register(pred_sp, esp);
812 sched_add_before(irn, pop);
815 foreach_out_edge_safe(load, edge) {
816 ir_node *proj = get_edge_src_irn(edge);
818 set_Proj_pred(proj, pop);
821 /* we can remove the Load now */
826 be_set_IncSP_offset(irn, -ofs);
827 be_set_IncSP_pred(irn, pred_sp);
832 * Find a free GP register if possible, else return NULL.
834 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
836 be_irg_t *birg = be_birg_from_irg(irg);
839 for (i = 0; i < N_ia32_gp_REGS; ++i) {
840 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
841 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
844 if (be_peephole_get_value(reg->global_index) == NULL)
852 * Creates a Pop instruction before the given schedule point.
854 * @param dbgi debug info
855 * @param block the block
856 * @param stack the previous stack value
857 * @param schedpoint the new node is added before this node
858 * @param reg the register to pop
860 * @return the new stack value
862 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
863 ir_node *stack, ir_node *schedpoint,
864 const arch_register_t *reg)
866 const arch_register_t *esp = &ia32_registers[REG_ESP];
867 ir_graph *irg = get_irn_irg(block);
873 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
875 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
876 arch_set_irn_register(stack, esp);
877 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
878 arch_set_irn_register(val, reg);
880 sched_add_before(schedpoint, pop);
883 keep = be_new_Keep(block, 1, in);
884 sched_add_before(schedpoint, keep);
890 * Optimize an IncSp by replacing it with Push/Pop.
892 static void peephole_be_IncSP(ir_node *node)
894 const arch_register_t *esp = &ia32_registers[REG_ESP];
895 const arch_register_t *reg;
901 /* first optimize incsp->incsp combinations */
902 node = be_peephole_IncSP_IncSP(node);
904 /* transform IncSP->Store combinations to Push where possible */
905 peephole_IncSP_Store_to_push(node);
907 /* transform Load->IncSP combinations to Pop where possible */
908 peephole_Load_IncSP_to_pop(node);
910 if (arch_get_irn_register(node) != esp)
913 /* replace IncSP -4 by Pop freereg when possible */
914 offset = be_get_IncSP_offset(node);
915 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
916 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
917 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
918 (offset != +8 || ia32_cg_config.use_sub_esp_8))
922 /* we need a free register for pop */
923 reg = get_free_gp_reg(get_irn_irg(node));
927 dbgi = get_irn_dbg_info(node);
928 block = get_nodes_block(node);
929 stack = be_get_IncSP_pred(node);
931 stack = create_pop(dbgi, block, stack, node, reg);
934 stack = create_pop(dbgi, block, stack, node, reg);
937 dbgi = get_irn_dbg_info(node);
938 block = get_nodes_block(node);
939 stack = be_get_IncSP_pred(node);
940 stack = new_bd_ia32_PushEax(dbgi, block, stack);
941 arch_set_irn_register(stack, esp);
942 sched_add_before(node, stack);
945 stack = new_bd_ia32_PushEax(dbgi, block, stack);
946 arch_set_irn_register(stack, esp);
947 sched_add_before(node, stack);
951 be_peephole_exchange(node, stack);
955 * Peephole optimisation for ia32_Const's
957 static void peephole_ia32_Const(ir_node *node)
959 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
960 const arch_register_t *reg;
965 /* try to transform a mov 0, reg to xor reg reg */
966 if (attr->offset != 0 || attr->symconst != NULL)
968 if (ia32_cg_config.use_mov_0)
970 /* xor destroys the flags, so no-one must be using them */
971 if (be_peephole_get_value(REG_EFLAGS) != NULL)
974 reg = arch_get_irn_register(node);
975 assert(be_peephole_get_reg_value(reg) == NULL);
977 /* create xor(produceval, produceval) */
978 block = get_nodes_block(node);
979 dbgi = get_irn_dbg_info(node);
980 xorn = new_bd_ia32_Xor0(dbgi, block);
981 arch_set_irn_register(xorn, reg);
983 sched_add_before(node, xorn);
985 copy_mark(node, xorn);
986 be_peephole_exchange(node, xorn);
989 static inline int is_noreg(const ir_node *node)
991 return is_ia32_NoReg_GP(node);
994 ir_node *ia32_immediate_from_long(long val)
996 ir_graph *irg = current_ir_graph;
997 ir_node *start_block = get_irg_start_block(irg);
999 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
1000 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
1005 static ir_node *create_immediate_from_am(const ir_node *node)
1007 ir_node *block = get_nodes_block(node);
1008 int offset = get_ia32_am_offs_int(node);
1009 int sc_sign = is_ia32_am_sc_sign(node);
1010 const ia32_attr_t *attr = get_ia32_attr_const(node);
1011 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1012 ir_entity *entity = get_ia32_am_sc(node);
1015 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1017 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1021 static int is_am_one(const ir_node *node)
1023 int offset = get_ia32_am_offs_int(node);
1024 ir_entity *entity = get_ia32_am_sc(node);
1026 return offset == 1 && entity == NULL;
1029 static int is_am_minus_one(const ir_node *node)
1031 int offset = get_ia32_am_offs_int(node);
1032 ir_entity *entity = get_ia32_am_sc(node);
1034 return offset == -1 && entity == NULL;
1038 * Transforms a LEA into an Add or SHL if possible.
1040 static void peephole_ia32_Lea(ir_node *node)
1045 const arch_register_t *base_reg;
1046 const arch_register_t *index_reg;
1047 const arch_register_t *out_reg;
1058 assert(is_ia32_Lea(node));
1060 /* we can only do this if it is allowed to clobber the flags */
1061 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1064 base = get_irn_n(node, n_ia32_Lea_base);
1065 index = get_irn_n(node, n_ia32_Lea_index);
1067 if (is_noreg(base)) {
1071 base_reg = arch_get_irn_register(base);
1073 if (is_noreg(index)) {
1077 index_reg = arch_get_irn_register(index);
1080 if (base == NULL && index == NULL) {
1081 /* we shouldn't construct these in the first place... */
1082 #ifdef DEBUG_libfirm
1083 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1088 out_reg = arch_get_irn_register(node);
1089 scale = get_ia32_am_scale(node);
1090 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1091 /* check if we have immediates values (frame entities should already be
1092 * expressed in the offsets) */
1093 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1099 /* we can transform leas where the out register is the same as either the
1100 * base or index register back to an Add or Shl */
1101 if (out_reg == base_reg) {
1102 if (index == NULL) {
1103 #ifdef DEBUG_libfirm
1104 if (!has_immediates) {
1105 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1110 goto make_add_immediate;
1112 if (scale == 0 && !has_immediates) {
1117 /* can't create an add */
1119 } else if (out_reg == index_reg) {
1121 if (has_immediates && scale == 0) {
1123 goto make_add_immediate;
1124 } else if (!has_immediates && scale > 0) {
1126 op2 = ia32_immediate_from_long(scale);
1128 } else if (!has_immediates) {
1129 #ifdef DEBUG_libfirm
1130 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1134 } else if (scale == 0 && !has_immediates) {
1139 /* can't create an add */
1142 /* can't create an add */
1147 if (ia32_cg_config.use_incdec) {
1148 if (is_am_one(node)) {
1149 dbgi = get_irn_dbg_info(node);
1150 block = get_nodes_block(node);
1151 res = new_bd_ia32_Inc(dbgi, block, op1);
1152 arch_set_irn_register(res, out_reg);
1155 if (is_am_minus_one(node)) {
1156 dbgi = get_irn_dbg_info(node);
1157 block = get_nodes_block(node);
1158 res = new_bd_ia32_Dec(dbgi, block, op1);
1159 arch_set_irn_register(res, out_reg);
1163 op2 = create_immediate_from_am(node);
1166 dbgi = get_irn_dbg_info(node);
1167 block = get_nodes_block(node);
1168 irg = get_irn_irg(node);
1169 noreg = ia32_new_NoReg_gp(irg);
1170 nomem = get_irg_no_mem(irg);
1171 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1172 arch_set_irn_register(res, out_reg);
1173 set_ia32_commutative(res);
1177 dbgi = get_irn_dbg_info(node);
1178 block = get_nodes_block(node);
1179 irg = get_irn_irg(node);
1180 noreg = ia32_new_NoReg_gp(irg);
1181 nomem = get_irg_no_mem(irg);
1182 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1183 arch_set_irn_register(res, out_reg);
1187 SET_IA32_ORIG_NODE(res, node);
1189 /* add new ADD/SHL to schedule */
1190 DBG_OPT_LEA2ADD(node, res);
1192 /* exchange the Add and the LEA */
1193 sched_add_before(node, res);
1194 copy_mark(node, res);
1195 be_peephole_exchange(node, res);
1199 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1201 static void peephole_ia32_Imul_split(ir_node *imul)
1203 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1204 const arch_register_t *reg;
1207 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1208 /* no memory, imm form ignore */
1211 /* we need a free register */
1212 reg = get_free_gp_reg(get_irn_irg(imul));
1216 /* fine, we can rebuild it */
1217 res = ia32_turn_back_am(imul);
1218 arch_set_irn_register(res, reg);
1222 * Replace xorps r,r and xorpd r,r by pxor r,r
1224 static void peephole_ia32_xZero(ir_node *xorn)
1226 set_irn_op(xorn, op_ia32_xPzero);
1230 * Replace 16bit sign extension from ax to eax by shorter cwtl
1232 static void peephole_ia32_Conv_I2I(ir_node *node)
1234 const arch_register_t *eax = &ia32_registers[REG_EAX];
1235 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1236 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1241 if (get_mode_size_bits(smaller_mode) != 16 ||
1242 !mode_is_signed(smaller_mode) ||
1243 eax != arch_get_irn_register(val) ||
1244 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1247 dbgi = get_irn_dbg_info(node);
1248 block = get_nodes_block(node);
1249 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1250 arch_set_irn_register(cwtl, eax);
1251 sched_add_before(node, cwtl);
1252 be_peephole_exchange(node, cwtl);
1256 * Register a peephole optimisation function.
1258 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1260 assert(op->ops.generic == NULL);
1261 op->ops.generic = (op_func)func;
1264 /* Perform peephole-optimizations. */
1265 void ia32_peephole_optimization(ir_graph *irg)
1267 /* we currently do it in 2 passes because:
1268 * Lea -> Add could be usefull as flag producer for Test later
1272 ir_clear_opcodes_generic_func();
1273 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1274 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1275 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1276 if (ia32_cg_config.use_short_sex_eax)
1277 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1278 if (ia32_cg_config.use_pxor)
1279 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1280 if (! ia32_cg_config.use_imul_mem_imm32)
1281 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1282 be_peephole_opt(irg);
1285 ir_clear_opcodes_generic_func();
1286 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1287 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1288 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1289 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1290 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1291 be_peephole_opt(irg);
1295 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1296 * all its Projs are removed as well.
1297 * @param irn The irn to be removed from schedule
1299 static inline void try_kill(ir_node *node)
1301 if (get_irn_mode(node) == mode_T) {
1302 foreach_out_edge_safe(node, edge) {
1303 ir_node *proj = get_edge_src_irn(edge);
1308 if (get_irn_n_edges(node) != 0)
1311 if (sched_is_scheduled(node)) {
1318 static void optimize_conv_store(ir_node *node)
1323 ir_mode *store_mode;
1325 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1328 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1329 pred_proj = get_irn_n(node, n_ia32_Store_val);
1330 if (is_Proj(pred_proj)) {
1331 pred = get_Proj_pred(pred_proj);
1335 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1337 if (get_ia32_op_type(pred) != ia32_Normal)
1340 /* the store only stores the lower bits, so we only need the conv
1341 * it it shrinks the mode */
1342 conv_mode = get_ia32_ls_mode(pred);
1343 store_mode = get_ia32_ls_mode(node);
1344 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1347 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1348 if (get_irn_n_edges(pred_proj) == 0) {
1349 kill_node(pred_proj);
1350 if (pred != pred_proj)
1355 static void optimize_load_conv(ir_node *node)
1357 ir_node *pred, *predpred;
1361 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1364 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1365 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1369 predpred = get_Proj_pred(pred);
1370 if (!is_ia32_Load(predpred))
1373 /* the load is sign extending the upper bits, so we only need the conv
1374 * if it shrinks the mode */
1375 load_mode = get_ia32_ls_mode(predpred);
1376 conv_mode = get_ia32_ls_mode(node);
1377 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1380 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1381 /* change the load if it has only 1 user */
1382 if (get_irn_n_edges(pred) == 1) {
1384 if (get_mode_sign(conv_mode)) {
1385 newmode = find_signed_mode(load_mode);
1387 newmode = find_unsigned_mode(load_mode);
1389 assert(newmode != NULL);
1390 set_ia32_ls_mode(predpred, newmode);
1392 /* otherwise we have to keep the conv */
1398 exchange(node, pred);
1401 static void optimize_conv_conv(ir_node *node)
1403 ir_node *pred_proj, *pred, *result_conv;
1404 ir_mode *pred_mode, *conv_mode;
1408 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1411 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1412 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1413 if (is_Proj(pred_proj))
1414 pred = get_Proj_pred(pred_proj);
1418 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1421 /* we know that after a conv, the upper bits are sign extended
1422 * so we only need the 2nd conv if it shrinks the mode */
1423 conv_mode = get_ia32_ls_mode(node);
1424 conv_mode_bits = get_mode_size_bits(conv_mode);
1425 pred_mode = get_ia32_ls_mode(pred);
1426 pred_mode_bits = get_mode_size_bits(pred_mode);
1428 if (conv_mode_bits == pred_mode_bits
1429 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1430 result_conv = pred_proj;
1431 } else if (conv_mode_bits <= pred_mode_bits) {
1432 /* if 2nd conv is smaller then first conv, then we can always take the
1434 if (get_irn_n_edges(pred_proj) == 1) {
1435 result_conv = pred_proj;
1436 set_ia32_ls_mode(pred, conv_mode);
1438 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1439 if (get_mode_size_bits(conv_mode) == 8) {
1440 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1441 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1442 arch_set_irn_register_reqs_in(pred, reqs);
1445 /* we don't want to end up with 2 loads, so we better do nothing */
1446 if (get_irn_mode(pred) == mode_T) {
1450 result_conv = exact_copy(pred);
1451 set_ia32_ls_mode(result_conv, conv_mode);
1453 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1454 if (get_mode_size_bits(conv_mode) == 8) {
1455 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1456 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1457 arch_set_irn_register_reqs_in(result_conv, reqs);
1461 /* if both convs have the same sign, then we can take the smaller one */
1462 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1463 result_conv = pred_proj;
1465 /* no optimisation possible if smaller conv is sign-extend */
1466 if (mode_is_signed(pred_mode)) {
1469 /* we can take the smaller conv if it is unsigned */
1470 result_conv = pred_proj;
1474 /* Some user (like Phis) won't be happy if we change the mode. */
1475 set_irn_mode(result_conv, get_irn_mode(node));
1478 exchange(node, result_conv);
1480 if (get_irn_n_edges(pred_proj) == 0) {
1481 kill_node(pred_proj);
1482 if (pred != pred_proj)
1485 optimize_conv_conv(result_conv);
1488 static void optimize_node(ir_node *node, void *env)
1492 optimize_load_conv(node);
1493 optimize_conv_store(node);
1494 optimize_conv_conv(node);
1498 * Performs conv and address mode optimization.
1500 void ia32_optimize_graph(ir_graph *irg)
1502 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1505 void ia32_init_optimize(void)
1507 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");