2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
32 #include "firm_types.h"
44 #include "../benode_t.h"
45 #include "../besched_t.h"
46 #include "../bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_util.h"
56 #include "ia32_architecture.h"
58 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
60 static ia32_code_gen_t *cg;
62 static void copy_mark(const ir_node *old, ir_node *new)
64 if (is_ia32_is_reload(old))
65 set_ia32_is_reload(new);
66 if (is_ia32_is_spill(old))
67 set_ia32_is_spill(new);
68 if (is_ia32_is_remat(old))
69 set_ia32_is_remat(new);
72 typedef enum produces_flag_t {
79 * Return which usable flag the given node produces
81 * @param node the node to check
82 * @param pn the projection number of the used result
84 static produces_flag_t produces_test_flag(ir_node *node, int pn)
87 const ia32_immediate_attr_t *imm_attr;
89 if (!is_ia32_irn(node))
90 return produces_no_flag;
92 switch (get_ia32_irn_opcode(node)) {
107 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
108 count = get_irn_n(node, n_ia32_ShlD_count);
109 goto check_shift_amount;
114 assert(n_ia32_Shl_count == n_ia32_Shr_count
115 && n_ia32_Shl_count == n_ia32_Sar_count);
116 count = get_irn_n(node, n_ia32_Shl_count);
118 /* when shift count is zero the flags are not affected, so we can only
119 * do this for constants != 0 */
120 if (!is_ia32_Immediate(count))
121 return produces_no_flag;
123 imm_attr = get_ia32_immediate_attr_const(count);
124 if (imm_attr->symconst != NULL)
125 return produces_no_flag;
126 if ((imm_attr->offset & 0x1f) == 0)
127 return produces_no_flag;
131 return pn == pn_ia32_Mul_res_high ?
132 produces_flag_carry : produces_no_flag;
135 return produces_no_flag;
138 return pn == pn_ia32_res ?
139 produces_flag_zero : produces_no_flag;
143 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
145 * @param node the node to change
147 * @return the new mode_T node (if the mode was changed) or node itself
149 static ir_node *turn_into_mode_t(ir_node *node)
154 const arch_register_t *reg;
156 if(get_irn_mode(node) == mode_T)
159 assert(get_irn_mode(node) == mode_Iu);
161 new_node = exact_copy(node);
162 set_irn_mode(new_node, mode_T);
164 block = get_nodes_block(new_node);
165 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
168 reg = arch_get_irn_register(node);
169 arch_set_irn_register(res_proj, reg);
171 sched_add_before(node, new_node);
172 be_peephole_exchange(node, res_proj);
177 * Replace Cmp(x, 0) by a Test(x, x)
179 static void peephole_ia32_Cmp(ir_node *const node)
182 ia32_immediate_attr_t const *imm;
189 ia32_attr_t const *attr;
193 arch_register_t const *reg;
194 ir_edge_t const *edge;
195 ir_edge_t const *tmp;
197 if (get_ia32_op_type(node) != ia32_Normal)
200 right = get_irn_n(node, n_ia32_Cmp_right);
201 if (!is_ia32_Immediate(right))
204 imm = get_ia32_immediate_attr_const(right);
205 if (imm->symconst != NULL || imm->offset != 0)
208 dbgi = get_irn_dbg_info(node);
209 irg = current_ir_graph;
210 block = get_nodes_block(node);
211 noreg = ia32_new_NoReg_gp(cg);
212 nomem = get_irg_no_mem(irg);
213 op = get_irn_n(node, n_ia32_Cmp_left);
214 attr = get_irn_generic_attr(node);
215 ins_permuted = attr->data.ins_permuted;
216 cmp_unsigned = attr->data.cmp_unsigned;
218 if (is_ia32_Cmp(node)) {
219 test = new_rd_ia32_Test(dbgi, irg, block, noreg, noreg, nomem,
220 op, op, ins_permuted, cmp_unsigned);
222 test = new_rd_ia32_Test8Bit(dbgi, irg, block, noreg, noreg, nomem,
223 op, op, ins_permuted, cmp_unsigned);
225 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
227 reg = arch_get_irn_register(node);
228 arch_set_irn_register(test, reg);
230 foreach_out_edge_safe(node, edge, tmp) {
231 ir_node *const user = get_edge_src_irn(edge);
234 exchange(user, test);
237 sched_add_before(node, test);
238 copy_mark(node, test);
239 be_peephole_exchange(node, test);
243 * Peephole optimization for Test instructions.
244 * We can remove the Test, if a zero flags was produced which is still
247 static void peephole_ia32_Test(ir_node *node)
249 ir_node *left = get_irn_n(node, n_ia32_Test_left);
250 ir_node *right = get_irn_n(node, n_ia32_Test_right);
254 int pn = pn_ia32_res;
256 const ir_edge_t *edge;
258 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
259 && n_ia32_Test_right == n_ia32_Test8Bit_right);
261 /* we need a test for 0 */
265 block = get_nodes_block(node);
266 if(get_nodes_block(left) != block)
270 pn = get_Proj_proj(left);
271 left = get_Proj_pred(left);
274 /* happens rarely, but if it does code will panic' */
275 if (is_ia32_Unknown_GP(left))
278 /* walk schedule up and abort when we find left or some other node destroys
282 schedpoint = sched_prev(schedpoint);
283 if (schedpoint == left)
285 if (arch_irn_is(schedpoint, modify_flags))
287 if (schedpoint == block)
288 panic("couldn't find left");
291 /* make sure only Lg/Eq tests are used */
292 foreach_out_edge(node, edge) {
293 ir_node *user = get_edge_src_irn(edge);
294 int pnc = get_ia32_condcode(user);
296 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
301 switch (produces_test_flag(left, pn)) {
302 case produces_flag_zero:
305 case produces_flag_carry:
306 foreach_out_edge(node, edge) {
307 ir_node *user = get_edge_src_irn(edge);
308 int pnc = get_ia32_condcode(user);
311 case pn_Cmp_Eq: pnc = pn_Cmp_Ge | ia32_pn_Cmp_unsigned; break;
312 case pn_Cmp_Lg: pnc = pn_Cmp_Lt | ia32_pn_Cmp_unsigned; break;
313 default: panic("unexpected pn");
315 set_ia32_condcode(user, pnc);
323 left = turn_into_mode_t(left);
325 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
326 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
328 arch_set_irn_register(flags_proj, &ia32_flags_regs[REG_EFLAGS]);
330 assert(get_irn_mode(node) != mode_T);
332 be_peephole_exchange(node, flags_proj);
336 * AMD Athlon works faster when RET is not destination of
337 * conditional jump or directly preceded by other jump instruction.
338 * Can be avoided by placing a Rep prefix before the return.
340 static void peephole_ia32_Return(ir_node *node) {
341 ir_node *block, *irn;
343 if (!ia32_cg_config.use_pad_return)
346 block = get_nodes_block(node);
348 /* check if this return is the first on the block */
349 sched_foreach_reverse_from(node, irn) {
350 switch (get_irn_opcode(irn)) {
352 /* the return node itself, ignore */
357 /* ignore no code generated */
360 /* arg, IncSP 0 nodes might occur, ignore these */
361 if (be_get_IncSP_offset(irn) == 0)
371 /* ensure, that the 3 byte return is generated */
372 be_Return_set_emit_pop(node, 1);
375 /* only optimize up to 48 stores behind IncSPs */
376 #define MAXPUSH_OPTIMIZE 48
379 * Tries to create Push's from IncSP, Store combinations.
380 * The Stores are replaced by Push's, the IncSP is modified
381 * (possibly into IncSP 0, but not removed).
383 static void peephole_IncSP_Store_to_push(ir_node *irn)
389 ir_node *stores[MAXPUSH_OPTIMIZE];
394 ir_node *first_push = NULL;
395 ir_edge_t const *edge;
396 ir_edge_t const *next;
398 memset(stores, 0, sizeof(stores));
400 assert(be_is_IncSP(irn));
402 inc_ofs = be_get_IncSP_offset(irn);
407 * We first walk the schedule after the IncSP node as long as we find
408 * suitable Stores that could be transformed to a Push.
409 * We save them into the stores array which is sorted by the frame offset/4
410 * attached to the node
413 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
418 /* it has to be a Store */
419 if (!is_ia32_Store(node))
422 /* it has to use our sp value */
423 if (get_irn_n(node, n_ia32_base) != irn)
425 /* Store has to be attached to NoMem */
426 mem = get_irn_n(node, n_ia32_mem);
430 /* unfortunately we can't support the full AMs possible for push at the
431 * moment. TODO: fix this */
432 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
435 offset = get_ia32_am_offs_int(node);
436 /* we should NEVER access uninitialized stack BELOW the current SP */
439 /* storing at half-slots is bad */
440 if ((offset & 3) != 0)
443 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
445 storeslot = offset >> 2;
447 /* storing into the same slot twice is bad (and shouldn't happen...) */
448 if (stores[storeslot] != NULL)
451 stores[storeslot] = node;
452 if (storeslot > maxslot)
458 for (i = -1; i < maxslot; ++i) {
459 if (stores[i + 1] == NULL)
463 /* walk through the Stores and create Pushs for them */
464 block = get_nodes_block(irn);
465 spmode = get_irn_mode(irn);
467 for (; i >= 0; --i) {
468 const arch_register_t *spreg;
470 ir_node *val, *mem, *mem_proj;
471 ir_node *store = stores[i];
472 ir_node *noreg = ia32_new_NoReg_gp(cg);
474 val = get_irn_n(store, n_ia32_unary_op);
475 mem = get_irn_n(store, n_ia32_mem);
476 spreg = arch_get_irn_register(curr_sp);
478 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
479 copy_mark(store, push);
481 if (first_push == NULL)
484 sched_add_after(curr_sp, push);
486 /* create stackpointer Proj */
487 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
488 arch_set_irn_register(curr_sp, spreg);
490 /* create memory Proj */
491 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
493 /* use the memproj now */
494 be_peephole_exchange(store, mem_proj);
499 foreach_out_edge_safe(irn, edge, next) {
500 ir_node *const src = get_edge_src_irn(edge);
501 int const pos = get_edge_src_pos(edge);
503 if (src == first_push)
506 set_irn_n(src, pos, curr_sp);
509 be_set_IncSP_offset(irn, inc_ofs);
513 static void peephole_store_incsp(ir_node *store)
522 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
523 if (!be_is_IncSP(am_base)
524 || get_nodes_block(am_base) != get_nodes_block(store))
526 mem = get_irn_n(store, n_ia32_Store_mem);
527 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
531 int incsp_offset = be_get_IncSP_offset(am_base);
532 if (incsp_offset <= 0)
535 /* we have to be at offset 0 */
536 int my_offset = get_ia32_am_offs_int(store);
537 if (my_offset != 0) {
538 /* TODO here: find out wether there is a store with offset 0 before
539 * us and wether we can move it down to our place */
542 ir_mode *ls_mode = get_ia32_ls_mode(store);
543 int my_store_size = get_mode_size_bytes(ls_mode);
545 if (my_offset + my_store_size > incsp_offset)
548 /* correctness checking:
549 - noone else must write to that stackslot
550 (because after translation incsp won't allocate it anymore)
552 sched_foreach_reverse_from(store, node) {
558 /* make sure noone else can use the space on the stack */
559 arity = get_irn_arity(node);
560 for (i = 0; i < arity; ++i) {
561 ir_node *pred = get_irn_n(node, i);
565 if (i == n_ia32_base &&
566 (get_ia32_op_type(node) == ia32_AddrModeS
567 || get_ia32_op_type(node) == ia32_AddrModeD)) {
568 int node_offset = get_ia32_am_offs_int(node);
569 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
570 int node_size = get_mode_size_bytes(node);
571 /* overlapping with our position? abort */
572 if (node_offset < my_offset + my_store_size
573 && node_offset + node_size >= my_offset)
575 /* otherwise it's fine */
579 /* strange use of esp: abort */
584 /* all ok, change to push */
585 dbgi = get_irn_dbg_info(store);
586 block = get_nodes_block(store);
587 noreg = ia32_new_NoReg_gp(cg);
590 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem,
592 create_push(dbgi, current_ir_graph, block, am_base, store);
597 * Return true if a mode can be stored in the GP register set
599 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
600 if (mode == mode_fpcw)
602 if (get_mode_size_bits(mode) > 32)
604 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
608 * Tries to create Pops from Load, IncSP combinations.
609 * The Loads are replaced by Pops, the IncSP is modified
610 * (possibly into IncSP 0, but not removed).
612 static void peephole_Load_IncSP_to_pop(ir_node *irn)
614 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
615 int i, maxslot, inc_ofs, ofs;
616 ir_node *node, *pred_sp, *block;
617 ir_node *loads[MAXPUSH_OPTIMIZE];
619 unsigned regmask = 0;
620 unsigned copymask = ~0;
622 memset(loads, 0, sizeof(loads));
623 assert(be_is_IncSP(irn));
625 inc_ofs = -be_get_IncSP_offset(irn);
630 * We first walk the schedule before the IncSP node as long as we find
631 * suitable Loads that could be transformed to a Pop.
632 * We save them into the stores array which is sorted by the frame offset/4
633 * attached to the node
636 pred_sp = be_get_IncSP_pred(irn);
637 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
640 const arch_register_t *sreg, *dreg;
642 /* it has to be a Load */
643 if (!is_ia32_Load(node)) {
644 if (be_is_Copy(node)) {
645 if (!mode_needs_gp_reg(get_irn_mode(node))) {
646 /* not a GP copy, ignore */
649 dreg = arch_get_irn_register(node);
650 sreg = arch_get_irn_register(be_get_Copy_op(node));
651 if (regmask & copymask & (1 << sreg->index)) {
654 if (regmask & copymask & (1 << dreg->index)) {
657 /* we CAN skip Copies if neither the destination nor the source
658 * is not in our regmask, ie none of our future Pop will overwrite it */
659 regmask |= (1 << dreg->index) | (1 << sreg->index);
660 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
666 /* we can handle only GP loads */
667 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
670 /* it has to use our predecessor sp value */
671 if (get_irn_n(node, n_ia32_base) != pred_sp) {
672 /* it would be ok if this load does not use a Pop result,
673 * but we do not check this */
677 /* should have NO index */
678 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
681 offset = get_ia32_am_offs_int(node);
682 /* we should NEVER access uninitialized stack BELOW the current SP */
685 /* storing at half-slots is bad */
686 if ((offset & 3) != 0)
689 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
691 /* ignore those outside the possible windows */
692 if (offset > inc_ofs - 4)
694 loadslot = offset >> 2;
696 /* loading from the same slot twice is bad (and shouldn't happen...) */
697 if (loads[loadslot] != NULL)
700 dreg = arch_get_irn_register(node);
701 if (regmask & (1 << dreg->index)) {
702 /* this register is already used */
705 regmask |= 1 << dreg->index;
707 loads[loadslot] = node;
708 if (loadslot > maxslot)
715 /* find the first slot */
716 for (i = maxslot; i >= 0; --i) {
717 ir_node *load = loads[i];
723 ofs = inc_ofs - (maxslot + 1) * 4;
726 /* create a new IncSP if needed */
727 block = get_nodes_block(irn);
730 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
731 sched_add_before(irn, pred_sp);
734 /* walk through the Loads and create Pops for them */
735 for (++i; i <= maxslot; ++i) {
736 ir_node *load = loads[i];
738 const ir_edge_t *edge, *tmp;
739 const arch_register_t *reg;
741 mem = get_irn_n(load, n_ia32_mem);
742 reg = arch_get_irn_register(load);
744 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
745 arch_set_irn_register(pop, reg);
747 copy_mark(load, pop);
749 /* create stackpointer Proj */
750 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
751 arch_set_irn_register(pred_sp, esp);
753 sched_add_before(irn, pop);
756 foreach_out_edge_safe(load, edge, tmp) {
757 ir_node *proj = get_edge_src_irn(edge);
759 set_Proj_pred(proj, pop);
762 /* we can remove the Load now */
767 be_set_IncSP_offset(irn, -ofs);
768 be_set_IncSP_pred(irn, pred_sp);
773 * Find a free GP register if possible, else return NULL.
775 static const arch_register_t *get_free_gp_reg(void)
779 for(i = 0; i < N_ia32_gp_REGS; ++i) {
780 const arch_register_t *reg = &ia32_gp_regs[i];
781 if(arch_register_type_is(reg, ignore))
784 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
785 return &ia32_gp_regs[i];
792 * Creates a Pop instruction before the given schedule point.
794 * @param dbgi debug info
795 * @param irg the graph
796 * @param block the block
797 * @param stack the previous stack value
798 * @param schedpoint the new node is added before this node
799 * @param reg the register to pop
801 * @return the new stack value
803 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
804 ir_node *stack, ir_node *schedpoint,
805 const arch_register_t *reg)
807 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
813 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
815 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
816 arch_set_irn_register(stack, esp);
817 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
818 arch_set_irn_register(val, reg);
820 sched_add_before(schedpoint, pop);
823 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
824 sched_add_before(schedpoint, keep);
830 * Creates a Push instruction before the given schedule point.
832 * @param dbgi debug info
833 * @param irg the graph
834 * @param block the block
835 * @param stack the previous stack value
836 * @param schedpoint the new node is added before this node
837 * @param reg the register to pop
839 * @return the new stack value
841 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
842 ir_node *stack, ir_node *schedpoint)
844 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
846 ir_node *val = ia32_new_Unknown_gp(cg);
847 ir_node *noreg = ia32_new_NoReg_gp(cg);
848 ir_node *nomem = get_irg_no_mem(irg);
849 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
850 sched_add_before(schedpoint, push);
852 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
853 arch_set_irn_register(stack, esp);
859 * Optimize an IncSp by replacing it with Push/Pop.
861 static void peephole_be_IncSP(ir_node *node)
863 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
864 const arch_register_t *reg;
865 ir_graph *irg = current_ir_graph;
871 /* first optimize incsp->incsp combinations */
872 node = be_peephole_IncSP_IncSP(node);
874 /* transform IncSP->Store combinations to Push where possible */
875 peephole_IncSP_Store_to_push(node);
877 /* transform Load->IncSP combinations to Pop where possible */
878 peephole_Load_IncSP_to_pop(node);
880 if (arch_get_irn_register(node) != esp)
883 /* replace IncSP -4 by Pop freereg when possible */
884 offset = be_get_IncSP_offset(node);
885 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
886 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
887 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
888 (offset != +8 || ia32_cg_config.use_sub_esp_8))
892 /* we need a free register for pop */
893 reg = get_free_gp_reg();
897 dbgi = get_irn_dbg_info(node);
898 block = get_nodes_block(node);
899 stack = be_get_IncSP_pred(node);
901 stack = create_pop(dbgi, irg, block, stack, node, reg);
904 stack = create_pop(dbgi, irg, block, stack, node, reg);
907 dbgi = get_irn_dbg_info(node);
908 block = get_nodes_block(node);
909 stack = be_get_IncSP_pred(node);
910 stack = create_push(dbgi, irg, block, stack, node);
913 stack = create_push(dbgi, irg, block, stack, node);
917 be_peephole_exchange(node, stack);
921 * Peephole optimisation for ia32_Const's
923 static void peephole_ia32_Const(ir_node *node)
925 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
926 const arch_register_t *reg;
927 ir_graph *irg = current_ir_graph;
934 /* try to transform a mov 0, reg to xor reg reg */
935 if (attr->offset != 0 || attr->symconst != NULL)
937 if (ia32_cg_config.use_mov_0)
939 /* xor destroys the flags, so no-one must be using them */
940 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
943 reg = arch_get_irn_register(node);
944 assert(be_peephole_get_reg_value(reg) == NULL);
946 /* create xor(produceval, produceval) */
947 block = get_nodes_block(node);
948 dbgi = get_irn_dbg_info(node);
949 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
950 arch_set_irn_register(produceval, reg);
952 noreg = ia32_new_NoReg_gp(cg);
953 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
954 produceval, produceval);
955 arch_set_irn_register(xor, reg);
957 sched_add_before(node, produceval);
958 sched_add_before(node, xor);
960 copy_mark(node, xor);
961 be_peephole_exchange(node, xor);
964 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
966 return node == cg->noreg_gp;
969 static ir_node *create_immediate_from_int(int val)
971 ir_graph *irg = current_ir_graph;
972 ir_node *start_block = get_irg_start_block(irg);
973 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
975 arch_set_irn_register(immediate, &ia32_gp_regs[REG_GP_NOREG]);
980 static ir_node *create_immediate_from_am(const ir_node *node)
982 ir_graph *irg = get_irn_irg(node);
983 ir_node *block = get_nodes_block(node);
984 int offset = get_ia32_am_offs_int(node);
985 int sc_sign = is_ia32_am_sc_sign(node);
986 ir_entity *entity = get_ia32_am_sc(node);
989 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
990 arch_set_irn_register(res, &ia32_gp_regs[REG_GP_NOREG]);
994 static int is_am_one(const ir_node *node)
996 int offset = get_ia32_am_offs_int(node);
997 ir_entity *entity = get_ia32_am_sc(node);
999 return offset == 1 && entity == NULL;
1002 static int is_am_minus_one(const ir_node *node)
1004 int offset = get_ia32_am_offs_int(node);
1005 ir_entity *entity = get_ia32_am_sc(node);
1007 return offset == -1 && entity == NULL;
1011 * Transforms a LEA into an Add or SHL if possible.
1013 static void peephole_ia32_Lea(ir_node *node)
1015 ir_graph *irg = current_ir_graph;
1018 const arch_register_t *base_reg;
1019 const arch_register_t *index_reg;
1020 const arch_register_t *out_reg;
1031 assert(is_ia32_Lea(node));
1033 /* we can only do this if are allowed to globber the flags */
1034 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
1037 base = get_irn_n(node, n_ia32_Lea_base);
1038 index = get_irn_n(node, n_ia32_Lea_index);
1040 if(is_noreg(cg, base)) {
1044 base_reg = arch_get_irn_register(base);
1046 if(is_noreg(cg, index)) {
1050 index_reg = arch_get_irn_register(index);
1053 if(base == NULL && index == NULL) {
1054 /* we shouldn't construct these in the first place... */
1055 #ifdef DEBUG_libfirm
1056 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1061 out_reg = arch_get_irn_register(node);
1062 scale = get_ia32_am_scale(node);
1063 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1064 /* check if we have immediates values (frame entities should already be
1065 * expressed in the offsets) */
1066 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1072 /* we can transform leas where the out register is the same as either the
1073 * base or index register back to an Add or Shl */
1074 if(out_reg == base_reg) {
1076 #ifdef DEBUG_libfirm
1077 if(!has_immediates) {
1078 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1083 goto make_add_immediate;
1085 if(scale == 0 && !has_immediates) {
1090 /* can't create an add */
1092 } else if(out_reg == index_reg) {
1094 if(has_immediates && scale == 0) {
1096 goto make_add_immediate;
1097 } else if(!has_immediates && scale > 0) {
1099 op2 = create_immediate_from_int(scale);
1101 } else if(!has_immediates) {
1102 #ifdef DEBUG_libfirm
1103 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1107 } else if(scale == 0 && !has_immediates) {
1112 /* can't create an add */
1115 /* can't create an add */
1120 if(ia32_cg_config.use_incdec) {
1121 if(is_am_one(node)) {
1122 dbgi = get_irn_dbg_info(node);
1123 block = get_nodes_block(node);
1124 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
1125 arch_set_irn_register(res, out_reg);
1128 if(is_am_minus_one(node)) {
1129 dbgi = get_irn_dbg_info(node);
1130 block = get_nodes_block(node);
1131 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
1132 arch_set_irn_register(res, out_reg);
1136 op2 = create_immediate_from_am(node);
1139 dbgi = get_irn_dbg_info(node);
1140 block = get_nodes_block(node);
1141 noreg = ia32_new_NoReg_gp(cg);
1142 nomem = new_NoMem();
1143 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
1144 arch_set_irn_register(res, out_reg);
1145 set_ia32_commutative(res);
1149 dbgi = get_irn_dbg_info(node);
1150 block = get_nodes_block(node);
1151 noreg = ia32_new_NoReg_gp(cg);
1152 nomem = new_NoMem();
1153 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
1154 arch_set_irn_register(res, out_reg);
1158 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
1160 /* add new ADD/SHL to schedule */
1161 DBG_OPT_LEA2ADD(node, res);
1163 /* exchange the Add and the LEA */
1164 sched_add_before(node, res);
1165 copy_mark(node, res);
1166 be_peephole_exchange(node, res);
1170 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1172 static void peephole_ia32_Imul_split(ir_node *imul)
1174 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1175 const arch_register_t *reg;
1178 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1179 /* no memory, imm form ignore */
1182 /* we need a free register */
1183 reg = get_free_gp_reg();
1187 /* fine, we can rebuild it */
1188 res = turn_back_am(imul);
1189 arch_set_irn_register(res, reg);
1193 * Replace xorps r,r and xorpd r,r by pxor r,r
1195 static void peephole_ia32_xZero(ir_node *xor) {
1196 set_irn_op(xor, op_ia32_xPzero);
1200 * Register a peephole optimisation function.
1202 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1203 assert(op->ops.generic == NULL);
1204 op->ops.generic = (op_func)func;
1207 /* Perform peephole-optimizations. */
1208 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1212 /* register peephole optimisations */
1213 clear_irp_opcodes_generic_func();
1214 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1215 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1216 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1217 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1218 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1219 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1220 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1221 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1222 if (! ia32_cg_config.use_imul_mem_imm32)
1223 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1224 if (ia32_cg_config.use_pxor)
1225 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1227 be_peephole_opt(cg->birg);
1231 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1232 * all it's Projs are removed as well.
1233 * @param irn The irn to be removed from schedule
1235 static INLINE void try_kill(ir_node *node)
1237 if(get_irn_mode(node) == mode_T) {
1238 const ir_edge_t *edge, *next;
1239 foreach_out_edge_safe(node, edge, next) {
1240 ir_node *proj = get_edge_src_irn(edge);
1245 if(get_irn_n_edges(node) != 0)
1248 if (sched_is_scheduled(node)) {
1255 static void optimize_conv_store(ir_node *node)
1260 ir_mode *store_mode;
1262 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1265 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1266 pred_proj = get_irn_n(node, n_ia32_Store_val);
1267 if(is_Proj(pred_proj)) {
1268 pred = get_Proj_pred(pred_proj);
1272 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1274 if(get_ia32_op_type(pred) != ia32_Normal)
1277 /* the store only stores the lower bits, so we only need the conv
1278 * it it shrinks the mode */
1279 conv_mode = get_ia32_ls_mode(pred);
1280 store_mode = get_ia32_ls_mode(node);
1281 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1284 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1285 if(get_irn_n_edges(pred_proj) == 0) {
1286 kill_node(pred_proj);
1287 if(pred != pred_proj)
1292 static void optimize_load_conv(ir_node *node)
1294 ir_node *pred, *predpred;
1298 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1301 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1302 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1306 predpred = get_Proj_pred(pred);
1307 if(!is_ia32_Load(predpred))
1310 /* the load is sign extending the upper bits, so we only need the conv
1311 * if it shrinks the mode */
1312 load_mode = get_ia32_ls_mode(predpred);
1313 conv_mode = get_ia32_ls_mode(node);
1314 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1317 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1318 /* change the load if it has only 1 user */
1319 if(get_irn_n_edges(pred) == 1) {
1321 if(get_mode_sign(conv_mode)) {
1322 newmode = find_signed_mode(load_mode);
1324 newmode = find_unsigned_mode(load_mode);
1326 assert(newmode != NULL);
1327 set_ia32_ls_mode(predpred, newmode);
1329 /* otherwise we have to keep the conv */
1335 exchange(node, pred);
1338 static void optimize_conv_conv(ir_node *node)
1340 ir_node *pred_proj, *pred, *result_conv;
1341 ir_mode *pred_mode, *conv_mode;
1345 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1348 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1349 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1350 if(is_Proj(pred_proj))
1351 pred = get_Proj_pred(pred_proj);
1355 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1358 /* we know that after a conv, the upper bits are sign extended
1359 * so we only need the 2nd conv if it shrinks the mode */
1360 conv_mode = get_ia32_ls_mode(node);
1361 conv_mode_bits = get_mode_size_bits(conv_mode);
1362 pred_mode = get_ia32_ls_mode(pred);
1363 pred_mode_bits = get_mode_size_bits(pred_mode);
1365 if(conv_mode_bits == pred_mode_bits
1366 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1367 result_conv = pred_proj;
1368 } else if(conv_mode_bits <= pred_mode_bits) {
1369 /* if 2nd conv is smaller then first conv, then we can always take the
1371 if(get_irn_n_edges(pred_proj) == 1) {
1372 result_conv = pred_proj;
1373 set_ia32_ls_mode(pred, conv_mode);
1375 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1376 if (get_mode_size_bits(conv_mode) == 8) {
1377 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1378 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1381 /* we don't want to end up with 2 loads, so we better do nothing */
1382 if(get_irn_mode(pred) == mode_T) {
1386 result_conv = exact_copy(pred);
1387 set_ia32_ls_mode(result_conv, conv_mode);
1389 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1390 if (get_mode_size_bits(conv_mode) == 8) {
1391 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1392 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1396 /* if both convs have the same sign, then we can take the smaller one */
1397 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1398 result_conv = pred_proj;
1400 /* no optimisation possible if smaller conv is sign-extend */
1401 if(mode_is_signed(pred_mode)) {
1404 /* we can take the smaller conv if it is unsigned */
1405 result_conv = pred_proj;
1410 exchange(node, result_conv);
1412 if(get_irn_n_edges(pred_proj) == 0) {
1413 kill_node(pred_proj);
1414 if(pred != pred_proj)
1417 optimize_conv_conv(result_conv);
1420 static void optimize_node(ir_node *node, void *env)
1424 optimize_load_conv(node);
1425 optimize_conv_store(node);
1426 optimize_conv_conv(node);
1430 * Performs conv and address mode optimization.
1432 void ia32_optimize_graph(ia32_code_gen_t *cg)
1434 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1437 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1440 void ia32_init_optimize(void)
1442 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");