8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
25 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
27 typedef int is_op_func_t(const ir_node *n);
30 * checks if a node represents the NOREG value
32 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
33 be_abi_irg_t *babi = cg->birg->abi;
34 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
35 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
37 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
38 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
43 /*************************************************
46 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
47 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
48 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
49 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
51 *************************************************/
54 * creates a unique ident by adding a number to a tag
56 * @param tag the tag string, must contain a %d if a number
59 static ident *unique_id(const char *tag)
61 static unsigned id = 0;
64 snprintf(str, sizeof(str), tag, ++id);
65 return new_id_from_str(str);
71 * Transforms a SymConst.
73 * @param mod the debug module
74 * @param block the block the new node should belong to
75 * @param node the ir SymConst node
76 * @param mode mode of the SymConst
77 * @return the created ia32 Const node
79 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
81 dbg_info *dbg = env->dbg;
82 ir_mode *mode = env->mode;
83 ir_graph *irg = env->irg;
84 ir_node *block = env->block;
86 if (mode_is_float(mode)) {
88 if (USE_SSE2(env->cg))
89 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
91 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
94 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
95 set_ia32_Const_attr(cnst, env->irn);
100 * Get a primitive type for a mode.
102 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
104 pmap_entry *e = pmap_find(types, mode);
109 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
110 res = new_type_primitive(new_id_from_str(buf), mode);
111 pmap_insert(types, mode, res);
119 * Get an entity that is initialized with a tarval
121 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
123 tarval *tv = get_Const_tarval(cnst);
124 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
129 ir_mode *mode = get_irn_mode(cnst);
130 ir_type *tp = get_Const_type(cnst);
131 if (tp == firm_unknown_type)
132 tp = get_prim_type(cg->isa->types, mode);
134 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
136 set_entity_ld_ident(res, get_entity_ident(res));
137 set_entity_visibility(res, visibility_local);
138 set_entity_variability(res, variability_constant);
139 set_entity_allocation(res, allocation_static);
141 /* we create a new entity here: It's initialization must resist on the
143 rem = current_ir_graph;
144 current_ir_graph = get_const_code_irg();
145 set_atomic_ent_value(res, new_Const_type(tv, tp));
146 current_ir_graph = rem;
148 pmap_insert(cg->isa->tv_ent, tv, res);
156 * Transforms a Const.
158 * @param mod the debug module
159 * @param block the block the new node should belong to
160 * @param node the ir Const node
161 * @param mode mode of the Const
162 * @return the created ia32 Const node
164 static ir_node *gen_Const(ia32_transform_env_t *env) {
167 ir_graph *irg = env->irg;
168 ir_node *block = env->block;
169 ir_node *node = env->irn;
170 dbg_info *dbg = env->dbg;
171 ir_mode *mode = env->mode;
173 if (mode_is_float(mode)) {
175 if (! USE_SSE2(env->cg)) {
176 cnst_classify_t clss = classify_Const(node);
178 if (clss == CNST_NULL)
179 return new_rd_ia32_vfldz(dbg, irg, block, mode);
180 else if (clss == CNST_ONE)
181 return new_rd_ia32_vfld1(dbg, irg, block, mode);
183 sym.entity_p = get_entity_for_tv(env->cg, node);
185 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
187 cnst = gen_SymConst(env);
190 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
191 set_ia32_Const_attr(cnst, node);
199 * Transforms (all) Const's into ia32_Const and places them in the
200 * block where they are used (or in the cfg-pred Block in case of Phi's).
201 * Additionally all reference nodes are changed into mode_Is nodes.
203 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
204 ia32_code_gen_t *cg = env;
205 ia32_transform_env_t tenv;
207 ir_node *pred, *cnst;
214 mode = get_irn_mode(irn);
216 /* transform all reference nodes into mode_Is nodes */
217 if (mode_is_reference(mode)) {
219 set_irn_mode(irn, mode);
222 tenv.block = get_nodes_block(irn);
225 DEBUG_ONLY(tenv.mod = cg->mod;)
227 /* Loop over all predecessors and check for Sym/Const nodes */
228 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
229 pred = get_irn_n(irn, i);
231 opc = get_irn_opcode(pred);
233 tenv.mode = get_irn_mode(pred);
234 tenv.dbg = get_irn_dbg_info(pred);
236 /* If it's a Phi, then we need to create the */
237 /* new Const in it's predecessor block */
239 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
242 /* put the const into the block where the original const was */
243 if (! (cg->opt & IA32_OPT_PLACECNST)) {
244 tenv.block = get_nodes_block(pred);
249 cnst = gen_Const(&tenv);
252 cnst = gen_SymConst(&tenv);
258 /* if we found a const, then set it */
260 set_irn_n(irn, i, cnst);
267 /********************************************************************************************************
268 * _____ _ _ ____ _ _ _ _ _
269 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
270 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
271 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
272 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
273 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
276 ********************************************************************************************************/
279 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
282 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
283 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
287 * Checks for potential CJmp/CJmpAM optimization candidates.
289 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
290 ir_node *cand = NULL;
291 ir_node *prev = sched_prev(irn);
293 if (is_Block(prev)) {
294 if (get_Block_n_cfgpreds(prev) == 1)
295 prev = get_Block_cfgpred(prev, 0);
300 /* The predecessor must be a ProjX. */
301 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
302 prev = get_Proj_pred(prev);
304 if (is_op_func(prev))
311 static int is_TestJmp_cand(const ir_node *irn) {
312 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
316 * Checks if two consecutive arguments of cand matches
317 * the two arguments of irn (TestJmp).
319 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
320 ir_node *in1 = get_irn_n(irn, 0);
321 ir_node *in2 = get_irn_n(irn, 1);
322 int i, n = get_irn_arity(cand);
325 for (i = 0; i < n - 1; i++) {
326 if (get_irn_n(cand, i) == in1 &&
327 get_irn_n(cand, i + 1) == in2)
335 return ia32_cnst_compare(cand, irn);
341 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
343 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
344 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
347 /* we found a possible candidate */
348 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
351 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
353 if (is_ia32_And(cand))
354 set_irn_op(irn, op_ia32_CJmpAM);
356 set_irn_op(irn, op_ia32_CJmp);
358 DB((cg->mod, LEVEL_1, "%+F\n", irn));
362 static int is_CondJmp_cand(const ir_node *irn) {
363 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
367 * Checks if the arguments of cand are the same of irn.
369 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
370 int i, n = get_irn_arity(cand);
373 for (i = 0; i < n; i++) {
374 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
381 return ia32_cnst_compare(cand, irn);
387 * Tries to replace a CondJmp by a CJmpAM
389 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
390 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
393 /* we found a possible candidate */
394 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
397 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
400 set_irn_op(irn, op_ia32_CJmp);
402 DB((cg->mod, LEVEL_1, "%+F\n", irn));
407 * Creates a Push from Store(IncSP(gp_reg_size))
409 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
410 ir_node *sp = get_irn_n(irn, 0);
411 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
412 const ir_edge_t *edge;
414 if (get_ia32_am_offs(irn) || !be_is_IncSP(sp))
417 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
418 &ia32_gp_regs[REG_GP_NOREG])
421 val = get_irn_n(irn, 2);
422 if (mode_is_float(get_irn_mode(val)))
425 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
426 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
429 /* ok, translate into Push */
430 edge = get_irn_out_edge_first(irn);
431 old_proj_M = get_edge_src_irn(edge);
433 next = sched_next(irn);
437 bl = get_nodes_block(irn);
438 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
439 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
440 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
441 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
443 /* the push must have SP out register */
444 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
446 exchange(old_proj_M, proj_M);
447 exchange(sp, proj_res);
448 sched_add_before(next, push);
449 sched_add_after(push, proj_res);
453 * Creates a Pop from IncSP(Load(sp))
455 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
456 ir_node *old_proj_M = be_get_IncSP_mem(irn);
457 ir_node *load = skip_Proj(old_proj_M);
458 ir_node *old_proj_res = NULL;
459 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
460 const ir_edge_t *edge;
461 const arch_register_t *reg, *sp;
463 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
466 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
467 &ia32_gp_regs[REG_GP_NOREG])
469 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
472 /* ok, translate into pop */
473 foreach_out_edge(load, edge) {
474 ir_node *succ = get_edge_src_irn(edge);
475 if (succ != old_proj_M) {
480 if (! old_proj_res) {
482 return; /* should not happen */
485 bl = get_nodes_block(load);
487 /* IncSP is typically scheduled after the load, so remove it first */
489 next = sched_next(old_proj_res);
490 sched_remove(old_proj_res);
493 reg = arch_get_irn_register(cg->arch_env, load);
494 sp = arch_get_irn_register(cg->arch_env, irn);
496 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
497 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
498 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
499 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
501 exchange(old_proj_M, proj_M);
502 exchange(old_proj_res, proj_res);
503 exchange(irn, proj_sp);
505 arch_set_irn_register(cg->arch_env, proj_res, reg);
506 arch_set_irn_register(cg->arch_env, proj_sp, sp);
508 sched_add_before(next, proj_sp);
509 sched_add_before(proj_sp, proj_res);
510 sched_add_before(proj_res,pop);
516 * Tries to optimize two following IncSP.
518 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
519 ir_node *prev = be_get_IncSP_pred(irn);
520 int real_uses = get_irn_n_edges(prev);
522 if (be_is_IncSP(prev) && real_uses == 1) {
523 /* first IncSP has only one IncSP user, kill the first one */
524 unsigned prev_offs = be_get_IncSP_offset(prev);
525 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
526 unsigned curr_offs = be_get_IncSP_offset(irn);
527 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
529 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
530 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
534 curr_dir = be_stack_dir_expand;
537 curr_dir = be_stack_dir_shrink;
538 be_set_IncSP_offset(prev, 0);
539 be_set_IncSP_offset(irn, (unsigned)new_ofs);
540 be_set_IncSP_direction(irn, curr_dir);
542 /* Omit the optimized IncSP */
543 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
548 * Performs Peephole Optimizations.
550 void ia32_peephole_optimization(ir_node *irn, void *env) {
551 ia32_code_gen_t *cg = env;
553 if (is_ia32_TestJmp(irn))
554 ia32_optimize_TestJmp(irn, cg);
555 else if (is_ia32_CondJmp(irn))
556 ia32_optimize_CondJmp(irn, cg);
557 else if (be_is_IncSP(irn))
558 ia32_optimize_IncSP(irn, cg);
563 /******************************************************************
565 * /\ | | | | | \/ | | |
566 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
567 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
568 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
569 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
571 ******************************************************************/
573 static int node_is_ia32_comm(const ir_node *irn) {
574 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
577 static int ia32_get_irn_n_edges(const ir_node *irn) {
578 const ir_edge_t *edge;
581 foreach_out_edge(irn, edge) {
589 * Returns the first mode_M Proj connected to irn.
591 static ir_node *get_mem_proj(const ir_node *irn) {
592 const ir_edge_t *edge;
595 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
597 foreach_out_edge(irn, edge) {
598 src = get_edge_src_irn(edge);
600 assert(is_Proj(src) && "Proj expected");
602 if (get_irn_mode(src) == mode_M)
610 * Returns the first Proj with mode != mode_M connected to irn.
612 static ir_node *get_res_proj(const ir_node *irn) {
613 const ir_edge_t *edge;
616 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
618 foreach_out_edge(irn, edge) {
619 src = get_edge_src_irn(edge);
621 assert(is_Proj(src) && "Proj expected");
623 if (get_irn_mode(src) != mode_M)
631 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
633 * @param pred The node to be checked
634 * @param is_op_func The check-function
635 * @return 1 if conditions are fulfilled, 0 otherwise
637 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
638 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
646 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
647 * and if the predecessor is in block bl.
649 * @param bl The block
650 * @param pred The node to be checked
651 * @param is_op_func The check-function
652 * @return 1 if conditions are fulfilled, 0 otherwise
654 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
655 int (*is_op_func)(const ir_node *n))
658 pred = get_Proj_pred(pred);
659 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
670 * Checks if irn is a candidate for address calculation or address mode.
672 * address calculation (AC):
673 * - none of the operand must be a Load within the same block OR
674 * - all Loads must have more than one user OR
675 * - the irn has a frame entity (it's a former FrameAddr)
678 * - at least one operand has to be a Load within the same block AND
679 * - the load must not have other users than the irn AND
680 * - the irn must not have a frame entity set
682 * @param block The block the Loads must/not be in
683 * @param irn The irn to check
684 * @param check_addr 1 if to check for address calculation, 0 otherwise
685 * return 1 if irn is a candidate for AC or AM, 0 otherwise
687 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
689 int n, is_cand = check_addr;
691 in = get_irn_n(irn, 2);
693 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
694 n = ia32_get_irn_n_edges(in);
695 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
698 in = get_irn_n(irn, 3);
700 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
701 n = ia32_get_irn_n_edges(in);
702 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
705 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
711 * Compares the base and index addr and the load/store entities
712 * and returns 1 if they are equal.
714 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
715 const ir_node *addr_b, const ir_node *addr_i)
717 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
718 entity *lent = get_ia32_frame_ent(load);
719 entity *sent = get_ia32_frame_ent(store);
720 ident *lid = get_ia32_am_sc(load);
721 ident *sid = get_ia32_am_sc(store);
722 char *loffs = get_ia32_am_offs(load);
723 char *soffs = get_ia32_am_offs(store);
725 /* are both entities set and equal? */
726 if (is_equal && (lent || sent))
727 is_equal = lent && sent && (lent == sent);
729 /* are address mode idents set and equal? */
730 if (is_equal && (lid || sid))
731 is_equal = lid && sid && (lid == sid);
733 /* are offsets set and equal */
734 if (is_equal && (loffs || soffs))
735 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
737 /* are the load and the store of the same mode? */
738 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
743 typedef enum _ia32_take_lea_attr {
744 IA32_LEA_ATTR_NONE = 0,
745 IA32_LEA_ATTR_BASE = (1 << 0),
746 IA32_LEA_ATTR_INDEX = (1 << 1),
747 IA32_LEA_ATTR_OFFS = (1 << 2),
748 IA32_LEA_ATTR_SCALE = (1 << 3),
749 IA32_LEA_ATTR_AMSC = (1 << 4),
750 IA32_LEA_ATTR_FENT = (1 << 5)
751 } ia32_take_lea_attr;
754 * Decides if we have to keep the LEA operand or if we can assimilate it.
756 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
757 int have_am_sc, ia32_code_gen_t *cg)
759 ir_node *lea_base = get_irn_n(lea, 0);
760 ir_node *lea_idx = get_irn_n(lea, 1);
761 entity *irn_ent = get_ia32_frame_ent(irn);
762 entity *lea_ent = get_ia32_frame_ent(lea);
764 int is_noreg_base = be_is_NoReg(cg, base);
765 int is_noreg_index = be_is_NoReg(cg, index);
766 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
768 /* If the Add and the LEA both have a different frame entity set: keep */
769 if (irn_ent && lea_ent && (irn_ent != lea_ent))
770 return IA32_LEA_ATTR_NONE;
771 else if (! irn_ent && lea_ent)
772 ret_val |= IA32_LEA_ATTR_FENT;
774 /* If the Add and the LEA both have already an address mode symconst: keep */
775 if (have_am_sc && get_ia32_am_sc(lea))
776 return IA32_LEA_ATTR_NONE;
777 else if (get_ia32_am_sc(lea))
778 ret_val |= IA32_LEA_ATTR_AMSC;
780 /* Check the different base-index combinations */
782 if (! is_noreg_base && ! is_noreg_index) {
783 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
784 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
785 if (am_flav & ia32_O)
786 ret_val |= IA32_LEA_ATTR_OFFS;
788 ret_val |= IA32_LEA_ATTR_BASE;
791 return IA32_LEA_ATTR_NONE;
793 else if (! is_noreg_base && is_noreg_index) {
794 /* Base is set but index not */
796 /* Base points to LEA: assimilate everything */
797 if (am_flav & ia32_O)
798 ret_val |= IA32_LEA_ATTR_OFFS;
799 if (am_flav & ia32_S)
800 ret_val |= IA32_LEA_ATTR_SCALE;
801 if (am_flav & ia32_I)
802 ret_val |= IA32_LEA_ATTR_INDEX;
804 ret_val |= IA32_LEA_ATTR_BASE;
806 else if (am_flav & ia32_B ? 0 : 1) {
807 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
808 if (am_flav & ia32_O)
809 ret_val |= IA32_LEA_ATTR_OFFS;
810 if (am_flav & ia32_S)
811 ret_val |= IA32_LEA_ATTR_SCALE;
813 ret_val |= IA32_LEA_ATTR_INDEX;
816 return IA32_LEA_ATTR_NONE;
818 else if (is_noreg_base && ! is_noreg_index) {
819 /* Index is set but not base */
821 /* Index points to LEA: assimilate everything */
822 if (am_flav & ia32_O)
823 ret_val |= IA32_LEA_ATTR_OFFS;
824 if (am_flav & ia32_S)
825 ret_val |= IA32_LEA_ATTR_SCALE;
826 if (am_flav & ia32_B)
827 ret_val |= IA32_LEA_ATTR_BASE;
829 ret_val |= IA32_LEA_ATTR_INDEX;
831 else if (am_flav & ia32_I ? 0 : 1) {
832 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
833 if (am_flav & ia32_O)
834 ret_val |= IA32_LEA_ATTR_OFFS;
835 if (am_flav & ia32_S)
836 ret_val |= IA32_LEA_ATTR_SCALE;
838 ret_val |= IA32_LEA_ATTR_BASE;
841 return IA32_LEA_ATTR_NONE;
844 assert(0 && "There must have been set base or index");
852 * Folds Add or Sub to LEA if possible
854 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
855 ir_graph *irg = get_irn_irg(irn);
856 dbg_info *dbg = get_irn_dbg_info(irn);
857 ir_node *block = get_nodes_block(irn);
859 ir_node *shift = NULL;
860 ir_node *lea_o = NULL;
863 const char *offs_cnst = NULL;
864 char *offs_lea = NULL;
871 entity *lea_ent = NULL;
872 ir_node *left, *right, *temp;
873 ir_node *base, *index;
874 ia32_am_flavour_t am_flav;
875 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
877 if (is_ia32_Add(irn))
880 left = get_irn_n(irn, 2);
881 right = get_irn_n(irn, 3);
883 /* "normalize" arguments in case of add with two operands */
884 if (isadd && ! be_is_NoReg(cg, right)) {
885 /* put LEA == ia32_am_O as right operand */
886 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
887 set_irn_n(irn, 2, right);
888 set_irn_n(irn, 3, left);
894 /* put LEA != ia32_am_O as left operand */
895 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
896 set_irn_n(irn, 2, right);
897 set_irn_n(irn, 3, left);
903 /* put SHL as left operand iff left is NOT a LEA */
904 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
905 set_irn_n(irn, 2, right);
906 set_irn_n(irn, 3, left);
919 /* check for operation with immediate */
920 if (is_ia32_ImmConst(irn)) {
921 DBG((mod, LEVEL_1, "\tfound op with imm const"));
923 offs_cnst = get_ia32_cnst(irn);
926 else if (is_ia32_ImmSymConst(irn)) {
927 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
931 am_sc = get_ia32_id_cnst(irn);
932 am_sc_sign = is_ia32_am_sc_sign(irn);
935 /* determine the operand which needs to be checked */
936 if (be_is_NoReg(cg, right)) {
943 /* check if right operand is AMConst (LEA with ia32_am_O) */
944 /* but we can only eat it up if there is no other symconst */
945 /* because the linker won't accept two symconsts */
946 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
947 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
949 offs_lea = get_ia32_am_offs(temp);
950 am_sc = get_ia32_am_sc(temp);
951 am_sc_sign = is_ia32_am_sc_sign(temp);
958 /* default for add -> make right operand to index */
962 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
964 /* determine the operand which needs to be checked */
966 if (is_ia32_Lea(left)) {
970 /* check for SHL 1,2,3 */
971 if (pred_is_specific_node(temp, is_ia32_Shl)) {
972 temp = get_Proj_pred(temp);
975 if (get_ia32_Immop_tarval(temp)) {
976 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
979 index = get_irn_n(temp, 2);
981 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
991 if (! be_is_NoReg(cg, index)) {
992 /* if we have index, but left == right -> no base */
996 else if (! is_ia32_Lea(left) && (index != right)) {
997 /* index != right -> we found a good Shl */
998 /* left != LEA -> this Shl was the left operand */
999 /* -> base is right operand */
1005 /* Try to assimilate a LEA as left operand */
1006 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1007 /* check if we can assimilate the LEA */
1008 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1010 if (take_attr == IA32_LEA_ATTR_NONE) {
1011 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1014 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1015 lea = left; /* for statistics */
1017 if (take_attr & IA32_LEA_ATTR_OFFS)
1018 offs = get_ia32_am_offs(left);
1020 if (take_attr & IA32_LEA_ATTR_AMSC) {
1021 am_sc = get_ia32_am_sc(left);
1023 am_sc_sign = is_ia32_am_sc_sign(left);
1026 if (take_attr & IA32_LEA_ATTR_SCALE)
1027 scale = get_ia32_am_scale(left);
1029 if (take_attr & IA32_LEA_ATTR_BASE)
1030 base = get_irn_n(left, 0);
1032 if (take_attr & IA32_LEA_ATTR_INDEX)
1033 index = get_irn_n(left, 1);
1035 if (take_attr & IA32_LEA_ATTR_FENT)
1036 lea_ent = get_ia32_frame_ent(left);
1040 /* ok, we can create a new LEA */
1042 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1044 /* add the old offset of a previous LEA */
1046 add_ia32_am_offs(res, offs);
1049 /* add the new offset */
1052 add_ia32_am_offs(res, offs_cnst);
1055 add_ia32_am_offs(res, offs_lea);
1059 /* either lea_O-cnst, -cnst or -lea_O */
1062 add_ia32_am_offs(res, offs_lea);
1065 sub_ia32_am_offs(res, offs_cnst);
1068 sub_ia32_am_offs(res, offs_lea);
1072 /* set the address mode symconst */
1074 set_ia32_am_sc(res, am_sc);
1076 set_ia32_am_sc_sign(res);
1079 /* copy the frame entity (could be set in case of Add */
1080 /* which was a FrameAddr) */
1082 set_ia32_frame_ent(res, lea_ent);
1084 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1086 if (get_ia32_frame_ent(res))
1087 set_ia32_use_frame(res);
1090 set_ia32_am_scale(res, scale);
1092 am_flav = ia32_am_N;
1093 /* determine new am flavour */
1094 if (offs || offs_cnst || offs_lea) {
1097 if (! be_is_NoReg(cg, base)) {
1100 if (! be_is_NoReg(cg, index)) {
1106 set_ia32_am_flavour(res, am_flav);
1108 set_ia32_op_type(res, ia32_AddrModeS);
1110 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1112 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1114 /* we will exchange it, report here before the Proj is created */
1115 if (shift && lea && lea_o)
1116 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1117 else if (shift && lea)
1118 DBG_OPT_LEA3(irn, lea, shift, res);
1119 else if (shift && lea_o)
1120 DBG_OPT_LEA3(irn, lea_o, shift, res);
1121 else if (lea && lea_o)
1122 DBG_OPT_LEA3(irn, lea_o, lea, res);
1124 DBG_OPT_LEA2(irn, shift, res);
1126 DBG_OPT_LEA2(irn, lea, res);
1128 DBG_OPT_LEA2(irn, lea_o, res);
1130 DBG_OPT_LEA1(irn, res);
1132 /* get the result Proj of the Add/Sub */
1133 irn = get_res_proj(irn);
1135 assert(irn && "Couldn't find result proj");
1137 /* exchange the old op with the new LEA */
1146 * Merges a Load/Store node with a LEA.
1147 * @param irn The Load/Store node
1148 * @param lea The LEA
1150 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1151 entity *irn_ent = get_ia32_frame_ent(irn);
1152 entity *lea_ent = get_ia32_frame_ent(lea);
1154 /* If the irn and the LEA both have a different frame entity set: do not merge */
1155 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1157 else if (! irn_ent && lea_ent) {
1158 set_ia32_frame_ent(irn, lea_ent);
1159 set_ia32_use_frame(irn);
1162 /* get the AM attributes from the LEA */
1163 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1164 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1165 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1167 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1168 if (is_ia32_am_sc_sign(lea))
1169 set_ia32_am_sc_sign(irn);
1171 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1173 /* set base and index */
1174 set_irn_n(irn, 0, get_irn_n(lea, 0));
1175 set_irn_n(irn, 1, get_irn_n(lea, 1));
1177 /* clear remat flag */
1178 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1180 if (is_ia32_Ld(irn))
1181 DBG_OPT_LOAD_LEA(lea, irn);
1183 DBG_OPT_STORE_LEA(lea, irn);
1188 * Optimizes a pattern around irn to address mode if possible.
1190 void ia32_optimize_am(ir_node *irn, void *env) {
1191 ia32_code_gen_t *cg = env;
1195 ir_node *block, *noreg_gp, *noreg_fp;
1196 ir_node *left, *right, *temp;
1197 ir_node *store, *load, *mem_proj;
1198 ir_node *succ, *addr_b, *addr_i;
1199 int check_am_src = 0;
1200 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1202 if (! is_ia32_irn(irn))
1205 dbg = get_irn_dbg_info(irn);
1206 mode = get_irn_mode(irn);
1207 block = get_nodes_block(irn);
1208 noreg_gp = ia32_new_NoReg_gp(cg);
1209 noreg_fp = ia32_new_NoReg_fp(cg);
1211 DBG((mod, LEVEL_1, "checking for AM\n"));
1213 /* 1st part: check for address calculations and transform the into Lea */
1215 /* Following cases can occur: */
1216 /* - Sub (l, imm) -> LEA [base - offset] */
1217 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1218 /* - Add (l, imm) -> LEA [base + offset] */
1219 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1220 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1221 /* - Add (l, r) -> LEA [base + index * scale] */
1222 /* with scale > 1 iff l/r == shl (1,2,3) */
1224 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1225 left = get_irn_n(irn, 2);
1226 right = get_irn_n(irn, 3);
1228 /* Do not try to create a LEA if one of the operands is a Load. */
1229 /* check is irn is a candidate for address calculation */
1230 if (is_candidate(block, irn, 1)) {
1231 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1232 res = fold_addr(cg, irn, noreg_gp);
1235 DB((mod, LEVEL_1, "transformed into %+F\n", res));
1237 DB((mod, LEVEL_1, "not transformed\n"));
1241 /* 2nd part: fold following patterns: */
1242 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1243 /* - Store -> LEA into Store } it might be better to keep the LEA */
1244 /* - op -> Load into AMop with am_Source */
1246 /* - op is am_Source capable AND */
1247 /* - the Load is only used by this op AND */
1248 /* - the Load is in the same block */
1249 /* - Store -> op -> Load into AMop with am_Dest */
1251 /* - op is am_Dest capable AND */
1252 /* - the Store uses the same address as the Load AND */
1253 /* - the Load is only used by this op AND */
1254 /* - the Load and Store are in the same block AND */
1255 /* - nobody else uses the result of the op */
1257 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
1258 /* 1st: check for Load/Store -> LEA */
1259 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1260 left = get_irn_n(irn, 0);
1262 if (is_ia32_Lea(left)) {
1263 const ir_edge_t *edge, *ne;
1266 /* merge all Loads/Stores connected to this LEA with the LEA */
1267 foreach_out_edge_safe(left, edge, ne) {
1268 src = get_edge_src_irn(edge);
1270 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1271 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1272 merge_loadstore_lea(src, left);
1277 /* check if the node is an address mode candidate */
1278 else if (is_candidate(block, irn, 0)) {
1279 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1281 left = get_irn_n(irn, 2);
1282 if (get_irn_arity(irn) == 4) {
1283 /* it's an "unary" operation */
1287 right = get_irn_n(irn, 3);
1290 /* normalize commutative ops */
1291 if (node_is_ia32_comm(irn)) {
1292 /* Assure that right operand is always a Load if there is one */
1293 /* because non-commutative ops can only use Dest AM if the right */
1294 /* operand is a load, so we only need to check right operand. */
1295 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1297 set_irn_n(irn, 2, right);
1298 set_irn_n(irn, 3, left);
1306 /* check for Store -> op -> Load */
1308 /* Store -> op -> Load optimization is only possible if supported by op */
1309 /* and if right operand is a Load */
1310 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1311 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1314 /* An address mode capable op always has a result Proj. */
1315 /* If this Proj is used by more than one other node, we don't need to */
1316 /* check further, otherwise we check for Store and remember the address, */
1317 /* the Store points to. */
1319 succ = get_res_proj(irn);
1320 assert(succ && "Couldn't find result proj");
1326 /* now check for users and Store */
1327 if (ia32_get_irn_n_edges(succ) == 1) {
1328 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1330 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1332 addr_b = get_irn_n(store, 0);
1333 addr_i = get_irn_n(store, 1);
1338 /* we found a Store as single user: Now check for Load */
1340 /* Extra check for commutative ops with two Loads */
1341 /* -> put the interesting Load right */
1342 if (node_is_ia32_comm(irn) &&
1343 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1345 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1346 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1348 /* We exchange left and right, so it's easier to kill */
1349 /* the correct Load later and to handle unary operations. */
1350 set_irn_n(irn, 2, right);
1351 set_irn_n(irn, 3, left);
1359 /* skip the Proj for easier access */
1360 load = get_Proj_pred(right);
1362 /* Compare Load and Store address */
1363 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1364 /* Right Load is from same address, so we can */
1365 /* disconnect the Load and Store here */
1367 /* set new base, index and attributes */
1368 set_irn_n(irn, 0, addr_b);
1369 set_irn_n(irn, 1, addr_i);
1370 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1371 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1372 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1373 set_ia32_op_type(irn, ia32_AddrModeD);
1374 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1375 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1377 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1378 if (is_ia32_am_sc_sign(load))
1379 set_ia32_am_sc_sign(irn);
1381 if (is_ia32_use_frame(load))
1382 set_ia32_use_frame(irn);
1384 /* connect to Load memory and disconnect Load */
1385 if (get_irn_arity(irn) == 5) {
1387 set_irn_n(irn, 4, get_irn_n(load, 2));
1388 set_irn_n(irn, 3, noreg_gp);
1392 set_irn_n(irn, 3, get_irn_n(load, 2));
1393 set_irn_n(irn, 2, noreg_gp);
1396 /* connect the memory Proj of the Store to the op */
1397 mem_proj = get_mem_proj(store);
1398 set_Proj_pred(mem_proj, irn);
1399 set_Proj_proj(mem_proj, 1);
1401 /* clear remat flag */
1402 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1404 DBG_OPT_AM_D(load, store, irn);
1406 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1409 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1410 /* There was no store, check if we still can optimize for source address mode */
1413 } /* if (support AM Dest) */
1414 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1415 /* op doesn't support am AM Dest -> check for AM Source */
1419 /* normalize commutative ops */
1420 if (node_is_ia32_comm(irn)) {
1421 /* Assure that left operand is always a Load if there is one */
1422 /* because non-commutative ops can only use Source AM if the */
1423 /* left operand is a Load, so we only need to check the left */
1424 /* operand afterwards. */
1425 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1426 set_irn_n(irn, 2, right);
1427 set_irn_n(irn, 3, left);
1435 /* optimize op -> Load iff Load is only used by this op */
1436 /* and left operand is a Load which only used by this irn */
1438 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1439 (ia32_get_irn_n_edges(left) == 1))
1441 left = get_Proj_pred(left);
1443 addr_b = get_irn_n(left, 0);
1444 addr_i = get_irn_n(left, 1);
1446 /* set new base, index and attributes */
1447 set_irn_n(irn, 0, addr_b);
1448 set_irn_n(irn, 1, addr_i);
1449 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1450 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1451 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1452 set_ia32_op_type(irn, ia32_AddrModeS);
1453 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1454 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1456 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1457 if (is_ia32_am_sc_sign(left))
1458 set_ia32_am_sc_sign(irn);
1460 /* clear remat flag */
1461 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1463 if (is_ia32_use_frame(left))
1464 set_ia32_use_frame(irn);
1466 /* connect to Load memory */
1467 if (get_irn_arity(irn) == 5) {
1469 set_irn_n(irn, 4, get_irn_n(left, 2));
1473 set_irn_n(irn, 3, get_irn_n(left, 2));
1476 /* disconnect from Load */
1477 set_irn_n(irn, 2, noreg_gp);
1479 DBG_OPT_AM_S(left, irn);
1481 /* If Load has a memory Proj, connect it to the op */
1482 mem_proj = get_mem_proj(left);
1484 set_Proj_pred(mem_proj, irn);
1485 set_Proj_proj(mem_proj, 1);
1488 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));