3 * File name: ir/be/ia32/ia32_optimize.c
4 * Purpose: Implements several optimizations for IA32
5 * Author: Christian Wuerdig
7 * Copyright: (c) 2006 Universitaet Karlsruhe
8 * Licence: This file protected by GPL - GNU GENERAL PUBLIC LICENSE.
18 #include "firm_types.h"
28 #include "../benode_t.h"
29 #include "../besched_t.h"
31 #include "ia32_new_nodes.h"
32 #include "bearch_ia32_t.h"
33 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
34 #include "ia32_transform.h"
35 #include "ia32_dbg_stat.h"
36 #include "ia32_util.h"
41 IA32_AM_CAND_NONE = 0, /**< no addressmode possible with irn inputs */
42 IA32_AM_CAND_LEFT = 1, /**< addressmode possible with left input */
43 IA32_AM_CAND_RIGHT = 2, /**< addressmode possible with right input */
44 IA32_AM_CAND_BOTH = 3 /**< addressmode possible with both inputs */
47 typedef int is_op_func_t(const ir_node *n);
48 typedef ir_node *load_func_t(dbg_info *db, ir_graph *irg, ir_node *block, ir_node *base, ir_node *index, ir_node *mem);
51 * checks if a node represents the NOREG value
53 static INLINE int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
54 return irn == cg->noreg_gp || irn == cg->noreg_xmm || irn == cg->noreg_vfp;
57 void ia32_pre_transform_phase(ia32_code_gen_t *cg) {
59 We need to transform the consts twice:
60 - the psi condition tree transformer needs existing constants to be ia32 constants
61 - the psi condition tree transformer inserts new firm constants which need to be transformed
63 //ia32_transform_all_firm_consts(cg);
64 irg_walk_graph(cg->irg, NULL, ia32_transform_psi_cond_tree, cg);
65 //ia32_transform_all_firm_consts(cg);
68 /********************************************************************************************************
69 * _____ _ _ ____ _ _ _ _ _
70 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
71 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
72 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
73 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
74 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
77 ********************************************************************************************************/
80 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
83 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
84 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
88 * Checks for potential CJmp/CJmpAM optimization candidates.
90 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
92 ir_node *prev = sched_prev(irn);
95 if (get_Block_n_cfgpreds(prev) == 1)
96 prev = get_Block_cfgpred(prev, 0);
101 /* The predecessor must be a ProjX. */
102 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
103 prev = get_Proj_pred(prev);
105 if (is_op_func(prev))
112 static int is_TestJmp_cand(const ir_node *irn) {
113 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
117 * Checks if two consecutive arguments of cand matches
118 * the two arguments of irn (TestJmp).
120 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
121 ir_node *in1 = get_irn_n(irn, 0);
122 ir_node *in2 = get_irn_n(irn, 1);
123 int i, n = get_irn_arity(cand);
126 for (i = 0; i < n - 1; i++) {
127 if (get_irn_n(cand, i) == in1 &&
128 get_irn_n(cand, i + 1) == in2)
136 return ia32_cnst_compare(cand, irn);
142 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
144 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
145 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
148 /* we found a possible candidate */
149 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
152 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
154 if (is_ia32_And(cand))
155 set_irn_op(irn, op_ia32_CJmpAM);
157 set_irn_op(irn, op_ia32_CJmp);
159 DB((cg->mod, LEVEL_1, "%+F\n", irn));
163 static int is_CondJmp_cand(const ir_node *irn) {
164 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
168 * Checks if the arguments of cand are the same of irn.
170 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
171 int i, n = get_irn_arity(cand);
174 for (i = 0; i < n; i++) {
175 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
182 return ia32_cnst_compare(cand, irn);
188 * Tries to replace a CondJmp by a CJmpAM
190 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
191 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
194 /* we found a possible candidate */
195 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
198 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
201 set_irn_op(irn, op_ia32_CJmpAM);
203 DB((cg->mod, LEVEL_1, "%+F\n", irn));
207 // only optimize up to 48 stores behind IncSPs
208 #define MAXPUSH_OPTIMIZE 48
211 * Tries to create pushs from IncSP,Store combinations
213 static void ia32_create_Pushs(ir_node *irn, ia32_code_gen_t *cg) {
217 ir_node *stores[MAXPUSH_OPTIMIZE];
218 ir_node *block = get_nodes_block(irn);
219 ir_graph *irg = cg->irg;
221 ir_mode *spmode = get_irn_mode(irn);
223 memset(stores, 0, sizeof(stores));
225 assert(be_is_IncSP(irn));
227 offset = be_get_IncSP_offset(irn);
232 * We first walk the schedule after the IncSP node as long as we find
233 * suitable stores that could be transformed to a push.
234 * We save them into the stores array which is sorted by the frame offset/4
235 * attached to the node
237 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
244 // it has to be a store
245 if(!is_ia32_Store(node))
248 // it has to use our sp value
249 if(get_irn_n(node, 0) != irn)
251 // store has to be attached to NoMem
252 mem = get_irn_n(node, 3);
257 if( (get_ia32_am_flavour(node) & ia32_am_IS) != 0)
260 am_offs = get_ia32_am_offs(node);
261 if(am_offs == NULL) {
264 // the am_offs has to be of the form "+NUMBER"
265 if(sscanf(am_offs, "+%d%n", &offset, &n) != 1 || am_offs[n] != '\0') {
266 // we shouldn't have any cases in the compiler at the moment
267 // that produce something different from esp+XX
273 storeslot = offset / 4;
274 if(storeslot >= MAXPUSH_OPTIMIZE)
277 // storing into the same slot twice is bad (and shouldn't happen...)
278 if(stores[storeslot] != NULL)
281 // storing at half-slots is bad
285 stores[storeslot] = node;
288 curr_sp = get_irn_n(irn, 0);
290 // walk the stores in inverse order and create pushs for them
291 i = (offset / 4) - 1;
292 if(i >= MAXPUSH_OPTIMIZE) {
293 i = MAXPUSH_OPTIMIZE - 1;
296 for( ; i >= 0; --i) {
297 const arch_register_t *spreg;
300 ir_node *store = stores[i];
301 ir_node *noreg = ia32_new_NoReg_gp(cg);
303 if(store == NULL || is_Bad(store))
306 val = get_irn_n(store, 2);
307 mem = get_irn_n(store, 3);
308 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
311 push = new_rd_ia32_Push(NULL, irg, block, noreg, noreg, val, curr_sp, mem);
312 if(get_ia32_immop_type(store) != ia32_ImmNone) {
313 copy_ia32_Immop_attr(push, store);
315 sched_add_before(irn, push);
317 // create stackpointer proj
318 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
319 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
320 sched_add_before(irn, curr_sp);
323 edges_reroute(store, push, irg);
325 // we can remove the store now
326 set_irn_n(store, 0, new_Bad());
327 set_irn_n(store, 1, new_Bad());
328 set_irn_n(store, 2, new_Bad());
329 set_irn_n(store, 3, new_Bad());
335 be_set_IncSP_offset(irn, offset);
337 // can we remove the IncSP now?
339 const ir_edge_t *edge, *next;
341 foreach_out_edge_safe(irn, edge, next) {
342 ir_node *arg = get_edge_src_irn(edge);
343 int pos = get_edge_src_pos(edge);
345 set_irn_n(arg, pos, curr_sp);
348 set_irn_n(irn, 0, new_Bad());
351 set_irn_n(irn, 0, curr_sp);
356 * Tries to optimize two following IncSP.
358 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
359 ir_node *prev = be_get_IncSP_pred(irn);
360 int real_uses = get_irn_n_edges(prev);
362 if (be_is_IncSP(prev) && real_uses == 1) {
363 /* first IncSP has only one IncSP user, kill the first one */
364 int prev_offs = be_get_IncSP_offset(prev);
365 int curr_offs = be_get_IncSP_offset(irn);
367 be_set_IncSP_offset(prev, prev_offs + curr_offs);
369 /* Omit the optimized IncSP */
370 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
372 set_irn_n(prev, 0, new_Bad());
378 * Performs Peephole Optimizations.
380 static void ia32_peephole_optimize_node(ir_node *irn, void *env) {
381 ia32_code_gen_t *cg = env;
383 /* AMD CPUs want explicit compare before conditional jump */
384 if (! ARCH_AMD(cg->opt_arch)) {
385 if (is_ia32_TestJmp(irn))
386 ia32_optimize_TestJmp(irn, cg);
387 else if (is_ia32_CondJmp(irn))
388 ia32_optimize_CondJmp(irn, cg);
391 if (be_is_IncSP(irn)) {
392 // optimize_IncSP doesn't respect dependency edges yet...
393 //ia32_optimize_IncSP(irn, cg);
394 (void) ia32_optimize_IncSP;
395 if (cg->opt & IA32_OPT_PUSHARGS)
396 ia32_create_Pushs(irn, cg);
400 void ia32_peephole_optimization(ir_graph *irg, ia32_code_gen_t *cg) {
401 irg_walk_graph(irg, ia32_peephole_optimize_node, NULL, cg);
404 /******************************************************************
406 * /\ | | | | | \/ | | |
407 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
408 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
409 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
410 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
412 ******************************************************************/
419 static int node_is_ia32_comm(const ir_node *irn) {
420 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
423 static int ia32_get_irn_n_edges(const ir_node *irn) {
424 const ir_edge_t *edge;
427 foreach_out_edge(irn, edge) {
435 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
437 * @param pred The node to be checked
438 * @param is_op_func The check-function
439 * @return 1 if conditions are fulfilled, 0 otherwise
441 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
442 return is_op_func(pred);
446 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
447 * and if the predecessor is in block bl.
449 * @param bl The block
450 * @param pred The node to be checked
451 * @param is_op_func The check-function
452 * @return 1 if conditions are fulfilled, 0 otherwise
454 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
455 int (*is_op_func)(const ir_node *n))
458 pred = get_Proj_pred(pred);
459 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
468 * Checks if irn is a candidate for address calculation. We avoid transforming
469 * adds to leas if they have a load as pred, because then we can use AM mode
472 * - none of the operand must be a Load within the same block OR
473 * - all Loads must have more than one user OR
475 * @param block The block the Loads must/mustnot be in
476 * @param irn The irn to check
477 * return 1 if irn is a candidate, 0 otherwise
479 static int is_addr_candidate(const ir_node *irn) {
480 #ifndef AGGRESSIVE_AM
481 const ir_node *block = get_nodes_block(irn);
482 ir_node *left, *right;
485 left = get_irn_n(irn, 2);
486 right = get_irn_n(irn, 3);
488 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld)) {
489 n = ia32_get_irn_n_edges(left);
490 /* load with only one user: don't create LEA */
495 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
496 n = ia32_get_irn_n_edges(right);
506 * Checks if irn is a candidate for address mode.
509 * - at least one operand has to be a Load within the same block AND
510 * - the load must not have other users than the irn AND
511 * - the irn must not have a frame entity set
513 * @param cg The ia32 code generator
514 * @param h The height information of the irg
515 * @param block The block the Loads must/mustnot be in
516 * @param irn The irn to check
517 * return 0 if irn is no candidate, 1 if left load can be used, 2 if right one, 3 for both
519 static ia32_am_cand_t is_am_candidate(ia32_code_gen_t *cg, heights_t *h, const ir_node *block, ir_node *irn) {
520 ir_node *in, *load, *other, *left, *right;
521 int is_cand = 0, cand;
524 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn) || is_ia32_vfild(irn) || is_ia32_vfist(irn) ||
525 is_ia32_GetST0(irn) || is_ia32_SetST0(irn) || is_ia32_xStoreSimple(irn))
528 left = get_irn_n(irn, 2);
529 arity = get_irn_arity(irn);
530 assert(arity == 5 || arity == 4);
533 right = get_irn_n(irn, 3);
541 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
542 #ifndef AGGRESSIVE_AM
544 n = ia32_get_irn_n_edges(in);
545 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
550 load = get_Proj_pred(in);
553 /* 8bit Loads are not supported (for binary ops),
554 * they cannot be used with every register */
555 if (get_irn_arity(irn) != 4 && get_mode_size_bits(get_ia32_ls_mode(load)) < 16) {
556 assert(get_irn_arity(irn) == 5);
560 /* If there is a data dependency of other irn from load: cannot use AM */
561 if (is_cand && get_nodes_block(other) == block) {
562 other = skip_Proj(other);
563 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
564 /* this could happen in loops */
565 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
569 cand = is_cand ? IA32_AM_CAND_LEFT : IA32_AM_CAND_NONE;
573 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
574 #ifndef AGGRESSIVE_AM
576 n = ia32_get_irn_n_edges(in);
577 is_cand = (n == 1) ? 1 : is_cand; /* load with more than one user: no AM */
582 load = get_Proj_pred(in);
585 /* 8bit Loads are not supported, they cannot be used with every register */
586 if (get_mode_size_bits(get_ia32_ls_mode(load)) < 16)
589 /* If there is a data dependency of other irn from load: cannot use load */
590 if (is_cand && get_nodes_block(other) == block) {
591 other = skip_Proj(other);
592 is_cand = heights_reachable_in_block(h, other, load) ? 0 : is_cand;
593 /* this could happen in loops */
594 is_cand = heights_reachable_in_block(h, load, irn) ? 0 : is_cand;
598 cand = is_cand ? (cand | IA32_AM_CAND_RIGHT) : cand;
600 /* if the irn has a frame entity: we do not use address mode */
601 return get_ia32_frame_ent(irn) ? IA32_AM_CAND_NONE : cand;
605 * Compares the base and index addr and the load/store entities
606 * and returns 1 if they are equal.
608 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
609 const ir_node *addr_b, const ir_node *addr_i)
611 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
612 ir_entity *lent = get_ia32_frame_ent(load);
613 ir_entity *sent = get_ia32_frame_ent(store);
614 ident *lid = get_ia32_am_sc(load);
615 ident *sid = get_ia32_am_sc(store);
616 char *loffs = get_ia32_am_offs(load);
617 char *soffs = get_ia32_am_offs(store);
619 /* are both entities set and equal? */
620 if (is_equal && (lent || sent))
621 is_equal = lent && sent && (lent == sent);
623 /* are address mode idents set and equal? */
624 if (is_equal && (lid || sid))
625 is_equal = lid && sid && (lid == sid);
627 /* are offsets set and equal */
628 if (is_equal && (loffs || soffs))
629 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
631 /* are the load and the store of the same mode? */
632 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
637 typedef enum _ia32_take_lea_attr {
638 IA32_LEA_ATTR_NONE = 0,
639 IA32_LEA_ATTR_BASE = (1 << 0),
640 IA32_LEA_ATTR_INDEX = (1 << 1),
641 IA32_LEA_ATTR_OFFS = (1 << 2),
642 IA32_LEA_ATTR_SCALE = (1 << 3),
643 IA32_LEA_ATTR_AMSC = (1 << 4),
644 IA32_LEA_ATTR_FENT = (1 << 5)
645 } ia32_take_lea_attr;
648 * Decides if we have to keep the LEA operand or if we can assimilate it.
650 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
651 int have_am_sc, ia32_code_gen_t *cg)
653 ir_entity *irn_ent = get_ia32_frame_ent(irn);
654 ir_entity *lea_ent = get_ia32_frame_ent(lea);
656 int is_noreg_base = be_is_NoReg(cg, base);
657 int is_noreg_index = be_is_NoReg(cg, index);
658 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
660 /* If the Add and the LEA both have a different frame entity set: keep */
661 if (irn_ent && lea_ent && (irn_ent != lea_ent))
662 return IA32_LEA_ATTR_NONE;
663 else if (! irn_ent && lea_ent)
664 ret_val |= IA32_LEA_ATTR_FENT;
666 /* If the Add and the LEA both have already an address mode symconst: keep */
667 if (have_am_sc && get_ia32_am_sc(lea))
668 return IA32_LEA_ATTR_NONE;
669 else if (get_ia32_am_sc(lea))
670 ret_val |= IA32_LEA_ATTR_AMSC;
672 /* Check the different base-index combinations */
674 if (! is_noreg_base && ! is_noreg_index) {
675 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
676 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
677 if (am_flav & ia32_O)
678 ret_val |= IA32_LEA_ATTR_OFFS;
680 ret_val |= IA32_LEA_ATTR_BASE;
683 return IA32_LEA_ATTR_NONE;
685 else if (! is_noreg_base && is_noreg_index) {
686 /* Base is set but index not */
688 /* Base points to LEA: assimilate everything */
689 if (am_flav & ia32_O)
690 ret_val |= IA32_LEA_ATTR_OFFS;
691 if (am_flav & ia32_S)
692 ret_val |= IA32_LEA_ATTR_SCALE;
693 if (am_flav & ia32_I)
694 ret_val |= IA32_LEA_ATTR_INDEX;
696 ret_val |= IA32_LEA_ATTR_BASE;
698 else if (am_flav & ia32_B ? 0 : 1) {
699 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
700 if (am_flav & ia32_O)
701 ret_val |= IA32_LEA_ATTR_OFFS;
702 if (am_flav & ia32_S)
703 ret_val |= IA32_LEA_ATTR_SCALE;
705 ret_val |= IA32_LEA_ATTR_INDEX;
708 return IA32_LEA_ATTR_NONE;
710 else if (is_noreg_base && ! is_noreg_index) {
711 /* Index is set but not base */
713 /* Index points to LEA: assimilate everything */
714 if (am_flav & ia32_O)
715 ret_val |= IA32_LEA_ATTR_OFFS;
716 if (am_flav & ia32_S)
717 ret_val |= IA32_LEA_ATTR_SCALE;
718 if (am_flav & ia32_B)
719 ret_val |= IA32_LEA_ATTR_BASE;
721 ret_val |= IA32_LEA_ATTR_INDEX;
723 else if (am_flav & ia32_I ? 0 : 1) {
724 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
725 if (am_flav & ia32_O)
726 ret_val |= IA32_LEA_ATTR_OFFS;
727 if (am_flav & ia32_S)
728 ret_val |= IA32_LEA_ATTR_SCALE;
730 ret_val |= IA32_LEA_ATTR_BASE;
733 return IA32_LEA_ATTR_NONE;
736 assert(0 && "There must have been set base or index");
743 * Adds res before irn into schedule if irn was scheduled.
744 * @param irn The schedule point
745 * @param res The node to be scheduled
747 static INLINE void try_add_to_sched(ir_node *irn, ir_node *res) {
748 if (sched_is_scheduled(irn))
749 sched_add_before(irn, res);
753 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
754 * all it's Projs are removed as well.
755 * @param irn The irn to be removed from schedule
757 static INLINE void try_remove_from_sched(ir_node *node) {
760 if(get_irn_mode(node) == mode_T) {
761 const ir_edge_t *edge;
762 foreach_out_edge(node, edge) {
763 ir_node *proj = get_edge_src_irn(edge);
764 try_remove_from_sched(proj);
768 if(get_irn_n_edges(node) != 0)
771 if (sched_is_scheduled(node)) {
775 arity = get_irn_arity(node);
776 for(i = 0; i < arity; ++i) {
777 set_irn_n(node, i, new_Bad());
782 * Folds Add or Sub to LEA if possible
784 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn) {
785 ir_graph *irg = get_irn_irg(irn);
786 dbg_info *dbg = get_irn_dbg_info(irn);
787 ir_node *block = get_nodes_block(irn);
789 ir_node *shift = NULL;
790 ir_node *lea_o = NULL;
801 ir_entity *lea_ent = NULL;
802 ir_node *noreg = ia32_new_NoReg_gp(cg);
803 ir_node *left, *right, *temp;
804 ir_node *base, *index;
805 int consumed_left_shift;
806 ia32_am_flavour_t am_flav;
807 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
809 if (is_ia32_Add(irn))
812 left = get_irn_n(irn, 2);
813 right = get_irn_n(irn, 3);
815 /* "normalize" arguments in case of add with two operands */
816 if (isadd && ! be_is_NoReg(cg, right)) {
817 /* put LEA == ia32_am_O as right operand */
818 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
819 set_irn_n(irn, 2, right);
820 set_irn_n(irn, 3, left);
826 /* put LEA != ia32_am_O as left operand */
827 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
828 set_irn_n(irn, 2, right);
829 set_irn_n(irn, 3, left);
835 /* put SHL as left operand iff left is NOT a LEA */
836 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
837 set_irn_n(irn, 2, right);
838 set_irn_n(irn, 3, left);
851 /* check for operation with immediate */
852 if (is_ia32_ImmConst(irn)) {
853 tarval *tv = get_ia32_Immop_tarval(irn);
855 DBG((mod, LEVEL_1, "\tfound op with imm const"));
857 offs_cnst = get_tarval_long(tv);
860 else if (isadd && is_ia32_ImmSymConst(irn)) {
861 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
865 am_sc = get_ia32_id_cnst(irn);
866 am_sc_sign = is_ia32_am_sc_sign(irn);
869 /* determine the operand which needs to be checked */
870 temp = be_is_NoReg(cg, right) ? left : right;
872 /* check if right operand is AMConst (LEA with ia32_am_O) */
873 /* but we can only eat it up if there is no other symconst */
874 /* because the linker won't accept two symconsts */
875 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
876 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
878 offs_lea = get_ia32_am_offs_int(temp);
879 am_sc = get_ia32_am_sc(temp);
880 am_sc_sign = is_ia32_am_sc_sign(temp);
887 else if (temp == right)
892 /* default for add -> make right operand to index */
895 consumed_left_shift = -1;
897 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
899 /* determine the operand which needs to be checked */
901 if (is_ia32_Lea(left)) {
903 consumed_left_shift = 0;
906 /* check for SHL 1,2,3 */
907 if (pred_is_specific_node(temp, is_ia32_Shl)) {
909 if (get_ia32_Immop_tarval(temp)) {
910 long shiftval = get_tarval_long(get_ia32_Immop_tarval(temp));
913 index = get_irn_n(temp, 2);
914 consumed_left_shift = consumed_left_shift < 0 ? 1 : 0;
918 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
924 if (! be_is_NoReg(cg, index)) {
925 /* if we have index, but left == right -> no base */
929 else if (consumed_left_shift == 1) {
930 /* -> base is right operand */
931 base = (right == lea_o) ? noreg : right;
936 /* Try to assimilate a LEA as left operand */
937 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
938 /* check if we can assimilate the LEA */
939 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
941 if (take_attr == IA32_LEA_ATTR_NONE) {
942 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
945 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
946 lea = left; /* for statistics */
948 if (take_attr & IA32_LEA_ATTR_OFFS)
949 offs = get_ia32_am_offs_int(left);
951 if (take_attr & IA32_LEA_ATTR_AMSC) {
952 am_sc = get_ia32_am_sc(left);
954 am_sc_sign = is_ia32_am_sc_sign(left);
957 if (take_attr & IA32_LEA_ATTR_SCALE)
958 scale = get_ia32_am_scale(left);
960 if (take_attr & IA32_LEA_ATTR_BASE)
961 base = get_irn_n(left, 0);
963 if (take_attr & IA32_LEA_ATTR_INDEX)
964 index = get_irn_n(left, 1);
966 if (take_attr & IA32_LEA_ATTR_FENT)
967 lea_ent = get_ia32_frame_ent(left);
971 /* ok, we can create a new LEA */
973 res = new_rd_ia32_Lea(dbg, irg, block, base, index);
975 /* add the old offset of a previous LEA */
976 add_ia32_am_offs_int(res, offs);
978 /* add the new offset */
980 add_ia32_am_offs_int(res, offs_cnst);
981 add_ia32_am_offs_int(res, offs_lea);
983 /* either lea_O-cnst, -cnst or -lea_O */
984 if (offs_cnst != 0) {
985 add_ia32_am_offs_int(res, offs_lea);
986 add_ia32_am_offs_int(res, -offs_cnst);
988 add_ia32_am_offs_int(res, offs_lea);
992 /* set the address mode symconst */
994 set_ia32_am_sc(res, am_sc);
996 set_ia32_am_sc_sign(res);
999 /* copy the frame entity (could be set in case of Add */
1000 /* which was a FrameAddr) */
1001 if (lea_ent != NULL) {
1002 set_ia32_frame_ent(res, lea_ent);
1003 set_ia32_use_frame(res);
1005 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1006 if(is_ia32_use_frame(irn))
1007 set_ia32_use_frame(res);
1011 set_ia32_am_scale(res, scale);
1013 am_flav = ia32_am_N;
1014 /* determine new am flavour */
1015 if (offs || offs_cnst || offs_lea || have_am_sc) {
1018 if (! be_is_NoReg(cg, base)) {
1021 if (! be_is_NoReg(cg, index)) {
1027 set_ia32_am_flavour(res, am_flav);
1029 set_ia32_op_type(res, ia32_AddrModeS);
1031 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1033 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1035 /* we will exchange it, report here before the Proj is created */
1036 if (shift && lea && lea_o) {
1037 try_remove_from_sched(shift);
1038 try_remove_from_sched(lea);
1039 try_remove_from_sched(lea_o);
1040 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1042 else if (shift && lea) {
1043 try_remove_from_sched(shift);
1044 try_remove_from_sched(lea);
1045 DBG_OPT_LEA3(irn, lea, shift, res);
1047 else if (shift && lea_o) {
1048 try_remove_from_sched(shift);
1049 try_remove_from_sched(lea_o);
1050 DBG_OPT_LEA3(irn, lea_o, shift, res);
1052 else if (lea && lea_o) {
1053 try_remove_from_sched(lea);
1054 try_remove_from_sched(lea_o);
1055 DBG_OPT_LEA3(irn, lea_o, lea, res);
1058 try_remove_from_sched(shift);
1059 DBG_OPT_LEA2(irn, shift, res);
1062 try_remove_from_sched(lea);
1063 DBG_OPT_LEA2(irn, lea, res);
1066 try_remove_from_sched(lea_o);
1067 DBG_OPT_LEA2(irn, lea_o, res);
1070 DBG_OPT_LEA1(irn, res);
1072 /* get the result Proj of the Add/Sub */
1073 try_add_to_sched(irn, res);
1074 try_remove_from_sched(irn);
1076 assert(irn && "Couldn't find result proj");
1078 /* exchange the old op with the new LEA */
1087 * Merges a Load/Store node with a LEA.
1088 * @param irn The Load/Store node
1089 * @param lea The LEA
1091 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1092 ir_entity *irn_ent = get_ia32_frame_ent(irn);
1093 ir_entity *lea_ent = get_ia32_frame_ent(lea);
1095 /* If the irn and the LEA both have a different frame entity set: do not merge */
1096 if (irn_ent != NULL && lea_ent != NULL && (irn_ent != lea_ent))
1098 else if (irn_ent == NULL && lea_ent != NULL) {
1099 set_ia32_frame_ent(irn, lea_ent);
1100 set_ia32_use_frame(irn);
1103 /* get the AM attributes from the LEA */
1104 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(lea));
1105 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1106 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1108 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1109 if (is_ia32_am_sc_sign(lea))
1110 set_ia32_am_sc_sign(irn);
1112 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1114 /* set base and index */
1115 set_irn_n(irn, 0, get_irn_n(lea, 0));
1116 set_irn_n(irn, 1, get_irn_n(lea, 1));
1118 try_remove_from_sched(lea);
1120 /* clear remat flag */
1121 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1123 if (is_ia32_Ld(irn))
1124 DBG_OPT_LOAD_LEA(lea, irn);
1126 DBG_OPT_STORE_LEA(lea, irn);
1131 * Sets new_right index of irn to right and new_left index to left.
1132 * Also exchange left and right
1134 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1137 set_irn_n(irn, new_right, *right);
1138 set_irn_n(irn, new_left, *left);
1144 /* this is only needed for Compares, but currently ALL nodes
1145 * have this attribute :-) */
1146 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1150 * Performs address calculation optimization (create LEAs if possible)
1152 static void optimize_lea(ir_node *irn, void *env) {
1153 ia32_code_gen_t *cg = env;
1155 if (! is_ia32_irn(irn))
1158 /* Following cases can occur: */
1159 /* - Sub (l, imm) -> LEA [base - offset] */
1160 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1161 /* - Add (l, imm) -> LEA [base + offset] */
1162 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1163 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1164 /* - Add (l, r) -> LEA [base + index * scale] */
1165 /* with scale > 1 iff l/r == shl (1,2,3) */
1166 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1169 if(!is_addr_candidate(irn))
1172 DBG((cg->mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1173 res = fold_addr(cg, irn);
1176 DB((cg->mod, LEVEL_1, "transformed into %+F\n", res));
1178 DB((cg->mod, LEVEL_1, "not transformed\n"));
1179 } else if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1180 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1181 /* - Store -> LEA into Store } it might be better to keep the LEA */
1182 ir_node *left = get_irn_n(irn, 0);
1184 if (is_ia32_Lea(left)) {
1185 const ir_edge_t *edge, *ne;
1188 /* merge all Loads/Stores connected to this LEA with the LEA */
1189 foreach_out_edge_safe(left, edge, ne) {
1190 src = get_edge_src_irn(edge);
1192 if (src && (get_edge_src_pos(edge) == 0) && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1193 DBG((cg->mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1194 if (! is_ia32_got_lea(src))
1195 merge_loadstore_lea(src, left);
1196 set_ia32_got_lea(src);
1204 * Checks for address mode patterns and performs the
1205 * necessary transformations.
1206 * This function is called by a walker.
1208 static void optimize_am(ir_node *irn, void *env) {
1209 ia32_am_opt_env_t *am_opt_env = env;
1210 ia32_code_gen_t *cg = am_opt_env->cg;
1211 ir_graph *irg = get_irn_irg(irn);
1212 heights_t *h = am_opt_env->h;
1213 ir_node *block, *left, *right;
1214 ir_node *store, *load, *mem_proj;
1215 ir_node *addr_b, *addr_i;
1216 int need_exchange_on_fail = 0;
1217 ia32_am_type_t am_support;
1218 ia32_am_cand_t cand;
1219 ia32_am_cand_t orig_cand;
1221 int source_possible;
1222 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1224 if (!is_ia32_irn(irn) || is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn))
1226 if (is_ia32_Lea(irn))
1229 am_support = get_ia32_am_support(irn);
1230 block = get_nodes_block(irn);
1232 DBG((mod, LEVEL_1, "checking for AM\n"));
1234 /* fold following patterns: */
1235 /* - op -> Load into AMop with am_Source */
1237 /* - op is am_Source capable AND */
1238 /* - the Load is only used by this op AND */
1239 /* - the Load is in the same block */
1240 /* - Store -> op -> Load into AMop with am_Dest */
1242 /* - op is am_Dest capable AND */
1243 /* - the Store uses the same address as the Load AND */
1244 /* - the Load is only used by this op AND */
1245 /* - the Load and Store are in the same block AND */
1246 /* - nobody else uses the result of the op */
1247 if (get_ia32_am_support(irn) == ia32_am_None)
1250 cand = is_am_candidate(cg, h, block, irn);
1251 if (cand == IA32_AM_CAND_NONE)
1255 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1257 left = get_irn_n(irn, 2);
1258 if (get_irn_arity(irn) == 4) {
1259 /* it's an "unary" operation */
1261 assert(cand == IA32_AM_CAND_BOTH);
1263 right = get_irn_n(irn, 3);
1266 dest_possible = am_support & ia32_am_Dest ? 1 : 0;
1267 source_possible = am_support & ia32_am_Source ? 1 : 0;
1269 if (dest_possible) {
1274 /* we should only have 1 user which is a store */
1275 if (ia32_get_irn_n_edges(irn) == 1) {
1276 ir_node *succ = get_edge_src_irn(get_irn_out_edge_first(irn));
1278 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1280 addr_b = get_irn_n(store, 0);
1281 addr_i = get_irn_n(store, 1);
1285 if (store == NULL) {
1290 if (dest_possible) {
1291 /* normalize nodes, we need the interesting load on the left side */
1292 if (cand & IA32_AM_CAND_RIGHT) {
1293 load = get_Proj_pred(right);
1294 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1295 exchange_left_right(irn, &left, &right, 3, 2);
1296 need_exchange_on_fail ^= 1;
1297 if (cand == IA32_AM_CAND_RIGHT)
1298 cand = IA32_AM_CAND_LEFT;
1303 if (dest_possible) {
1304 if(cand & IA32_AM_CAND_LEFT && is_Proj(left)) {
1305 load = get_Proj_pred(left);
1307 #ifndef AGGRESSIVE_AM
1308 /* we have to be the only user of the load */
1309 if (get_irn_n_edges(left) > 1) {
1318 if (dest_possible) {
1319 /* the store has to use the loads memory or the same memory
1321 ir_node *loadmem = get_irn_n(load, 2);
1322 ir_node *storemem = get_irn_n(store, 3);
1323 assert(get_irn_mode(loadmem) == mode_M);
1324 assert(get_irn_mode(storemem) == mode_M);
1325 if(storemem != loadmem || !is_Proj(storemem)
1326 || get_Proj_pred(storemem) != load) {
1331 if (dest_possible) {
1332 /* Compare Load and Store address */
1333 if (!load_store_addr_is_equal(load, store, addr_b, addr_i))
1337 if (dest_possible) {
1338 /* all conditions fullfilled, do the transformation */
1339 assert(cand & IA32_AM_CAND_LEFT);
1341 /* set new base, index and attributes */
1342 set_irn_n(irn, 0, addr_b);
1343 set_irn_n(irn, 1, addr_i);
1344 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1345 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1346 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1347 set_ia32_op_type(irn, ia32_AddrModeD);
1348 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1349 if(is_ia32_use_frame(load))
1350 set_ia32_use_frame(irn);
1351 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1353 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1354 if (is_ia32_am_sc_sign(load))
1355 set_ia32_am_sc_sign(irn);
1357 if (is_ia32_use_frame(load))
1358 set_ia32_use_frame(irn);
1360 /* connect to Load memory and disconnect Load */
1361 if (get_irn_arity(irn) == 5) {
1363 set_irn_n(irn, 4, get_irn_n(load, 2));
1364 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1367 set_irn_n(irn, 3, get_irn_n(load, 2));
1368 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1371 set_irn_mode(irn, mode_M);
1373 /* connect the memory Proj of the Store to the op */
1374 mem_proj = ia32_get_proj_for_mode(store, mode_M);
1375 edges_reroute(mem_proj, irn, irg);
1377 /* clear remat flag */
1378 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1380 try_remove_from_sched(load);
1381 try_remove_from_sched(store);
1382 DBG_OPT_AM_D(load, store, irn);
1384 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1385 need_exchange_on_fail = 0;
1386 source_possible = 0;
1389 if (source_possible) {
1390 /* normalize ops, we need the load on the right */
1391 if(cand == IA32_AM_CAND_LEFT) {
1392 if(node_is_ia32_comm(irn)) {
1393 exchange_left_right(irn, &left, &right, 3, 2);
1394 need_exchange_on_fail ^= 1;
1395 cand = IA32_AM_CAND_RIGHT;
1397 source_possible = 0;
1402 if (source_possible) {
1403 /* all conditions fullfilled, do transform */
1404 assert(cand & IA32_AM_CAND_RIGHT);
1405 load = get_Proj_pred(right);
1407 if(get_irn_n_edges(load) > 1) {
1408 source_possible = 0;
1412 if (source_possible) {
1413 addr_b = get_irn_n(load, 0);
1414 addr_i = get_irn_n(load, 1);
1416 /* set new base, index and attributes */
1417 set_irn_n(irn, 0, addr_b);
1418 set_irn_n(irn, 1, addr_i);
1419 add_ia32_am_offs_int(irn, get_ia32_am_offs_int(load));
1420 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1421 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1422 set_ia32_op_type(irn, ia32_AddrModeS);
1423 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1424 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1426 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1427 if (is_ia32_am_sc_sign(load))
1428 set_ia32_am_sc_sign(irn);
1430 /* clear remat flag */
1431 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1433 if (is_ia32_use_frame(load))
1434 set_ia32_use_frame(irn);
1436 /* connect to Load memory and disconnect Load */
1437 if (get_irn_arity(irn) == 5) {
1439 set_irn_n(irn, 3, ia32_get_admissible_noreg(cg, irn, 3));
1440 set_irn_n(irn, 4, get_irn_n(load, 2));
1442 assert(get_irn_arity(irn) == 4);
1444 set_irn_n(irn, 2, ia32_get_admissible_noreg(cg, irn, 2));
1445 set_irn_n(irn, 3, get_irn_n(load, 2));
1448 DBG_OPT_AM_S(load, irn);
1450 /* If Load has a memory Proj, connect it to the op */
1451 mem_proj = ia32_get_proj_for_mode(load, mode_M);
1452 if (mem_proj != NULL) {
1454 ir_mode *mode = get_irn_mode(irn);
1456 res_proj = new_rd_Proj(get_irn_dbg_info(irn), irg,
1457 get_nodes_block(irn), new_Unknown(mode_T),
1459 set_irn_mode(irn, mode_T);
1460 edges_reroute(irn, res_proj, irg);
1461 set_Proj_pred(res_proj, irn);
1463 set_Proj_pred(mem_proj, irn);
1464 set_Proj_proj(mem_proj, 1);
1466 if(sched_is_scheduled(irn)) {
1467 sched_add_after(irn, res_proj);
1468 sched_add_after(irn, mem_proj);
1472 if(get_irn_n_edges(load) == 0) {
1473 try_remove_from_sched(load);
1475 need_exchange_on_fail = 0;
1477 DB((mod, LEVEL_1, "merged with %+F into source AM\n", load));
1480 /* was exchanged but optimize failed: exchange back */
1481 if (need_exchange_on_fail) {
1482 exchange_left_right(irn, &left, &right, 3, 2);
1487 * Performs address mode optimization.
1489 void ia32_optimize_addressmode(ia32_code_gen_t *cg) {
1490 /* if we are supposed to do AM or LEA optimization: recalculate edges */
1491 if (cg->opt & (IA32_OPT_DOAM | IA32_OPT_LEA)) {
1492 edges_deactivate(cg->irg);
1493 edges_activate(cg->irg);
1496 /* no optimizations at all */
1500 /* beware: we cannot optimize LEA and AM in one run because */
1501 /* LEA optimization adds new nodes to the irg which */
1502 /* invalidates the phase data */
1504 if (cg->opt & IA32_OPT_LEA) {
1505 irg_walk_blkwise_graph(cg->irg, NULL, optimize_lea, cg);
1509 be_dump(cg->irg, "-lea", dump_ir_block_graph_sched);
1511 if (cg->opt & IA32_OPT_DOAM) {
1512 /* we need height information for am optimization */
1513 heights_t *h = heights_new(cg->irg);
1514 ia32_am_opt_env_t env;
1519 irg_walk_blkwise_graph(cg->irg, NULL, optimize_am, &env);