8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
21 #include "ia32_transform.h"
22 #include "ia32_dbg_stat.h"
25 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
27 typedef int is_op_func_t(const ir_node *n);
30 * checks if a node represents the NOREG value
32 static int be_is_NoReg(ia32_code_gen_t *cg, const ir_node *irn) {
33 be_abi_irg_t *babi = cg->birg->abi;
34 const arch_register_t *fp_noreg = USE_SSE2(cg) ?
35 &ia32_xmm_regs[REG_XMM_NOREG] : &ia32_vfp_regs[REG_VFP_NOREG];
37 return (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_GP_NOREG]) == irn) ||
38 (be_abi_get_callee_save_irn(babi, fp_noreg) == irn);
43 /*************************************************
46 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
47 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
48 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
49 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
51 *************************************************/
54 * creates a unique ident by adding a number to a tag
56 * @param tag the tag string, must contain a %d if a number
59 static ident *unique_id(const char *tag)
61 static unsigned id = 0;
64 snprintf(str, sizeof(str), tag, ++id);
65 return new_id_from_str(str);
71 * Transforms a SymConst.
73 * @param mod the debug module
74 * @param block the block the new node should belong to
75 * @param node the ir SymConst node
76 * @param mode mode of the SymConst
77 * @return the created ia32 Const node
79 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
81 dbg_info *dbg = env->dbg;
82 ir_mode *mode = env->mode;
83 ir_graph *irg = env->irg;
84 ir_node *block = env->block;
86 if (mode_is_float(mode)) {
88 if (USE_SSE2(env->cg))
89 cnst = new_rd_ia32_xConst(dbg, irg, block, get_irg_no_mem(irg), mode);
91 cnst = new_rd_ia32_vfConst(dbg, irg, block, get_irg_no_mem(irg), mode);
94 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), mode);
96 set_ia32_Const_attr(cnst, env->irn);
102 * Get a primitive type for a mode.
104 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
106 pmap_entry *e = pmap_find(types, mode);
111 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
112 res = new_type_primitive(new_id_from_str(buf), mode);
113 pmap_insert(types, mode, res);
121 * Get an entity that is initialized with a tarval
123 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
125 tarval *tv = get_Const_tarval(cnst);
126 pmap_entry *e = pmap_find(cg->isa->tv_ent, tv);
131 ir_mode *mode = get_irn_mode(cnst);
132 ir_type *tp = get_Const_type(cnst);
133 if (tp == firm_unknown_type)
134 tp = get_prim_type(cg->isa->types, mode);
136 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
138 set_entity_ld_ident(res, get_entity_ident(res));
139 set_entity_visibility(res, visibility_local);
140 set_entity_variability(res, variability_constant);
141 set_entity_allocation(res, allocation_static);
143 /* we create a new entity here: It's initialization must resist on the
145 rem = current_ir_graph;
146 current_ir_graph = get_const_code_irg();
147 set_atomic_ent_value(res, new_Const_type(tv, tp));
148 current_ir_graph = rem;
150 pmap_insert(cg->isa->tv_ent, tv, res);
158 * Transforms a Const.
160 * @param mod the debug module
161 * @param block the block the new node should belong to
162 * @param node the ir Const node
163 * @param mode mode of the Const
164 * @return the created ia32 Const node
166 static ir_node *gen_Const(ia32_transform_env_t *env) {
169 ir_graph *irg = env->irg;
170 ir_node *block = env->block;
171 ir_node *node = env->irn;
172 dbg_info *dbg = env->dbg;
173 ir_mode *mode = env->mode;
175 if (mode_is_float(mode)) {
177 if (! USE_SSE2(env->cg)) {
178 cnst_classify_t clss = classify_Const(node);
180 if (clss == CNST_NULL)
181 return new_rd_ia32_vfldz(dbg, irg, block, mode);
182 else if (clss == CNST_ONE)
183 return new_rd_ia32_vfld1(dbg, irg, block, mode);
185 sym.entity_p = get_entity_for_tv(env->cg, node);
187 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
189 cnst = gen_SymConst(env);
192 cnst = new_rd_ia32_Const(dbg, irg, block, get_irg_no_mem(irg), get_irn_mode(node));
193 set_ia32_Const_attr(cnst, node);
201 * Transforms (all) Const's into ia32_Const and places them in the
202 * block where they are used (or in the cfg-pred Block in case of Phi's).
203 * Additionally all reference nodes are changed into mode_Is nodes.
205 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
206 ia32_code_gen_t *cg = env;
207 ia32_transform_env_t tenv;
209 ir_node *pred, *cnst;
216 mode = get_irn_mode(irn);
218 /* transform all reference nodes into mode_Is nodes */
219 if (mode_is_reference(mode)) {
221 set_irn_mode(irn, mode);
224 tenv.block = get_nodes_block(irn);
227 DEBUG_ONLY(tenv.mod = cg->mod;)
229 /* Loop over all predecessors and check for Sym/Const nodes */
230 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
231 pred = get_irn_n(irn, i);
233 opc = get_irn_opcode(pred);
235 tenv.mode = get_irn_mode(pred);
236 tenv.dbg = get_irn_dbg_info(pred);
238 /* If it's a Phi, then we need to create the */
239 /* new Const in it's predecessor block */
241 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
244 /* put the const into the block where the original const was */
245 if (! (cg->opt & IA32_OPT_PLACECNST)) {
246 tenv.block = get_nodes_block(pred);
251 cnst = gen_Const(&tenv);
254 cnst = gen_SymConst(&tenv);
260 /* if we found a const, then set it */
262 set_irn_n(irn, i, cnst);
269 /********************************************************************************************************
270 * _____ _ _ ____ _ _ _ _ _
271 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
272 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
273 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
274 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
275 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
278 ********************************************************************************************************/
281 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
284 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
285 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
289 * Checks for potential CJmp/CJmpAM optimization candidates.
291 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
292 ir_node *cand = NULL;
293 ir_node *prev = sched_prev(irn);
295 if (is_Block(prev)) {
296 if (get_Block_n_cfgpreds(prev) == 1)
297 prev = get_Block_cfgpred(prev, 0);
302 /* The predecessor must be a ProjX. */
303 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
304 prev = get_Proj_pred(prev);
306 if (is_op_func(prev))
313 static int is_TestJmp_cand(const ir_node *irn) {
314 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
318 * Checks if two consecutive arguments of cand matches
319 * the two arguments of irn (TestJmp).
321 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
322 ir_node *in1 = get_irn_n(irn, 0);
323 ir_node *in2 = get_irn_n(irn, 1);
324 int i, n = get_irn_arity(cand);
327 for (i = 0; i < n - 1; i++) {
328 if (get_irn_n(cand, i) == in1 &&
329 get_irn_n(cand, i + 1) == in2)
337 return ia32_cnst_compare(cand, irn);
343 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
345 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
346 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
349 /* we found a possible candidate */
350 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
353 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
355 if (is_ia32_And(cand))
356 set_irn_op(irn, op_ia32_CJmpAM);
358 set_irn_op(irn, op_ia32_CJmp);
360 DB((cg->mod, LEVEL_1, "%+F\n", irn));
364 static int is_CondJmp_cand(const ir_node *irn) {
365 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
369 * Checks if the arguments of cand are the same of irn.
371 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
372 int i, n = get_irn_arity(cand);
375 for (i = 0; i < n; i++) {
376 if (get_irn_n(cand, i) != get_irn_n(irn, i)) {
383 return ia32_cnst_compare(cand, irn);
389 * Tries to replace a CondJmp by a CJmpAM
391 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
392 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
395 /* we found a possible candidate */
396 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
399 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
402 set_irn_op(irn, op_ia32_CJmpAM);
404 DB((cg->mod, LEVEL_1, "%+F\n", irn));
409 * Creates a Push from Store(IncSP(gp_reg_size))
411 static void ia32_create_Push(ir_node *irn, ia32_code_gen_t *cg) {
412 ir_node *sp = get_irn_n(irn, 0);
413 ir_node *val, *next, *push, *bl, *proj_M, *proj_res, *old_proj_M;
414 const ir_edge_t *edge;
416 if (get_ia32_am_offs(irn) || !be_is_IncSP(sp))
419 if (arch_get_irn_register(cg->arch_env, get_irn_n(irn, 1)) !=
420 &ia32_gp_regs[REG_GP_NOREG])
423 val = get_irn_n(irn, 2);
424 if (mode_is_float(get_irn_mode(val)))
427 if (be_get_IncSP_direction(sp) != be_stack_dir_expand ||
428 be_get_IncSP_offset(sp) != get_mode_size_bytes(ia32_reg_classes[CLASS_ia32_gp].mode))
431 /* ok, translate into Push */
432 edge = get_irn_out_edge_first(irn);
433 old_proj_M = get_edge_src_irn(edge);
435 next = sched_next(irn);
439 bl = get_nodes_block(irn);
440 push = new_rd_ia32_Push(NULL, current_ir_graph, bl,
441 be_get_IncSP_pred(sp), val, be_get_IncSP_mem(sp));
442 proj_res = new_r_Proj(current_ir_graph, bl, push, get_irn_mode(sp), pn_ia32_Push_stack);
443 proj_M = new_r_Proj(current_ir_graph, bl, push, mode_M, pn_ia32_Push_M);
445 /* copy a possible constant from the store */
446 set_ia32_id_cnst(push, get_ia32_id_cnst(irn));
447 set_ia32_immop_type(push, get_ia32_immop_type(irn));
449 /* the push must have SP out register */
450 arch_set_irn_register(cg->arch_env, push, arch_get_irn_register(cg->arch_env, sp));
452 exchange(old_proj_M, proj_M);
453 exchange(sp, proj_res);
454 sched_add_before(next, push);
455 sched_add_after(push, proj_res);
459 * Creates a Pop from IncSP(Load(sp))
461 static void ia32_create_Pop(ir_node *irn, ia32_code_gen_t *cg) {
462 ir_node *old_proj_M = be_get_IncSP_mem(irn);
463 ir_node *load = skip_Proj(old_proj_M);
464 ir_node *old_proj_res = NULL;
465 ir_node *bl, *pop, *next, *proj_res, *proj_sp, *proj_M;
466 const ir_edge_t *edge;
467 const arch_register_t *reg, *sp;
469 if (! is_ia32_Load(load) || get_ia32_am_offs(load))
472 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 1)) !=
473 &ia32_gp_regs[REG_GP_NOREG])
475 if (arch_get_irn_register(cg->arch_env, get_irn_n(load, 0)) != cg->isa->arch_isa.sp)
478 /* ok, translate into pop */
479 foreach_out_edge(load, edge) {
480 ir_node *succ = get_edge_src_irn(edge);
481 if (succ != old_proj_M) {
486 if (! old_proj_res) {
488 return; /* should not happen */
491 bl = get_nodes_block(load);
493 /* IncSP is typically scheduled after the load, so remove it first */
495 next = sched_next(old_proj_res);
496 sched_remove(old_proj_res);
499 reg = arch_get_irn_register(cg->arch_env, load);
500 sp = arch_get_irn_register(cg->arch_env, irn);
502 pop = new_rd_ia32_Pop(NULL, current_ir_graph, bl, get_irn_n(irn, 0), get_irn_n(load, 2));
503 proj_res = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(old_proj_res), pn_ia32_Pop_res);
504 proj_sp = new_r_Proj(current_ir_graph, bl, pop, get_irn_mode(irn), pn_ia32_Pop_stack);
505 proj_M = new_r_Proj(current_ir_graph, bl, pop, mode_M, pn_ia32_Pop_M);
507 exchange(old_proj_M, proj_M);
508 exchange(old_proj_res, proj_res);
509 exchange(irn, proj_sp);
511 arch_set_irn_register(cg->arch_env, proj_res, reg);
512 arch_set_irn_register(cg->arch_env, proj_sp, sp);
514 sched_add_before(next, proj_sp);
515 sched_add_before(proj_sp, proj_res);
516 sched_add_before(proj_res,pop);
520 * Tries to optimize two following IncSP.
522 static void ia32_optimize_IncSP(ir_node *irn, ia32_code_gen_t *cg) {
523 ir_node *prev = be_get_IncSP_pred(irn);
524 int real_uses = get_irn_n_edges(prev);
526 if (be_is_IncSP(prev) && real_uses == 1) {
527 /* first IncSP has only one IncSP user, kill the first one */
528 unsigned prev_offs = be_get_IncSP_offset(prev);
529 be_stack_dir_t prev_dir = be_get_IncSP_direction(prev);
530 unsigned curr_offs = be_get_IncSP_offset(irn);
531 be_stack_dir_t curr_dir = be_get_IncSP_direction(irn);
533 int new_ofs = prev_offs * (prev_dir == be_stack_dir_expand ? -1 : +1) +
534 curr_offs * (curr_dir == be_stack_dir_expand ? -1 : +1);
538 curr_dir = be_stack_dir_expand;
541 curr_dir = be_stack_dir_shrink;
542 be_set_IncSP_offset(prev, 0);
543 be_set_IncSP_offset(irn, (unsigned)new_ofs);
544 be_set_IncSP_direction(irn, curr_dir);
546 /* Omit the optimized IncSP */
547 be_set_IncSP_pred(irn, be_get_IncSP_pred(prev));
552 * Performs Peephole Optimizations.
554 void ia32_peephole_optimization(ir_node *irn, void *env) {
555 ia32_code_gen_t *cg = env;
557 if (is_ia32_TestJmp(irn))
558 ia32_optimize_TestJmp(irn, cg);
559 else if (is_ia32_CondJmp(irn))
560 ia32_optimize_CondJmp(irn, cg);
561 else if (be_is_IncSP(irn))
562 ia32_optimize_IncSP(irn, cg);
563 else if (is_ia32_Store(irn))
564 ia32_create_Push(irn, cg);
569 /******************************************************************
571 * /\ | | | | | \/ | | |
572 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
573 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
574 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
575 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
577 ******************************************************************/
579 static int node_is_ia32_comm(const ir_node *irn) {
580 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
583 static int ia32_get_irn_n_edges(const ir_node *irn) {
584 const ir_edge_t *edge;
587 foreach_out_edge(irn, edge) {
595 * Returns the first mode_M Proj connected to irn.
597 static ir_node *get_mem_proj(const ir_node *irn) {
598 const ir_edge_t *edge;
601 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
603 foreach_out_edge(irn, edge) {
604 src = get_edge_src_irn(edge);
606 assert(is_Proj(src) && "Proj expected");
608 if (get_irn_mode(src) == mode_M)
616 * Returns the first Proj with mode != mode_M connected to irn.
618 static ir_node *get_res_proj(const ir_node *irn) {
619 const ir_edge_t *edge;
622 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
624 foreach_out_edge(irn, edge) {
625 src = get_edge_src_irn(edge);
627 assert(is_Proj(src) && "Proj expected");
629 if (get_irn_mode(src) != mode_M)
637 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
639 * @param pred The node to be checked
640 * @param is_op_func The check-function
641 * @return 1 if conditions are fulfilled, 0 otherwise
643 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
644 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
652 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
653 * and if the predecessor is in block bl.
655 * @param bl The block
656 * @param pred The node to be checked
657 * @param is_op_func The check-function
658 * @return 1 if conditions are fulfilled, 0 otherwise
660 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
661 int (*is_op_func)(const ir_node *n))
664 pred = get_Proj_pred(pred);
665 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
676 * Checks if irn is a candidate for address calculation or address mode.
678 * address calculation (AC):
679 * - none of the operand must be a Load within the same block OR
680 * - all Loads must have more than one user OR
681 * - the irn has a frame entity (it's a former FrameAddr)
684 * - at least one operand has to be a Load within the same block AND
685 * - the load must not have other users than the irn AND
686 * - the irn must not have a frame entity set
688 * @param block The block the Loads must/not be in
689 * @param irn The irn to check
690 * @param check_addr 1 if to check for address calculation, 0 otherwise
691 * return 1 if irn is a candidate for AC or AM, 0 otherwise
693 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
695 int n, is_cand = check_addr;
697 in = get_irn_n(irn, 2);
699 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
700 n = ia32_get_irn_n_edges(in);
701 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
704 in = get_irn_n(irn, 3);
706 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
707 n = ia32_get_irn_n_edges(in);
708 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
711 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
717 * Compares the base and index addr and the load/store entities
718 * and returns 1 if they are equal.
720 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
721 const ir_node *addr_b, const ir_node *addr_i)
723 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
724 entity *lent = get_ia32_frame_ent(load);
725 entity *sent = get_ia32_frame_ent(store);
726 ident *lid = get_ia32_am_sc(load);
727 ident *sid = get_ia32_am_sc(store);
728 char *loffs = get_ia32_am_offs(load);
729 char *soffs = get_ia32_am_offs(store);
731 /* are both entities set and equal? */
732 if (is_equal && (lent || sent))
733 is_equal = lent && sent && (lent == sent);
735 /* are address mode idents set and equal? */
736 if (is_equal && (lid || sid))
737 is_equal = lid && sid && (lid == sid);
739 /* are offsets set and equal */
740 if (is_equal && (loffs || soffs))
741 is_equal = loffs && soffs && strcmp(loffs, soffs) == 0;
743 /* are the load and the store of the same mode? */
744 is_equal = is_equal ? get_ia32_ls_mode(load) == get_ia32_ls_mode(store) : 0;
749 typedef enum _ia32_take_lea_attr {
750 IA32_LEA_ATTR_NONE = 0,
751 IA32_LEA_ATTR_BASE = (1 << 0),
752 IA32_LEA_ATTR_INDEX = (1 << 1),
753 IA32_LEA_ATTR_OFFS = (1 << 2),
754 IA32_LEA_ATTR_SCALE = (1 << 3),
755 IA32_LEA_ATTR_AMSC = (1 << 4),
756 IA32_LEA_ATTR_FENT = (1 << 5)
757 } ia32_take_lea_attr;
760 * Decides if we have to keep the LEA operand or if we can assimilate it.
762 static int do_new_lea(ir_node *irn, ir_node *base, ir_node *index, ir_node *lea,
763 int have_am_sc, ia32_code_gen_t *cg)
765 ir_node *lea_base = get_irn_n(lea, 0);
766 ir_node *lea_idx = get_irn_n(lea, 1);
767 entity *irn_ent = get_ia32_frame_ent(irn);
768 entity *lea_ent = get_ia32_frame_ent(lea);
770 int is_noreg_base = be_is_NoReg(cg, base);
771 int is_noreg_index = be_is_NoReg(cg, index);
772 ia32_am_flavour_t am_flav = get_ia32_am_flavour(lea);
774 /* If the Add and the LEA both have a different frame entity set: keep */
775 if (irn_ent && lea_ent && (irn_ent != lea_ent))
776 return IA32_LEA_ATTR_NONE;
777 else if (! irn_ent && lea_ent)
778 ret_val |= IA32_LEA_ATTR_FENT;
780 /* If the Add and the LEA both have already an address mode symconst: keep */
781 if (have_am_sc && get_ia32_am_sc(lea))
782 return IA32_LEA_ATTR_NONE;
783 else if (get_ia32_am_sc(lea))
784 ret_val |= IA32_LEA_ATTR_AMSC;
786 /* Check the different base-index combinations */
788 if (! is_noreg_base && ! is_noreg_index) {
789 /* Assimilate if base is the lea and the LEA is just a Base + Offset calculation */
790 if ((base == lea) && ! (am_flav & ia32_I ? 1 : 0)) {
791 if (am_flav & ia32_O)
792 ret_val |= IA32_LEA_ATTR_OFFS;
794 ret_val |= IA32_LEA_ATTR_BASE;
797 return IA32_LEA_ATTR_NONE;
799 else if (! is_noreg_base && is_noreg_index) {
800 /* Base is set but index not */
802 /* Base points to LEA: assimilate everything */
803 if (am_flav & ia32_O)
804 ret_val |= IA32_LEA_ATTR_OFFS;
805 if (am_flav & ia32_S)
806 ret_val |= IA32_LEA_ATTR_SCALE;
807 if (am_flav & ia32_I)
808 ret_val |= IA32_LEA_ATTR_INDEX;
810 ret_val |= IA32_LEA_ATTR_BASE;
812 else if (am_flav & ia32_B ? 0 : 1) {
813 /* Base is not the LEA but the LEA is an index only calculation: assimilate */
814 if (am_flav & ia32_O)
815 ret_val |= IA32_LEA_ATTR_OFFS;
816 if (am_flav & ia32_S)
817 ret_val |= IA32_LEA_ATTR_SCALE;
819 ret_val |= IA32_LEA_ATTR_INDEX;
822 return IA32_LEA_ATTR_NONE;
824 else if (is_noreg_base && ! is_noreg_index) {
825 /* Index is set but not base */
827 /* Index points to LEA: assimilate everything */
828 if (am_flav & ia32_O)
829 ret_val |= IA32_LEA_ATTR_OFFS;
830 if (am_flav & ia32_S)
831 ret_val |= IA32_LEA_ATTR_SCALE;
832 if (am_flav & ia32_B)
833 ret_val |= IA32_LEA_ATTR_BASE;
835 ret_val |= IA32_LEA_ATTR_INDEX;
837 else if (am_flav & ia32_I ? 0 : 1) {
838 /* Index is not the LEA but the LEA is a base only calculation: assimilate */
839 if (am_flav & ia32_O)
840 ret_val |= IA32_LEA_ATTR_OFFS;
841 if (am_flav & ia32_S)
842 ret_val |= IA32_LEA_ATTR_SCALE;
844 ret_val |= IA32_LEA_ATTR_BASE;
847 return IA32_LEA_ATTR_NONE;
850 assert(0 && "There must have been set base or index");
858 * Folds Add or Sub to LEA if possible
860 static ir_node *fold_addr(ia32_code_gen_t *cg, ir_node *irn, ir_node *noreg) {
861 ir_graph *irg = get_irn_irg(irn);
862 dbg_info *dbg = get_irn_dbg_info(irn);
863 ir_node *block = get_nodes_block(irn);
865 ir_node *shift = NULL;
866 ir_node *lea_o = NULL;
869 const char *offs_cnst = NULL;
870 char *offs_lea = NULL;
877 entity *lea_ent = NULL;
878 ir_node *left, *right, *temp;
879 ir_node *base, *index;
880 ia32_am_flavour_t am_flav;
881 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
883 if (is_ia32_Add(irn))
886 left = get_irn_n(irn, 2);
887 right = get_irn_n(irn, 3);
889 /* "normalize" arguments in case of add with two operands */
890 if (isadd && ! be_is_NoReg(cg, right)) {
891 /* put LEA == ia32_am_O as right operand */
892 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
893 set_irn_n(irn, 2, right);
894 set_irn_n(irn, 3, left);
900 /* put LEA != ia32_am_O as left operand */
901 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
902 set_irn_n(irn, 2, right);
903 set_irn_n(irn, 3, left);
909 /* put SHL as left operand iff left is NOT a LEA */
910 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
911 set_irn_n(irn, 2, right);
912 set_irn_n(irn, 3, left);
925 /* check for operation with immediate */
926 if (is_ia32_ImmConst(irn)) {
927 DBG((mod, LEVEL_1, "\tfound op with imm const"));
929 offs_cnst = get_ia32_cnst(irn);
932 else if (is_ia32_ImmSymConst(irn)) {
933 DBG((mod, LEVEL_1, "\tfound op with imm symconst"));
937 am_sc = get_ia32_id_cnst(irn);
938 am_sc_sign = is_ia32_am_sc_sign(irn);
941 /* determine the operand which needs to be checked */
942 if (be_is_NoReg(cg, right)) {
949 /* check if right operand is AMConst (LEA with ia32_am_O) */
950 /* but we can only eat it up if there is no other symconst */
951 /* because the linker won't accept two symconsts */
952 if (! have_am_sc && is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
953 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
955 offs_lea = get_ia32_am_offs(temp);
956 am_sc = get_ia32_am_sc(temp);
957 am_sc_sign = is_ia32_am_sc_sign(temp);
964 /* default for add -> make right operand to index */
968 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
970 /* determine the operand which needs to be checked */
972 if (is_ia32_Lea(left)) {
976 /* check for SHL 1,2,3 */
977 if (pred_is_specific_node(temp, is_ia32_Shl)) {
978 temp = get_Proj_pred(temp);
981 if (get_ia32_Immop_tarval(temp)) {
982 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
985 index = get_irn_n(temp, 2);
987 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
997 if (! be_is_NoReg(cg, index)) {
998 /* if we have index, but left == right -> no base */
1002 else if (! is_ia32_Lea(left) && (index != right)) {
1003 /* index != right -> we found a good Shl */
1004 /* left != LEA -> this Shl was the left operand */
1005 /* -> base is right operand */
1011 /* Try to assimilate a LEA as left operand */
1012 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
1013 /* check if we can assimilate the LEA */
1014 int take_attr = do_new_lea(irn, base, index, left, have_am_sc, cg);
1016 if (take_attr == IA32_LEA_ATTR_NONE) {
1017 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
1020 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
1021 lea = left; /* for statistics */
1023 if (take_attr & IA32_LEA_ATTR_OFFS)
1024 offs = get_ia32_am_offs(left);
1026 if (take_attr & IA32_LEA_ATTR_AMSC) {
1027 am_sc = get_ia32_am_sc(left);
1029 am_sc_sign = is_ia32_am_sc_sign(left);
1032 if (take_attr & IA32_LEA_ATTR_SCALE)
1033 scale = get_ia32_am_scale(left);
1035 if (take_attr & IA32_LEA_ATTR_BASE)
1036 base = get_irn_n(left, 0);
1038 if (take_attr & IA32_LEA_ATTR_INDEX)
1039 index = get_irn_n(left, 1);
1041 if (take_attr & IA32_LEA_ATTR_FENT)
1042 lea_ent = get_ia32_frame_ent(left);
1046 /* ok, we can create a new LEA */
1048 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
1050 /* add the old offset of a previous LEA */
1052 add_ia32_am_offs(res, offs);
1055 /* add the new offset */
1058 add_ia32_am_offs(res, offs_cnst);
1061 add_ia32_am_offs(res, offs_lea);
1065 /* either lea_O-cnst, -cnst or -lea_O */
1068 add_ia32_am_offs(res, offs_lea);
1071 sub_ia32_am_offs(res, offs_cnst);
1074 sub_ia32_am_offs(res, offs_lea);
1078 /* set the address mode symconst */
1080 set_ia32_am_sc(res, am_sc);
1082 set_ia32_am_sc_sign(res);
1085 /* copy the frame entity (could be set in case of Add */
1086 /* which was a FrameAddr) */
1088 set_ia32_frame_ent(res, lea_ent);
1090 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
1092 if (get_ia32_frame_ent(res))
1093 set_ia32_use_frame(res);
1096 set_ia32_am_scale(res, scale);
1098 am_flav = ia32_am_N;
1099 /* determine new am flavour */
1100 if (offs || offs_cnst || offs_lea) {
1103 if (! be_is_NoReg(cg, base)) {
1106 if (! be_is_NoReg(cg, index)) {
1112 set_ia32_am_flavour(res, am_flav);
1114 set_ia32_op_type(res, ia32_AddrModeS);
1116 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, irn));
1118 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
1120 /* we will exchange it, report here before the Proj is created */
1121 if (shift && lea && lea_o)
1122 DBG_OPT_LEA4(irn, lea_o, lea, shift, res);
1123 else if (shift && lea)
1124 DBG_OPT_LEA3(irn, lea, shift, res);
1125 else if (shift && lea_o)
1126 DBG_OPT_LEA3(irn, lea_o, shift, res);
1127 else if (lea && lea_o)
1128 DBG_OPT_LEA3(irn, lea_o, lea, res);
1130 DBG_OPT_LEA2(irn, shift, res);
1132 DBG_OPT_LEA2(irn, lea, res);
1134 DBG_OPT_LEA2(irn, lea_o, res);
1136 DBG_OPT_LEA1(irn, res);
1138 /* get the result Proj of the Add/Sub */
1139 irn = get_res_proj(irn);
1141 assert(irn && "Couldn't find result proj");
1143 /* exchange the old op with the new LEA */
1152 * Merges a Load/Store node with a LEA.
1153 * @param irn The Load/Store node
1154 * @param lea The LEA
1156 static void merge_loadstore_lea(ir_node *irn, ir_node *lea) {
1157 entity *irn_ent = get_ia32_frame_ent(irn);
1158 entity *lea_ent = get_ia32_frame_ent(lea);
1160 /* If the irn and the LEA both have a different frame entity set: do not merge */
1161 if (irn_ent && lea_ent && (irn_ent != lea_ent))
1163 else if (! irn_ent && lea_ent) {
1164 set_ia32_frame_ent(irn, lea_ent);
1165 set_ia32_use_frame(irn);
1168 /* get the AM attributes from the LEA */
1169 add_ia32_am_offs(irn, get_ia32_am_offs(lea));
1170 set_ia32_am_scale(irn, get_ia32_am_scale(lea));
1171 set_ia32_am_flavour(irn, get_ia32_am_flavour(lea));
1173 set_ia32_am_sc(irn, get_ia32_am_sc(lea));
1174 if (is_ia32_am_sc_sign(lea))
1175 set_ia32_am_sc_sign(irn);
1177 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
1179 /* set base and index */
1180 set_irn_n(irn, 0, get_irn_n(lea, 0));
1181 set_irn_n(irn, 1, get_irn_n(lea, 1));
1183 /* clear remat flag */
1184 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1186 if (is_ia32_Ld(irn))
1187 DBG_OPT_LOAD_LEA(lea, irn);
1189 DBG_OPT_STORE_LEA(lea, irn);
1194 * Sets new_right index of irn to right and new_left index to left.
1195 * Also exchange left and right
1197 static void exchange_left_right(ir_node *irn, ir_node **left, ir_node **right, int new_left, int new_right) {
1200 set_irn_n(irn, new_right, *right);
1201 set_irn_n(irn, new_left, *left);
1207 /* this is only needed for Compares, but currently ALL nodes
1208 * have this attribute :-) */
1209 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1213 * Optimizes a pattern around irn to address mode if possible.
1215 void ia32_optimize_am(ir_node *irn, void *env) {
1216 ia32_code_gen_t *cg = env;
1220 ir_node *block, *noreg_gp, *noreg_fp;
1221 ir_node *left, *right, *temp;
1222 ir_node *store, *load, *mem_proj;
1223 ir_node *succ, *addr_b, *addr_i;
1224 int check_am_src = 0;
1225 int need_exchange_on_fail = 0;
1226 DEBUG_ONLY(firm_dbg_module_t *mod = cg->mod;)
1228 if (! is_ia32_irn(irn))
1231 dbg = get_irn_dbg_info(irn);
1232 mode = get_irn_mode(irn);
1233 block = get_nodes_block(irn);
1234 noreg_gp = ia32_new_NoReg_gp(cg);
1235 noreg_fp = ia32_new_NoReg_fp(cg);
1237 DBG((mod, LEVEL_1, "checking for AM\n"));
1239 /* 1st part: check for address calculations and transform the into Lea */
1241 /* Following cases can occur: */
1242 /* - Sub (l, imm) -> LEA [base - offset] */
1243 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
1244 /* - Add (l, imm) -> LEA [base + offset] */
1245 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
1246 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
1247 /* - Add (l, r) -> LEA [base + index * scale] */
1248 /* with scale > 1 iff l/r == shl (1,2,3) */
1250 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
1251 left = get_irn_n(irn, 2);
1252 right = get_irn_n(irn, 3);
1254 /* Do not try to create a LEA if one of the operands is a Load. */
1255 /* check is irn is a candidate for address calculation */
1256 if (is_candidate(block, irn, 1)) {
1257 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
1258 res = fold_addr(cg, irn, noreg_gp);
1261 DB((mod, LEVEL_1, "transformed into %+F\n", res));
1263 DB((mod, LEVEL_1, "not transformed\n"));
1267 /* 2nd part: fold following patterns: */
1268 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
1269 /* - Store -> LEA into Store } it might be better to keep the LEA */
1270 /* - op -> Load into AMop with am_Source */
1272 /* - op is am_Source capable AND */
1273 /* - the Load is only used by this op AND */
1274 /* - the Load is in the same block */
1275 /* - Store -> op -> Load into AMop with am_Dest */
1277 /* - op is am_Dest capable AND */
1278 /* - the Store uses the same address as the Load AND */
1279 /* - the Load is only used by this op AND */
1280 /* - the Load and Store are in the same block AND */
1281 /* - nobody else uses the result of the op */
1283 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
1284 /* 1st: check for Load/Store -> LEA */
1285 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
1286 left = get_irn_n(irn, 0);
1288 if (is_ia32_Lea(left)) {
1289 const ir_edge_t *edge, *ne;
1292 /* merge all Loads/Stores connected to this LEA with the LEA */
1293 foreach_out_edge_safe(left, edge, ne) {
1294 src = get_edge_src_irn(edge);
1296 if (src && (is_ia32_Ld(src) || is_ia32_St(src) || is_ia32_Store8Bit(src))) {
1297 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
1298 merge_loadstore_lea(src, left);
1303 /* check if the node is an address mode candidate */
1304 else if (is_candidate(block, irn, 0)) {
1305 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
1307 left = get_irn_n(irn, 2);
1308 if (get_irn_arity(irn) == 4) {
1309 /* it's an "unary" operation */
1313 right = get_irn_n(irn, 3);
1316 /* normalize commutative ops */
1317 if (node_is_ia32_comm(irn)) {
1318 /* Assure that right operand is always a Load if there is one */
1319 /* because non-commutative ops can only use Dest AM if the right */
1320 /* operand is a load, so we only need to check right operand. */
1321 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1323 exchange_left_right(irn, &left, &right, 3, 2);
1324 need_exchange_on_fail = 1;
1328 /* check for Store -> op -> Load */
1330 /* Store -> op -> Load optimization is only possible if supported by op */
1331 /* and if right operand is a Load */
1332 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
1333 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
1336 /* An address mode capable op always has a result Proj. */
1337 /* If this Proj is used by more than one other node, we don't need to */
1338 /* check further, otherwise we check for Store and remember the address, */
1339 /* the Store points to. */
1341 succ = get_res_proj(irn);
1342 assert(succ && "Couldn't find result proj");
1348 /* now check for users and Store */
1349 if (ia32_get_irn_n_edges(succ) == 1) {
1350 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
1352 if (is_ia32_xStore(succ) || is_ia32_Store(succ)) {
1354 addr_b = get_irn_n(store, 0);
1355 addr_i = get_irn_n(store, 1);
1360 /* we found a Store as single user: Now check for Load */
1362 /* Extra check for commutative ops with two Loads */
1363 /* -> put the interesting Load right */
1364 if (node_is_ia32_comm(irn) &&
1365 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
1367 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
1368 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
1370 /* We exchange left and right, so it's easier to kill */
1371 /* the correct Load later and to handle unary operations. */
1372 set_irn_n(irn, 2, right);
1373 set_irn_n(irn, 3, left);
1379 /* this is only needed for Compares, but currently ALL nodes
1380 * have this attribute :-) */
1381 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1385 /* skip the Proj for easier access */
1386 load = get_Proj_pred(right);
1388 /* Compare Load and Store address */
1389 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
1390 /* Right Load is from same address, so we can */
1391 /* disconnect the Load and Store here */
1393 /* set new base, index and attributes */
1394 set_irn_n(irn, 0, addr_b);
1395 set_irn_n(irn, 1, addr_i);
1396 add_ia32_am_offs(irn, get_ia32_am_offs(load));
1397 set_ia32_am_scale(irn, get_ia32_am_scale(load));
1398 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
1399 set_ia32_op_type(irn, ia32_AddrModeD);
1400 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
1401 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
1403 set_ia32_am_sc(irn, get_ia32_am_sc(load));
1404 if (is_ia32_am_sc_sign(load))
1405 set_ia32_am_sc_sign(irn);
1407 if (is_ia32_use_frame(load))
1408 set_ia32_use_frame(irn);
1410 /* connect to Load memory and disconnect Load */
1411 if (get_irn_arity(irn) == 5) {
1413 set_irn_n(irn, 4, get_irn_n(load, 2));
1414 set_irn_n(irn, 3, noreg_gp);
1418 set_irn_n(irn, 3, get_irn_n(load, 2));
1419 set_irn_n(irn, 2, noreg_gp);
1422 /* connect the memory Proj of the Store to the op */
1423 mem_proj = get_mem_proj(store);
1424 set_Proj_pred(mem_proj, irn);
1425 set_Proj_proj(mem_proj, 1);
1427 /* clear remat flag */
1428 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1430 DBG_OPT_AM_D(load, store, irn);
1432 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1435 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1436 /* There was no store, check if we still can optimize for source address mode */
1439 } /* if (support AM Dest) */
1440 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1441 /* op doesn't support am AM Dest -> check for AM Source */
1445 /* was exchanged but optimize failed: exchange back */
1446 if (check_am_src && need_exchange_on_fail)
1447 exchange_left_right(irn, &left, &right, 3, 2);
1449 need_exchange_on_fail = 0;
1451 /* normalize commutative ops */
1452 if (check_am_src && node_is_ia32_comm(irn)) {
1453 /* Assure that left operand is always a Load if there is one */
1454 /* because non-commutative ops can only use Source AM if the */
1455 /* left operand is a Load, so we only need to check the left */
1456 /* operand afterwards. */
1457 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1458 exchange_left_right(irn, &left, &right, 3, 2);
1459 need_exchange_on_fail = 1;
1463 /* optimize op -> Load iff Load is only used by this op */
1464 /* and left operand is a Load which only used by this irn */
1466 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1467 (ia32_get_irn_n_edges(left) == 1))
1469 left = get_Proj_pred(left);
1471 addr_b = get_irn_n(left, 0);
1472 addr_i = get_irn_n(left, 1);
1474 /* set new base, index and attributes */
1475 set_irn_n(irn, 0, addr_b);
1476 set_irn_n(irn, 1, addr_i);
1477 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1478 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1479 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1480 set_ia32_op_type(irn, ia32_AddrModeS);
1481 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1482 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1484 set_ia32_am_sc(irn, get_ia32_am_sc(left));
1485 if (is_ia32_am_sc_sign(left))
1486 set_ia32_am_sc_sign(irn);
1488 /* clear remat flag */
1489 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1491 if (is_ia32_use_frame(left))
1492 set_ia32_use_frame(irn);
1494 /* connect to Load memory */
1495 if (get_irn_arity(irn) == 5) {
1497 set_irn_n(irn, 4, get_irn_n(left, 2));
1499 /* this is only needed for Compares, but currently ALL nodes
1500 * have this attribute :-) */
1501 set_ia32_pncode(irn, get_inversed_pnc(get_ia32_pncode(irn)));
1503 /* disconnect from Load */
1504 /* (make second op -> first, set second in to noreg) */
1505 set_irn_n(irn, 2, get_irn_n(irn, 3));
1506 set_irn_n(irn, 3, noreg_gp);
1510 set_irn_n(irn, 3, get_irn_n(left, 2));
1512 /* disconnect from Load */
1513 set_irn_n(irn, 2, noreg_gp);
1516 DBG_OPT_AM_S(left, irn);
1518 /* If Load has a memory Proj, connect it to the op */
1519 mem_proj = get_mem_proj(left);
1521 set_Proj_pred(mem_proj, irn);
1522 set_Proj_proj(mem_proj, 1);
1525 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));
1528 /* was exchanged but optimize failed: exchange back */
1529 if (need_exchange_on_fail)
1530 exchange_left_right(irn, &left, &right, 3, 2);