2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
31 #include "firm_types.h"
46 #include "bepeephole.h"
48 #include "ia32_new_nodes.h"
49 #include "ia32_optimize.h"
50 #include "bearch_ia32_t.h"
51 #include "gen_ia32_regalloc_if.h"
52 #include "ia32_common_transform.h"
53 #include "ia32_transform.h"
54 #include "ia32_dbg_stat.h"
55 #include "ia32_architecture.h"
57 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
59 static void copy_mark(const ir_node *old, ir_node *newn)
61 if (is_ia32_is_reload(old))
62 set_ia32_is_reload(newn);
63 if (is_ia32_is_spill(old))
64 set_ia32_is_spill(newn);
65 if (is_ia32_is_remat(old))
66 set_ia32_is_remat(newn);
69 typedef enum produces_flag_t {
72 produces_zero_in_carry
76 * Return which usable flag the given node produces about the result.
77 * That is zero (ZF) and sign(SF).
78 * We do not check for carry (CF) or overflow (OF).
80 * @param node the node to check
81 * @param pn the projection number of the used result
83 static produces_flag_t check_produces_zero_sign(ir_node *node, int pn)
86 const ia32_immediate_attr_t *imm_attr;
88 if (!is_ia32_irn(node))
89 return produces_no_flag;
91 switch (get_ia32_irn_opcode(node)) {
106 assert((int)n_ia32_ShlD_count == (int)n_ia32_ShrD_count);
107 count = get_irn_n(node, n_ia32_ShlD_count);
108 goto check_shift_amount;
113 assert((int)n_ia32_Shl_count == (int)n_ia32_Shr_count
114 && (int)n_ia32_Shl_count == (int)n_ia32_Sar_count);
115 count = get_irn_n(node, n_ia32_Shl_count);
117 /* when shift count is zero the flags are not affected, so we can only
118 * do this for constants != 0 */
119 if (!is_ia32_Immediate(count))
120 return produces_no_flag;
122 imm_attr = get_ia32_immediate_attr_const(count);
123 if (imm_attr->symconst != NULL)
124 return produces_no_flag;
125 if ((imm_attr->offset & 0x1f) == 0)
126 return produces_no_flag;
130 return pn == pn_ia32_Mul_res_high ?
131 produces_zero_in_carry : produces_no_flag;
134 return produces_no_flag;
137 return pn == pn_ia32_res ? produces_zero_sign : produces_no_flag;
141 * Replace Cmp(x, 0) by a Test(x, x)
143 static void peephole_ia32_Cmp(ir_node *const node)
147 ia32_immediate_attr_t const *imm;
153 ia32_attr_t const *attr;
156 arch_register_t const *reg;
157 ir_edge_t const *edge;
158 ir_edge_t const *tmp;
160 if (get_ia32_op_type(node) != ia32_Normal)
163 right = get_irn_n(node, n_ia32_Cmp_right);
164 if (!is_ia32_Immediate(right))
167 imm = get_ia32_immediate_attr_const(right);
168 if (imm->symconst != NULL || imm->offset != 0)
171 dbgi = get_irn_dbg_info(node);
172 irg = get_irn_irg(node);
173 block = get_nodes_block(node);
174 noreg = ia32_new_NoReg_gp(irg);
175 nomem = get_irg_no_mem(current_ir_graph);
176 op = get_irn_n(node, n_ia32_Cmp_left);
177 attr = get_ia32_attr(node);
178 ins_permuted = attr->data.ins_permuted;
180 if (is_ia32_Cmp(node)) {
181 test = new_bd_ia32_Test(dbgi, block, noreg, noreg, nomem,
182 op, op, ins_permuted);
184 test = new_bd_ia32_Test8Bit(dbgi, block, noreg, noreg, nomem,
185 op, op, ins_permuted);
187 set_ia32_ls_mode(test, get_ia32_ls_mode(node));
189 reg = arch_get_irn_register_out(node, pn_ia32_Cmp_eflags);
190 arch_set_irn_register_out(test, pn_ia32_Test_eflags, reg);
192 foreach_out_edge_safe(node, edge, tmp) {
193 ir_node *const user = get_edge_src_irn(edge);
196 exchange(user, test);
199 sched_add_before(node, test);
200 copy_mark(node, test);
201 be_peephole_exchange(node, test);
205 * Peephole optimization for Test instructions.
206 * - Remove the Test, if an appropriate flag was produced which is still live
207 * - Change a Test(x, c) to 8Bit, if 0 <= c < 256 (3 byte shorter opcode)
209 static void peephole_ia32_Test(ir_node *node)
211 ir_node *left = get_irn_n(node, n_ia32_Test_left);
212 ir_node *right = get_irn_n(node, n_ia32_Test_right);
214 assert((int)n_ia32_Test_left == (int)n_ia32_Test8Bit_left
215 && (int)n_ia32_Test_right == (int)n_ia32_Test8Bit_right);
217 if (left == right) { /* we need a test for 0 */
218 ir_node *block = get_nodes_block(node);
219 int pn = pn_ia32_res;
225 const ir_edge_t *edge;
226 produces_flag_t produced;
228 if (get_nodes_block(left) != block)
232 pn = get_Proj_proj(op);
233 op = get_Proj_pred(op);
236 /* walk schedule up and abort when we find left or some other node
237 * destroys the flags */
240 schedpoint = sched_prev(schedpoint);
241 if (schedpoint == op)
243 if (arch_irn_is(schedpoint, modify_flags))
245 if (schedpoint == block)
246 panic("couldn't find left");
249 produced = check_produces_zero_sign(op, pn);
250 if (produced == produces_no_flag)
253 /* make sure users only look at the sign/zero flag */
254 foreach_out_edge(node, edge) {
255 ir_node *user = get_edge_src_irn(edge);
256 ia32_condition_code_t cc = get_ia32_condcode(user);
258 if (cc == ia32_cc_equal || cc == ia32_cc_not_equal)
260 if (produced == produces_zero_sign
261 && (cc == ia32_cc_sign || cc == ia32_cc_not_sign)) {
267 op_mode = get_ia32_ls_mode(op);
269 op_mode = get_irn_mode(op);
271 /* Make sure we operate on the same bit size */
272 if (get_mode_size_bits(op_mode) != get_mode_size_bits(get_ia32_ls_mode(node)))
275 if (produced == produces_zero_in_carry) {
276 /* patch users to look at the carry instead of the zero flag */
277 foreach_out_edge(node, edge) {
278 ir_node *user = get_edge_src_irn(edge);
279 ia32_condition_code_t cc = get_ia32_condcode(user);
282 case ia32_cc_equal: cc = ia32_cc_above_equal; break;
283 case ia32_cc_not_equal: cc = ia32_cc_below; break;
284 default: panic("unexpected pn");
286 set_ia32_condcode(user, cc);
290 if (get_irn_mode(op) != mode_T) {
291 set_irn_mode(op, mode_T);
293 /* If there are other users, reroute them to result proj */
294 if (get_irn_n_edges(op) != 2) {
295 ir_node *res = new_r_Proj(op, mode_Iu, pn_ia32_res);
297 edges_reroute(op, res);
298 /* Reattach the result proj to left */
299 set_Proj_pred(res, op);
302 if (get_irn_n_edges(left) == 2)
306 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
307 flags_proj = new_r_Proj(op, flags_mode, pn_ia32_flags);
308 arch_set_irn_register(flags_proj, &ia32_registers[REG_EFLAGS]);
310 assert(get_irn_mode(node) != mode_T);
312 be_peephole_exchange(node, flags_proj);
313 } else if (is_ia32_Immediate(right)) {
314 ia32_immediate_attr_t const *const imm = get_ia32_immediate_attr_const(right);
317 /* A test with a symconst is rather strange, but better safe than sorry */
318 if (imm->symconst != NULL)
321 offset = imm->offset;
322 if (get_ia32_op_type(node) == ia32_AddrModeS) {
323 ia32_attr_t *const attr = get_ia32_attr(node);
325 if ((offset & 0xFFFFFF00) == 0) {
326 /* attr->am_offs += 0; */
327 } else if ((offset & 0xFFFF00FF) == 0) {
328 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>8);
329 set_irn_n(node, n_ia32_Test_right, imm_node);
331 } else if ((offset & 0xFF00FFFF) == 0) {
332 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>16);
333 set_irn_n(node, n_ia32_Test_right, imm_node);
335 } else if ((offset & 0x00FFFFFF) == 0) {
336 ir_node *imm_node = ia32_create_Immediate(NULL, 0, offset>>24);
337 set_irn_n(node, n_ia32_Test_right, imm_node);
342 } else if (offset < 256) {
343 arch_register_t const* const reg = arch_get_irn_register(left);
345 if (reg != &ia32_registers[REG_EAX] &&
346 reg != &ia32_registers[REG_EBX] &&
347 reg != &ia32_registers[REG_ECX] &&
348 reg != &ia32_registers[REG_EDX]) {
355 /* Technically we should build a Test8Bit because of the register
356 * constraints, but nobody changes registers at this point anymore. */
357 set_ia32_ls_mode(node, mode_Bu);
362 * AMD Athlon works faster when RET is not destination of
363 * conditional jump or directly preceded by other jump instruction.
364 * Can be avoided by placing a Rep prefix before the return.
366 static void peephole_ia32_Return(ir_node *node)
370 if (!ia32_cg_config.use_pad_return)
373 /* check if this return is the first on the block */
374 sched_foreach_reverse_from(node, irn) {
375 switch (get_irn_opcode(irn)) {
377 /* the return node itself, ignore */
381 /* ignore no code generated */
384 /* arg, IncSP 0 nodes might occur, ignore these */
385 if (be_get_IncSP_offset(irn) == 0)
395 /* ensure, that the 3 byte return is generated */
396 be_Return_set_emit_pop(node, 1);
399 /* only optimize up to 48 stores behind IncSPs */
400 #define MAXPUSH_OPTIMIZE 48
403 * Tries to create Push's from IncSP, Store combinations.
404 * The Stores are replaced by Push's, the IncSP is modified
405 * (possibly into IncSP 0, but not removed).
407 static void peephole_IncSP_Store_to_push(ir_node *irn)
413 ir_node *stores[MAXPUSH_OPTIMIZE];
418 ir_node *first_push = NULL;
419 ir_edge_t const *edge;
420 ir_edge_t const *next;
422 memset(stores, 0, sizeof(stores));
424 assert(be_is_IncSP(irn));
426 inc_ofs = be_get_IncSP_offset(irn);
431 * We first walk the schedule after the IncSP node as long as we find
432 * suitable Stores that could be transformed to a Push.
433 * We save them into the stores array which is sorted by the frame offset/4
434 * attached to the node
437 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
442 /* it has to be a Store */
443 if (!is_ia32_Store(node))
446 /* it has to use our sp value */
447 if (get_irn_n(node, n_ia32_base) != irn)
449 /* Store has to be attached to NoMem */
450 mem = get_irn_n(node, n_ia32_mem);
454 /* unfortunately we can't support the full AMs possible for push at the
455 * moment. TODO: fix this */
456 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
459 offset = get_ia32_am_offs_int(node);
460 /* we should NEVER access uninitialized stack BELOW the current SP */
463 /* storing at half-slots is bad */
464 if ((offset & 3) != 0)
467 if (inc_ofs - 4 < offset || offset >= MAXPUSH_OPTIMIZE * 4)
469 storeslot = offset >> 2;
471 /* storing into the same slot twice is bad (and shouldn't happen...) */
472 if (stores[storeslot] != NULL)
475 stores[storeslot] = node;
476 if (storeslot > maxslot)
482 for (i = -1; i < maxslot; ++i) {
483 if (stores[i + 1] == NULL)
487 /* walk through the Stores and create Pushs for them */
488 block = get_nodes_block(irn);
489 spmode = get_irn_mode(irn);
490 irg = get_irn_irg(irn);
491 for (; i >= 0; --i) {
492 const arch_register_t *spreg;
494 ir_node *val, *mem, *mem_proj;
495 ir_node *store = stores[i];
496 ir_node *noreg = ia32_new_NoReg_gp(irg);
498 val = get_irn_n(store, n_ia32_unary_op);
499 mem = get_irn_n(store, n_ia32_mem);
500 spreg = arch_get_irn_register(curr_sp);
502 push = new_bd_ia32_Push(get_irn_dbg_info(store), block, noreg, noreg,
504 copy_mark(store, push);
506 if (first_push == NULL)
509 sched_add_after(skip_Proj(curr_sp), push);
511 /* create stackpointer Proj */
512 curr_sp = new_r_Proj(push, spmode, pn_ia32_Push_stack);
513 arch_set_irn_register(curr_sp, spreg);
515 /* create memory Proj */
516 mem_proj = new_r_Proj(push, mode_M, pn_ia32_Push_M);
518 /* rewire Store Projs */
519 foreach_out_edge_safe(store, edge, next) {
520 ir_node *proj = get_edge_src_irn(edge);
523 switch (get_Proj_proj(proj)) {
524 case pn_ia32_Store_M:
525 exchange(proj, mem_proj);
528 panic("unexpected Proj on Store->IncSp");
532 /* use the memproj now */
533 be_peephole_exchange(store, push);
538 foreach_out_edge_safe(irn, edge, next) {
539 ir_node *const src = get_edge_src_irn(edge);
540 int const pos = get_edge_src_pos(edge);
542 if (src == first_push)
545 set_irn_n(src, pos, curr_sp);
548 be_set_IncSP_offset(irn, inc_ofs);
553 * Creates a Push instruction before the given schedule point.
555 * @param dbgi debug info
556 * @param block the block
557 * @param stack the previous stack value
558 * @param schedpoint the new node is added before this node
559 * @param reg the register to pop
561 * @return the new stack value
563 static ir_node *create_push(dbg_info *dbgi, ir_node *block,
564 ir_node *stack, ir_node *schedpoint)
566 const arch_register_t *esp = &ia32_registers[REG_ESP];
568 ir_node *val = ia32_new_NoReg_gp(cg);
569 ir_node *noreg = ia32_new_NoReg_gp(cg);
570 ir_graph *irg = get_irn_irg(block);
571 ir_node *nomem = get_irg_no_mem(irg);
572 ir_node *push = new_bd_ia32_Push(dbgi, block, noreg, noreg, nomem, val, stack);
573 sched_add_before(schedpoint, push);
575 stack = new_r_Proj(push, mode_Iu, pn_ia32_Push_stack);
576 arch_set_irn_register(stack, esp);
581 static void peephole_store_incsp(ir_node *store)
592 ir_node *am_base = get_irn_n(store, n_ia32_Store_base);
593 if (!be_is_IncSP(am_base)
594 || get_nodes_block(am_base) != get_nodes_block(store))
596 mem = get_irn_n(store, n_ia32_Store_mem);
597 if (!is_ia32_NoReg_GP(get_irn_n(store, n_ia32_Store_index))
601 int incsp_offset = be_get_IncSP_offset(am_base);
602 if (incsp_offset <= 0)
605 /* we have to be at offset 0 */
606 int my_offset = get_ia32_am_offs_int(store);
607 if (my_offset != 0) {
608 /* TODO here: find out whether there is a store with offset 0 before
609 * us and whether we can move it down to our place */
612 ir_mode *ls_mode = get_ia32_ls_mode(store);
613 int my_store_size = get_mode_size_bytes(ls_mode);
615 if (my_offset + my_store_size > incsp_offset)
618 /* correctness checking:
619 - noone else must write to that stackslot
620 (because after translation incsp won't allocate it anymore)
622 sched_foreach_reverse_from(store, node) {
628 /* make sure noone else can use the space on the stack */
629 arity = get_irn_arity(node);
630 for (i = 0; i < arity; ++i) {
631 ir_node *pred = get_irn_n(node, i);
635 if (i == n_ia32_base &&
636 (get_ia32_op_type(node) == ia32_AddrModeS
637 || get_ia32_op_type(node) == ia32_AddrModeD)) {
638 int node_offset = get_ia32_am_offs_int(node);
639 ir_mode *node_ls_mode = get_ia32_ls_mode(node);
640 int node_size = get_mode_size_bytes(node_ls_mode);
641 /* overlapping with our position? abort */
642 if (node_offset < my_offset + my_store_size
643 && node_offset + node_size >= my_offset)
645 /* otherwise it's fine */
649 /* strange use of esp: abort */
654 /* all ok, change to push */
655 dbgi = get_irn_dbg_info(store);
656 block = get_nodes_block(store);
657 noreg = ia32_new_NoReg_gp(cg);
658 val = get_irn_n(store, n_ia32_Store_val);
660 push = new_bd_ia32_Push(dbgi, block, noreg, noreg, mem,
662 create_push(dbgi, current_ir_graph, block, am_base, store);
667 * Return true if a mode can be stored in the GP register set
669 static inline int mode_needs_gp_reg(ir_mode *mode)
671 if (mode == ia32_mode_fpcw)
673 if (get_mode_size_bits(mode) > 32)
675 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
679 * Tries to create Pops from Load, IncSP combinations.
680 * The Loads are replaced by Pops, the IncSP is modified
681 * (possibly into IncSP 0, but not removed).
683 static void peephole_Load_IncSP_to_pop(ir_node *irn)
685 const arch_register_t *esp = &ia32_registers[REG_ESP];
686 int i, maxslot, inc_ofs, ofs;
687 ir_node *node, *pred_sp, *block;
688 ir_node *loads[MAXPUSH_OPTIMIZE];
689 unsigned regmask = 0;
690 unsigned copymask = ~0;
692 memset(loads, 0, sizeof(loads));
693 assert(be_is_IncSP(irn));
695 inc_ofs = -be_get_IncSP_offset(irn);
700 * We first walk the schedule before the IncSP node as long as we find
701 * suitable Loads that could be transformed to a Pop.
702 * We save them into the stores array which is sorted by the frame offset/4
703 * attached to the node
706 pred_sp = be_get_IncSP_pred(irn);
707 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
710 const arch_register_t *sreg, *dreg;
712 /* it has to be a Load */
713 if (!is_ia32_Load(node)) {
714 if (be_is_Copy(node)) {
715 if (!mode_needs_gp_reg(get_irn_mode(node))) {
716 /* not a GP copy, ignore */
719 dreg = arch_get_irn_register(node);
720 sreg = arch_get_irn_register(be_get_Copy_op(node));
721 if (regmask & copymask & (1 << sreg->index)) {
724 if (regmask & copymask & (1 << dreg->index)) {
727 /* we CAN skip Copies if neither the destination nor the source
728 * is not in our regmask, ie none of our future Pop will overwrite it */
729 regmask |= (1 << dreg->index) | (1 << sreg->index);
730 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
736 /* we can handle only GP loads */
737 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
740 /* it has to use our predecessor sp value */
741 if (get_irn_n(node, n_ia32_base) != pred_sp) {
742 /* it would be ok if this load does not use a Pop result,
743 * but we do not check this */
747 /* should have NO index */
748 if (!is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
751 offset = get_ia32_am_offs_int(node);
752 /* we should NEVER access uninitialized stack BELOW the current SP */
755 /* storing at half-slots is bad */
756 if ((offset & 3) != 0)
759 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
761 /* ignore those outside the possible windows */
762 if (offset > inc_ofs - 4)
764 loadslot = offset >> 2;
766 /* loading from the same slot twice is bad (and shouldn't happen...) */
767 if (loads[loadslot] != NULL)
770 dreg = arch_get_irn_register_out(node, pn_ia32_Load_res);
771 if (regmask & (1 << dreg->index)) {
772 /* this register is already used */
775 regmask |= 1 << dreg->index;
777 loads[loadslot] = node;
778 if (loadslot > maxslot)
785 /* find the first slot */
786 for (i = maxslot; i >= 0; --i) {
787 ir_node *load = loads[i];
793 ofs = inc_ofs - (maxslot + 1) * 4;
796 /* create a new IncSP if needed */
797 block = get_nodes_block(irn);
799 pred_sp = be_new_IncSP(esp, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
800 sched_add_before(irn, pred_sp);
803 /* walk through the Loads and create Pops for them */
804 for (++i; i <= maxslot; ++i) {
805 ir_node *load = loads[i];
807 const ir_edge_t *edge, *tmp;
808 const arch_register_t *reg;
810 mem = get_irn_n(load, n_ia32_mem);
811 reg = arch_get_irn_register_out(load, pn_ia32_Load_res);
813 pop = new_bd_ia32_Pop(get_irn_dbg_info(load), block, mem, pred_sp);
814 arch_set_irn_register_out(pop, pn_ia32_Load_res, reg);
816 copy_mark(load, pop);
818 /* create stackpointer Proj */
819 pred_sp = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
820 arch_set_irn_register(pred_sp, esp);
822 sched_add_before(irn, pop);
825 foreach_out_edge_safe(load, edge, tmp) {
826 ir_node *proj = get_edge_src_irn(edge);
828 set_Proj_pred(proj, pop);
831 /* we can remove the Load now */
836 be_set_IncSP_offset(irn, -ofs);
837 be_set_IncSP_pred(irn, pred_sp);
842 * Find a free GP register if possible, else return NULL.
844 static const arch_register_t *get_free_gp_reg(ir_graph *irg)
846 be_irg_t *birg = be_birg_from_irg(irg);
849 for (i = 0; i < N_ia32_gp_REGS; ++i) {
850 const arch_register_t *reg = &ia32_reg_classes[CLASS_ia32_gp].regs[i];
851 if (!rbitset_is_set(birg->allocatable_regs, reg->global_index))
854 if (be_peephole_get_value(reg->global_index) == NULL)
862 * Creates a Pop instruction before the given schedule point.
864 * @param dbgi debug info
865 * @param block the block
866 * @param stack the previous stack value
867 * @param schedpoint the new node is added before this node
868 * @param reg the register to pop
870 * @return the new stack value
872 static ir_node *create_pop(dbg_info *dbgi, ir_node *block,
873 ir_node *stack, ir_node *schedpoint,
874 const arch_register_t *reg)
876 const arch_register_t *esp = &ia32_registers[REG_ESP];
877 ir_graph *irg = get_irn_irg(block);
883 pop = new_bd_ia32_Pop(dbgi, block, get_irg_no_mem(irg), stack);
885 stack = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_stack);
886 arch_set_irn_register(stack, esp);
887 val = new_r_Proj(pop, mode_Iu, pn_ia32_Pop_res);
888 arch_set_irn_register(val, reg);
890 sched_add_before(schedpoint, pop);
893 keep = be_new_Keep(block, 1, in);
894 sched_add_before(schedpoint, keep);
900 * Optimize an IncSp by replacing it with Push/Pop.
902 static void peephole_be_IncSP(ir_node *node)
904 const arch_register_t *esp = &ia32_registers[REG_ESP];
905 const arch_register_t *reg;
911 /* first optimize incsp->incsp combinations */
912 node = be_peephole_IncSP_IncSP(node);
914 /* transform IncSP->Store combinations to Push where possible */
915 peephole_IncSP_Store_to_push(node);
917 /* transform Load->IncSP combinations to Pop where possible */
918 peephole_Load_IncSP_to_pop(node);
920 if (arch_get_irn_register(node) != esp)
923 /* replace IncSP -4 by Pop freereg when possible */
924 offset = be_get_IncSP_offset(node);
925 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
926 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
927 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
928 (offset != +8 || ia32_cg_config.use_sub_esp_8))
932 /* we need a free register for pop */
933 reg = get_free_gp_reg(get_irn_irg(node));
937 dbgi = get_irn_dbg_info(node);
938 block = get_nodes_block(node);
939 stack = be_get_IncSP_pred(node);
941 stack = create_pop(dbgi, block, stack, node, reg);
944 stack = create_pop(dbgi, block, stack, node, reg);
947 dbgi = get_irn_dbg_info(node);
948 block = get_nodes_block(node);
949 stack = be_get_IncSP_pred(node);
950 stack = new_bd_ia32_PushEax(dbgi, block, stack);
951 arch_set_irn_register(stack, esp);
952 sched_add_before(node, stack);
955 stack = new_bd_ia32_PushEax(dbgi, block, stack);
956 arch_set_irn_register(stack, esp);
957 sched_add_before(node, stack);
961 be_peephole_exchange(node, stack);
965 * Peephole optimisation for ia32_Const's
967 static void peephole_ia32_Const(ir_node *node)
969 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
970 const arch_register_t *reg;
975 /* try to transform a mov 0, reg to xor reg reg */
976 if (attr->offset != 0 || attr->symconst != NULL)
978 if (ia32_cg_config.use_mov_0)
980 /* xor destroys the flags, so no-one must be using them */
981 if (be_peephole_get_value(REG_EFLAGS) != NULL)
984 reg = arch_get_irn_register(node);
985 assert(be_peephole_get_reg_value(reg) == NULL);
987 /* create xor(produceval, produceval) */
988 block = get_nodes_block(node);
989 dbgi = get_irn_dbg_info(node);
990 xorn = new_bd_ia32_Xor0(dbgi, block);
991 arch_set_irn_register(xorn, reg);
993 sched_add_before(node, xorn);
995 copy_mark(node, xorn);
996 be_peephole_exchange(node, xorn);
999 static inline int is_noreg(const ir_node *node)
1001 return is_ia32_NoReg_GP(node);
1004 ir_node *ia32_immediate_from_long(long val)
1006 ir_graph *irg = current_ir_graph;
1007 ir_node *start_block = get_irg_start_block(irg);
1009 = new_bd_ia32_Immediate(NULL, start_block, NULL, 0, 0, val);
1010 arch_set_irn_register(immediate, &ia32_registers[REG_GP_NOREG]);
1015 static ir_node *create_immediate_from_am(const ir_node *node)
1017 ir_node *block = get_nodes_block(node);
1018 int offset = get_ia32_am_offs_int(node);
1019 int sc_sign = is_ia32_am_sc_sign(node);
1020 const ia32_attr_t *attr = get_ia32_attr_const(node);
1021 int sc_no_pic_adjust = attr->data.am_sc_no_pic_adjust;
1022 ir_entity *entity = get_ia32_am_sc(node);
1025 res = new_bd_ia32_Immediate(NULL, block, entity, sc_sign, sc_no_pic_adjust,
1027 arch_set_irn_register(res, &ia32_registers[REG_GP_NOREG]);
1031 static int is_am_one(const ir_node *node)
1033 int offset = get_ia32_am_offs_int(node);
1034 ir_entity *entity = get_ia32_am_sc(node);
1036 return offset == 1 && entity == NULL;
1039 static int is_am_minus_one(const ir_node *node)
1041 int offset = get_ia32_am_offs_int(node);
1042 ir_entity *entity = get_ia32_am_sc(node);
1044 return offset == -1 && entity == NULL;
1048 * Transforms a LEA into an Add or SHL if possible.
1050 static void peephole_ia32_Lea(ir_node *node)
1055 const arch_register_t *base_reg;
1056 const arch_register_t *index_reg;
1057 const arch_register_t *out_reg;
1068 assert(is_ia32_Lea(node));
1070 /* we can only do this if it is allowed to clobber the flags */
1071 if (be_peephole_get_value(REG_EFLAGS) != NULL)
1074 base = get_irn_n(node, n_ia32_Lea_base);
1075 index = get_irn_n(node, n_ia32_Lea_index);
1077 if (is_noreg(base)) {
1081 base_reg = arch_get_irn_register(base);
1083 if (is_noreg(index)) {
1087 index_reg = arch_get_irn_register(index);
1090 if (base == NULL && index == NULL) {
1091 /* we shouldn't construct these in the first place... */
1092 #ifdef DEBUG_libfirm
1093 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
1098 out_reg = arch_get_irn_register(node);
1099 scale = get_ia32_am_scale(node);
1100 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
1101 /* check if we have immediates values (frame entities should already be
1102 * expressed in the offsets) */
1103 if (get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
1109 /* we can transform leas where the out register is the same as either the
1110 * base or index register back to an Add or Shl */
1111 if (out_reg == base_reg) {
1112 if (index == NULL) {
1113 #ifdef DEBUG_libfirm
1114 if (!has_immediates) {
1115 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1120 goto make_add_immediate;
1122 if (scale == 0 && !has_immediates) {
1127 /* can't create an add */
1129 } else if (out_reg == index_reg) {
1131 if (has_immediates && scale == 0) {
1133 goto make_add_immediate;
1134 } else if (!has_immediates && scale > 0) {
1136 op2 = ia32_immediate_from_long(scale);
1138 } else if (!has_immediates) {
1139 #ifdef DEBUG_libfirm
1140 ir_fprintf(stderr, "Optimisation warning: found lea which is "
1144 } else if (scale == 0 && !has_immediates) {
1149 /* can't create an add */
1152 /* can't create an add */
1157 if (ia32_cg_config.use_incdec) {
1158 if (is_am_one(node)) {
1159 dbgi = get_irn_dbg_info(node);
1160 block = get_nodes_block(node);
1161 res = new_bd_ia32_Inc(dbgi, block, op1);
1162 arch_set_irn_register(res, out_reg);
1165 if (is_am_minus_one(node)) {
1166 dbgi = get_irn_dbg_info(node);
1167 block = get_nodes_block(node);
1168 res = new_bd_ia32_Dec(dbgi, block, op1);
1169 arch_set_irn_register(res, out_reg);
1173 op2 = create_immediate_from_am(node);
1176 dbgi = get_irn_dbg_info(node);
1177 block = get_nodes_block(node);
1178 irg = get_irn_irg(node);
1179 noreg = ia32_new_NoReg_gp(irg);
1180 nomem = get_irg_no_mem(irg);
1181 res = new_bd_ia32_Add(dbgi, block, noreg, noreg, nomem, op1, op2);
1182 arch_set_irn_register(res, out_reg);
1183 set_ia32_commutative(res);
1187 dbgi = get_irn_dbg_info(node);
1188 block = get_nodes_block(node);
1189 irg = get_irn_irg(node);
1190 noreg = ia32_new_NoReg_gp(irg);
1191 nomem = get_irg_no_mem(irg);
1192 res = new_bd_ia32_Shl(dbgi, block, op1, op2);
1193 arch_set_irn_register(res, out_reg);
1197 SET_IA32_ORIG_NODE(res, node);
1199 /* add new ADD/SHL to schedule */
1200 DBG_OPT_LEA2ADD(node, res);
1202 /* exchange the Add and the LEA */
1203 sched_add_before(node, res);
1204 copy_mark(node, res);
1205 be_peephole_exchange(node, res);
1209 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
1211 static void peephole_ia32_Imul_split(ir_node *imul)
1213 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
1214 const arch_register_t *reg;
1217 if (!is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
1218 /* no memory, imm form ignore */
1221 /* we need a free register */
1222 reg = get_free_gp_reg(get_irn_irg(imul));
1226 /* fine, we can rebuild it */
1227 res = ia32_turn_back_am(imul);
1228 arch_set_irn_register(res, reg);
1232 * Replace xorps r,r and xorpd r,r by pxor r,r
1234 static void peephole_ia32_xZero(ir_node *xorn)
1236 set_irn_op(xorn, op_ia32_xPzero);
1240 * Replace 16bit sign extension from ax to eax by shorter cwtl
1242 static void peephole_ia32_Conv_I2I(ir_node *node)
1244 const arch_register_t *eax = &ia32_registers[REG_EAX];
1245 ir_mode *smaller_mode = get_ia32_ls_mode(node);
1246 ir_node *val = get_irn_n(node, n_ia32_Conv_I2I_val);
1251 if (get_mode_size_bits(smaller_mode) != 16 ||
1252 !mode_is_signed(smaller_mode) ||
1253 eax != arch_get_irn_register(val) ||
1254 eax != arch_get_irn_register_out(node, pn_ia32_Conv_I2I_res))
1257 dbgi = get_irn_dbg_info(node);
1258 block = get_nodes_block(node);
1259 cwtl = new_bd_ia32_Cwtl(dbgi, block, val);
1260 arch_set_irn_register(cwtl, eax);
1261 sched_add_before(node, cwtl);
1262 be_peephole_exchange(node, cwtl);
1266 * Register a peephole optimisation function.
1268 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func)
1270 assert(op->ops.generic == NULL);
1271 op->ops.generic = (op_func)func;
1274 /* Perform peephole-optimizations. */
1275 void ia32_peephole_optimization(ir_graph *irg)
1277 /* we currently do it in 2 passes because:
1278 * Lea -> Add could be usefull as flag producer for Test later
1282 clear_irp_opcodes_generic_func();
1283 register_peephole_optimisation(op_ia32_Cmp, peephole_ia32_Cmp);
1284 register_peephole_optimisation(op_ia32_Cmp8Bit, peephole_ia32_Cmp);
1285 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1286 if (ia32_cg_config.use_short_sex_eax)
1287 register_peephole_optimisation(op_ia32_Conv_I2I, peephole_ia32_Conv_I2I);
1288 if (ia32_cg_config.use_pxor)
1289 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1290 if (! ia32_cg_config.use_imul_mem_imm32)
1291 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1292 be_peephole_opt(irg);
1295 clear_irp_opcodes_generic_func();
1296 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1297 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1298 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1299 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1300 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1301 be_peephole_opt(irg);
1305 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1306 * all its Projs are removed as well.
1307 * @param irn The irn to be removed from schedule
1309 static inline void try_kill(ir_node *node)
1311 if (get_irn_mode(node) == mode_T) {
1312 const ir_edge_t *edge, *next;
1313 foreach_out_edge_safe(node, edge, next) {
1314 ir_node *proj = get_edge_src_irn(edge);
1319 if (get_irn_n_edges(node) != 0)
1322 if (sched_is_scheduled(node)) {
1329 static void optimize_conv_store(ir_node *node)
1334 ir_mode *store_mode;
1336 if (!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1339 assert((int)n_ia32_Store_val == (int)n_ia32_Store8Bit_val);
1340 pred_proj = get_irn_n(node, n_ia32_Store_val);
1341 if (is_Proj(pred_proj)) {
1342 pred = get_Proj_pred(pred_proj);
1346 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1348 if (get_ia32_op_type(pred) != ia32_Normal)
1351 /* the store only stores the lower bits, so we only need the conv
1352 * it it shrinks the mode */
1353 conv_mode = get_ia32_ls_mode(pred);
1354 store_mode = get_ia32_ls_mode(node);
1355 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1358 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1359 if (get_irn_n_edges(pred_proj) == 0) {
1360 kill_node(pred_proj);
1361 if (pred != pred_proj)
1366 static void optimize_load_conv(ir_node *node)
1368 ir_node *pred, *predpred;
1372 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1375 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1376 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1380 predpred = get_Proj_pred(pred);
1381 if (!is_ia32_Load(predpred))
1384 /* the load is sign extending the upper bits, so we only need the conv
1385 * if it shrinks the mode */
1386 load_mode = get_ia32_ls_mode(predpred);
1387 conv_mode = get_ia32_ls_mode(node);
1388 if (get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1391 if (get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1392 /* change the load if it has only 1 user */
1393 if (get_irn_n_edges(pred) == 1) {
1395 if (get_mode_sign(conv_mode)) {
1396 newmode = find_signed_mode(load_mode);
1398 newmode = find_unsigned_mode(load_mode);
1400 assert(newmode != NULL);
1401 set_ia32_ls_mode(predpred, newmode);
1403 /* otherwise we have to keep the conv */
1409 exchange(node, pred);
1412 static void optimize_conv_conv(ir_node *node)
1414 ir_node *pred_proj, *pred, *result_conv;
1415 ir_mode *pred_mode, *conv_mode;
1419 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1422 assert((int)n_ia32_Conv_I2I_val == (int)n_ia32_Conv_I2I8Bit_val);
1423 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1424 if (is_Proj(pred_proj))
1425 pred = get_Proj_pred(pred_proj);
1429 if (!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1432 /* we know that after a conv, the upper bits are sign extended
1433 * so we only need the 2nd conv if it shrinks the mode */
1434 conv_mode = get_ia32_ls_mode(node);
1435 conv_mode_bits = get_mode_size_bits(conv_mode);
1436 pred_mode = get_ia32_ls_mode(pred);
1437 pred_mode_bits = get_mode_size_bits(pred_mode);
1439 if (conv_mode_bits == pred_mode_bits
1440 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1441 result_conv = pred_proj;
1442 } else if (conv_mode_bits <= pred_mode_bits) {
1443 /* if 2nd conv is smaller then first conv, then we can always take the
1445 if (get_irn_n_edges(pred_proj) == 1) {
1446 result_conv = pred_proj;
1447 set_ia32_ls_mode(pred, conv_mode);
1449 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1450 if (get_mode_size_bits(conv_mode) == 8) {
1451 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1452 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1453 arch_set_irn_register_reqs_in(pred, reqs);
1456 /* we don't want to end up with 2 loads, so we better do nothing */
1457 if (get_irn_mode(pred) == mode_T) {
1461 result_conv = exact_copy(pred);
1462 set_ia32_ls_mode(result_conv, conv_mode);
1464 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1465 if (get_mode_size_bits(conv_mode) == 8) {
1466 const arch_register_req_t **reqs = arch_get_irn_register_reqs_in(node);
1467 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1468 arch_set_irn_register_reqs_in(result_conv, reqs);
1472 /* if both convs have the same sign, then we can take the smaller one */
1473 if (get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1474 result_conv = pred_proj;
1476 /* no optimisation possible if smaller conv is sign-extend */
1477 if (mode_is_signed(pred_mode)) {
1480 /* we can take the smaller conv if it is unsigned */
1481 result_conv = pred_proj;
1485 /* Some user (like Phis) won't be happy if we change the mode. */
1486 set_irn_mode(result_conv, get_irn_mode(node));
1489 exchange(node, result_conv);
1491 if (get_irn_n_edges(pred_proj) == 0) {
1492 kill_node(pred_proj);
1493 if (pred != pred_proj)
1496 optimize_conv_conv(result_conv);
1499 static void optimize_node(ir_node *node, void *env)
1503 optimize_load_conv(node);
1504 optimize_conv_store(node);
1505 optimize_conv_conv(node);
1509 * Performs conv and address mode optimization.
1511 void ia32_optimize_graph(ir_graph *irg)
1513 irg_walk_blkwise_graph(irg, NULL, optimize_node, NULL);
1516 void ia32_init_optimize(void)
1518 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");