8 #include "firm_types.h"
15 #include "../benode_t.h"
16 #include "../besched_t.h"
18 #include "ia32_new_nodes.h"
19 #include "bearch_ia32_t.h"
20 #include "gen_ia32_regalloc_if.h" /* the generated interface (register type and class defenitions) */
23 #define is_NoMem(irn) (get_irn_op(irn) == op_NoMem)
25 typedef int is_op_func_t(const ir_node *n);
27 static int be_is_NoReg(be_abi_irg_t *babi, const ir_node *irn) {
28 if (be_abi_get_callee_save_irn(babi, &ia32_gp_regs[REG_XXX]) == irn ||
29 be_abi_get_callee_save_irn(babi, &ia32_fp_regs[REG_XXXX]) == irn)
39 /*************************************************
42 * | | ___ _ __ ___| |_ __ _ _ __ | |_ ___
43 * | | / _ \| '_ \/ __| __/ _` | '_ \| __/ __|
44 * | |___| (_) | | | \__ \ || (_| | | | | |_\__ \
45 * \_____\___/|_| |_|___/\__\__,_|_| |_|\__|___/
47 *************************************************/
50 * creates a unique ident by adding a number to a tag
52 * @param tag the tag string, must contain a %d if a number
55 static ident *unique_id(const char *tag)
57 static unsigned id = 0;
60 snprintf(str, sizeof(str), tag, ++id);
61 return new_id_from_str(str);
67 * Transforms a SymConst.
69 * @param mod the debug module
70 * @param block the block the new node should belong to
71 * @param node the ir SymConst node
72 * @param mode mode of the SymConst
73 * @return the created ia32 Const node
75 static ir_node *gen_SymConst(ia32_transform_env_t *env) {
77 dbg_info *dbg = env->dbg;
78 ir_mode *mode = env->mode;
79 ir_graph *irg = env->irg;
80 ir_node *block = env->block;
82 if (mode_is_float(mode)) {
83 cnst = new_rd_ia32_fConst(dbg, irg, block, mode);
86 cnst = new_rd_ia32_Const(dbg, irg, block, mode);
88 set_ia32_Const_attr(cnst, env->irn);
93 * Get a primitive type for a mode.
95 static ir_type *get_prim_type(pmap *types, ir_mode *mode)
97 pmap_entry *e = pmap_find(types, mode);
102 snprintf(buf, sizeof(buf), "prim_type_%s", get_mode_name(mode));
103 res = new_type_primitive(new_id_from_str(buf), mode);
104 pmap_insert(types, mode, res);
112 * Get an entity that is initialized with a tarval
114 static entity *get_entity_for_tv(ia32_code_gen_t *cg, ir_node *cnst)
116 tarval *tv = get_Const_tarval(cnst);
117 pmap_entry *e = pmap_find(cg->tv_ent, tv);
122 ir_mode *mode = get_irn_mode(cnst);
123 ir_type *tp = get_Const_type(cnst);
124 if (tp == firm_unknown_type)
125 tp = get_prim_type(cg->types, mode);
127 res = new_entity(get_glob_type(), unique_id("ia32FloatCnst_%u"), tp);
129 set_entity_ld_ident(res, get_entity_ident(res));
130 set_entity_visibility(res, visibility_local);
131 set_entity_variability(res, variability_constant);
132 set_entity_allocation(res, allocation_static);
134 /* we create a new entity here: It's initialization must resist on the
136 rem = current_ir_graph;
137 current_ir_graph = get_const_code_irg();
138 set_atomic_ent_value(res, new_Const_type(tv, tp));
139 current_ir_graph = rem;
147 * Transforms a Const.
149 * @param mod the debug module
150 * @param block the block the new node should belong to
151 * @param node the ir Const node
152 * @param mode mode of the Const
153 * @return the created ia32 Const node
155 static ir_node *gen_Const(ia32_transform_env_t *env) {
158 ir_graph *irg = env->irg;
159 ir_node *block = env->block;
160 ir_node *node = env->irn;
161 dbg_info *dbg = env->dbg;
162 ir_mode *mode = env->mode;
164 if (mode_is_float(mode)) {
165 sym.entity_p = get_entity_for_tv(env->cg, node);
167 cnst = new_rd_SymConst(dbg, irg, block, sym, symconst_addr_ent);
169 cnst = gen_SymConst(env);
172 cnst = new_rd_ia32_Const(dbg, irg, block, get_irn_mode(node));
173 set_ia32_Const_attr(cnst, node);
181 * Transforms (all) Const's into ia32_Const and places them in the
182 * block where they are used (or in the cfg-pred Block in case of Phi's).
183 * Additionally all reference nodes are changed into mode_Is nodes.
185 void ia32_place_consts_set_modes(ir_node *irn, void *env) {
186 ia32_code_gen_t *cg = env;
187 ia32_transform_env_t tenv;
189 ir_node *pred, *cnst;
196 mode = get_irn_mode(irn);
198 /* transform all reference nodes into mode_Is nodes */
199 if (mode_is_reference(mode)) {
201 set_irn_mode(irn, mode);
204 tenv.block = get_nodes_block(irn);
209 /* Loop over all predecessors and check for Sym/Const nodes */
210 for (i = get_irn_arity(irn) - 1; i >= 0; --i) {
211 pred = get_irn_n(irn, i);
213 opc = get_irn_opcode(pred);
215 tenv.mode = get_irn_mode(pred);
216 tenv.dbg = get_irn_dbg_info(pred);
218 /* If it's a Phi, then we need to create the */
219 /* new Const in it's predecessor block */
221 tenv.block = get_Block_cfgpred_block(get_nodes_block(irn), i);
224 /* put the const into the block where the original const was */
225 if (! cg->opt.placecnst) {
226 tenv.block = get_nodes_block(pred);
231 cnst = gen_Const(&tenv);
234 cnst = gen_SymConst(&tenv);
240 /* if we found a const, then set it */
242 set_irn_n(irn, i, cnst);
249 /********************************************************************************************************
250 * _____ _ _ ____ _ _ _ _ _
251 * | __ \ | | | | / __ \ | | (_) (_) | | (_)
252 * | |__) |__ ___ _ __ | |__ ___ | | ___ | | | |_ __ | |_ _ _ __ ___ _ ______ _| |_ _ ___ _ __
253 * | ___/ _ \/ _ \ '_ \| '_ \ / _ \| |/ _ \ | | | | '_ \| __| | '_ ` _ \| |_ / _` | __| |/ _ \| '_ \
254 * | | | __/ __/ |_) | | | | (_) | | __/ | |__| | |_) | |_| | | | | | | |/ / (_| | |_| | (_) | | | |
255 * |_| \___|\___| .__/|_| |_|\___/|_|\___| \____/| .__/ \__|_|_| |_| |_|_/___\__,_|\__|_|\___/|_| |_|
258 ********************************************************************************************************/
261 * NOTE: THESE PEEPHOLE OPTIMIZATIONS MUST BE CALLED AFTER SCHEDULING AND REGISTER ALLOCATION.
264 static int ia32_cnst_compare(ir_node *n1, ir_node *n2) {
265 return get_ia32_id_cnst(n1) == get_ia32_id_cnst(n2);
269 * Checks for potential CJmp/CJmpAM optimization candidates.
271 static ir_node *ia32_determine_cjmp_cand(ir_node *irn, is_op_func_t *is_op_func) {
272 ir_node *cand = NULL;
273 ir_node *prev = sched_prev(irn);
275 if (is_Block(prev)) {
276 if (get_Block_n_cfgpreds(prev) == 1)
277 prev = get_Block_cfgpred(prev, 0);
282 /* The predecessor must be a ProjX. */
283 if (prev && is_Proj(prev) && get_irn_mode(prev) == mode_X) {
284 prev = get_Proj_pred(prev);
286 if (is_op_func(prev))
293 static int is_TestJmp_cand(const ir_node *irn) {
294 return is_ia32_TestJmp(irn) || is_ia32_And(irn);
298 * Checks if two consecutive arguments of cand matches
299 * the two arguments of irn (TestJmp).
301 static int is_TestJmp_replacement(ir_node *cand, ir_node *irn) {
302 ir_node *in1 = get_irn_n(irn, 0);
303 ir_node *in2 = get_irn_n(irn, 1);
304 int i, n = get_irn_arity(cand);
307 for (i = 0; i < n - 1; i++) {
308 if (get_irn_n(cand, i) == in1 &&
309 get_irn_n(cand, i + 1) == in2)
317 return ia32_cnst_compare(cand, irn);
323 * Tries to replace a TestJmp by a CJmp or CJmpAM (in case of And)
325 static void ia32_optimize_TestJmp(ir_node *irn, ia32_code_gen_t *cg) {
326 ir_node *cand = ia32_determine_cjmp_cand(irn, is_TestJmp_cand);
329 /* we found a possible candidate */
330 replace = cand ? is_TestJmp_replacement(cand, irn) : 0;
333 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
335 if (is_ia32_And(cand))
336 set_irn_op(irn, op_ia32_CJmpAM);
338 set_irn_op(irn, op_ia32_CJmp);
340 DB((cg->mod, LEVEL_1, "%+F\n", irn));
344 static int is_CondJmp_cand(const ir_node *irn) {
345 return is_ia32_CondJmp(irn) || is_ia32_Sub(irn);
349 * Checks if the arguments of cand are the same of irn.
351 static int is_CondJmp_replacement(ir_node *cand, ir_node *irn) {
352 int i, n = get_irn_arity(cand);
355 for (i = 0; i < n; i++) {
356 if (get_irn_n(cand, i) == get_irn_n(irn, i)) {
363 return ia32_cnst_compare(cand, irn);
369 * Tries to replace a CondJmp by a CJmpAM
371 static void ia32_optimize_CondJmp(ir_node *irn, ia32_code_gen_t *cg) {
372 ir_node *cand = ia32_determine_cjmp_cand(irn, is_CondJmp_cand);
375 /* we found a possible candidate */
376 replace = cand ? is_CondJmp_replacement(cand, irn) : 0;
379 DBG((cg->mod, LEVEL_1, "replacing %+F by ", irn));
381 set_irn_op(irn, op_ia32_CJmp);
383 DB((cg->mod, LEVEL_1, "%+F\n", irn));
388 * Performs Peephole Optimizations
390 void ia32_peephole_optimization(ir_node *irn, void *env) {
391 if (is_ia32_TestJmp(irn)) {
392 ia32_optimize_TestJmp(irn, env);
394 else if (is_ia32_CondJmp(irn)) {
395 ia32_optimize_CondJmp(irn, env);
401 /******************************************************************
403 * /\ | | | | | \/ | | |
404 * / \ __| | __| |_ __ ___ ___ ___| \ / | ___ __| | ___
405 * / /\ \ / _` |/ _` | '__/ _ \/ __/ __| |\/| |/ _ \ / _` |/ _ \
406 * / ____ \ (_| | (_| | | | __/\__ \__ \ | | | (_) | (_| | __/
407 * /_/ \_\__,_|\__,_|_| \___||___/___/_| |_|\___/ \__,_|\___|
409 ******************************************************************/
411 static int node_is_comm(const ir_node *irn) {
412 return is_ia32_irn(irn) ? is_ia32_commutative(irn) : 0;
415 static int ia32_get_irn_n_edges(const ir_node *irn) {
416 const ir_edge_t *edge;
419 foreach_out_edge(irn, edge) {
427 * Returns the first mode_M Proj connected to irn.
429 static ir_node *get_mem_proj(const ir_node *irn) {
430 const ir_edge_t *edge;
433 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
435 foreach_out_edge(irn, edge) {
436 src = get_edge_src_irn(edge);
438 assert(is_Proj(src) && "Proj expected");
440 if (get_irn_mode(src) == mode_M)
448 * Returns the first Proj with mode != mode_M connected to irn.
450 static ir_node *get_res_proj(const ir_node *irn) {
451 const ir_edge_t *edge;
454 assert(get_irn_mode(irn) == mode_T && "expected mode_T node");
456 foreach_out_edge(irn, edge) {
457 src = get_edge_src_irn(edge);
459 assert(is_Proj(src) && "Proj expected");
461 if (get_irn_mode(src) != mode_M)
469 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor.
471 * @param pred The node to be checked
472 * @param is_op_func The check-function
473 * @return 1 if conditions are fulfilled, 0 otherwise
475 static int pred_is_specific_node(const ir_node *pred, is_op_func_t *is_op_func) {
476 if (is_Proj(pred) && is_op_func(get_Proj_pred(pred))) {
484 * Determines if pred is a Proj and if is_op_func returns true for it's predecessor
485 * and if the predecessor is in block bl.
487 * @param bl The block
488 * @param pred The node to be checked
489 * @param is_op_func The check-function
490 * @return 1 if conditions are fulfilled, 0 otherwise
492 static int pred_is_specific_nodeblock(const ir_node *bl, const ir_node *pred,
493 int (*is_op_func)(const ir_node *n))
496 pred = get_Proj_pred(pred);
497 if ((bl == get_nodes_block(pred)) && is_op_func(pred)) {
508 * Checks if irn is a candidate for address calculation or address mode.
510 * address calculation (AC):
511 * - none of the operand must be a Load within the same block OR
512 * - all Loads must have more than one user OR
513 * - the irn has a frame entity (it's a former FrameAddr)
516 * - at least one operand has to be a Load within the same block AND
517 * - the load must not have other users than the irn AND
518 * - the irn must not have a frame entity set
520 * @param block The block the Loads must/not be in
521 * @param irn The irn to check
522 * @param check_addr 1 if to check for address calculation, 0 otherwise
523 * return 1 if irn is a candidate for AC or AM, 0 otherwise
525 static int is_candidate(const ir_node *block, const ir_node *irn, int check_addr) {
527 int n, is_cand = check_addr;
529 in = get_irn_n(irn, 2);
531 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
532 n = ia32_get_irn_n_edges(in);
533 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
536 in = get_irn_n(irn, 3);
538 if (pred_is_specific_nodeblock(block, in, is_ia32_Ld)) {
539 n = ia32_get_irn_n_edges(in);
540 is_cand = check_addr ? (n == 1 ? 0 : is_cand) : (n == 1 ? 1 : is_cand);
543 is_cand = get_ia32_frame_ent(irn) ? (check_addr ? 1 : 0) : is_cand;
549 * Compares the base and index addr and the load/store entities
550 * and returns 1 if they are equal.
552 static int load_store_addr_is_equal(const ir_node *load, const ir_node *store,
553 const ir_node *addr_b, const ir_node *addr_i)
555 int is_equal = (addr_b == get_irn_n(load, 0)) && (addr_i == get_irn_n(load, 1));
556 entity *lent = get_ia32_frame_ent(load);
557 entity *sent = get_ia32_frame_ent(store);
559 /* are both entities set and equal? */
560 is_equal = lent && sent && (lent == sent);
562 /* are the load and the store of the same mode? */
563 is_equal = get_ia32_ls_mode(load) == get_ia32_ls_mode(store);
571 * Folds Add or Sub to LEA if possible
573 static ir_node *fold_addr(be_abi_irg_t *babi, ir_node *irn, firm_dbg_module_t *mod, ir_node *noreg) {
574 ir_graph *irg = get_irn_irg(irn);
575 dbg_info *dbg = get_irn_dbg_info(irn);
576 ir_node *block = get_nodes_block(irn);
579 const char *offs_cnst = NULL;
580 char *offs_lea = NULL;
584 ir_node *left, *right, *temp;
585 ir_node *base, *index;
586 ia32_am_flavour_t am_flav;
588 if (is_ia32_Add(irn))
591 left = get_irn_n(irn, 2);
592 right = get_irn_n(irn, 3);
594 /* "normalize" arguments in case of add with two operands */
595 if (isadd && ! be_is_NoReg(babi, right)) {
596 /* put LEA == ia32_am_O as right operand */
597 if (is_ia32_Lea(left) && get_ia32_am_flavour(left) == ia32_am_O) {
598 set_irn_n(irn, 2, right);
599 set_irn_n(irn, 3, left);
605 /* put LEA != ia32_am_O as left operand */
606 if (is_ia32_Lea(right) && get_ia32_am_flavour(right) != ia32_am_O) {
607 set_irn_n(irn, 2, right);
608 set_irn_n(irn, 3, left);
614 /* put SHL as left operand iff left is NOT a LEA */
615 if (! is_ia32_Lea(left) && pred_is_specific_node(right, is_ia32_Shl)) {
616 set_irn_n(irn, 2, right);
617 set_irn_n(irn, 3, left);
630 /* check if operand is either const */
631 if (is_ia32_ImmConst(irn) || is_ia32_ImmSymConst(irn)) {
632 DBG((mod, LEVEL_1, "\tfound op with imm"));
634 offs_cnst = get_ia32_cnst(irn);
638 /* determine the operand which needs to be checked */
639 if (be_is_NoReg(babi, right)) {
646 /* check if right operand is AMConst (LEA with ia32_am_O) */
647 if (is_ia32_Lea(temp) && get_ia32_am_flavour(temp) == ia32_am_O) {
648 DBG((mod, LEVEL_1, "\tgot op with LEA am_O"));
650 offs_lea = get_ia32_am_offs(temp);
655 /* default for add -> make right operand to index */
659 DBG((mod, LEVEL_1, "\tgot LEA candidate with index %+F\n", index));
661 /* determine the operand which needs to be checked */
663 if (is_ia32_Lea(left)) {
667 /* check for SHL 1,2,3 */
668 if (pred_is_specific_node(temp, is_ia32_Shl)) {
669 temp = get_Proj_pred(temp);
671 if (get_ia32_Immop_tarval(temp)) {
672 scale = get_tarval_long(get_ia32_Immop_tarval(temp));
675 index = get_irn_n(temp, 2);
677 DBG((mod, LEVEL_1, "\tgot scaled index %+F\n", index));
683 if (! be_is_NoReg(babi, index)) {
684 /* if we have index, but left == right -> no base */
688 else if (! is_ia32_Lea(left) && (index != right)) {
689 /* index != right -> we found a good Shl */
690 /* left != LEA -> this Shl was the left operand */
691 /* -> base is right operand */
697 /* Try to assimilate a LEA as left operand */
698 if (is_ia32_Lea(left) && (get_ia32_am_flavour(left) != ia32_am_O)) {
699 am_flav = get_ia32_am_flavour(left);
701 /* If we have an Add with a real right operand (not NoReg) and */
702 /* the LEA contains already an index calculation then we create */
704 /* If the LEA contains already a frame_entity then we also */
705 /* create a new one otherwise we would loose it. */
706 if ((isadd && !be_is_NoReg(babi, index) && (am_flav & ia32_am_I)) ||
707 get_ia32_frame_ent(left))
709 DBG((mod, LEVEL_1, "\tleave old LEA, creating new one\n"));
712 DBG((mod, LEVEL_1, "\tgot LEA as left operand ... assimilating\n"));
713 offs = get_ia32_am_offs(left);
714 base = get_irn_n(left, 0);
715 index = get_irn_n(left, 1);
716 scale = get_ia32_am_scale(left);
720 /* ok, we can create a new LEA */
722 res = new_rd_ia32_Lea(dbg, irg, block, base, index, mode_Is);
724 /* add the old offset of a previous LEA */
726 add_ia32_am_offs(res, offs);
729 /* add the new offset */
732 add_ia32_am_offs(res, offs_cnst);
735 add_ia32_am_offs(res, offs_lea);
739 /* either lea_O-cnst, -cnst or -lea_O */
742 add_ia32_am_offs(res, offs_lea);
745 sub_ia32_am_offs(res, offs_cnst);
748 sub_ia32_am_offs(res, offs_lea);
752 /* copy the frame entity (could be set in case of Add */
753 /* which was a FrameAddr) */
754 set_ia32_frame_ent(res, get_ia32_frame_ent(irn));
756 if (is_ia32_use_frame(irn))
757 set_ia32_use_frame(res);
760 set_ia32_am_scale(res, scale);
763 /* determine new am flavour */
764 if (offs || offs_cnst || offs_lea) {
767 if (! be_is_NoReg(babi, base)) {
770 if (! be_is_NoReg(babi, index)) {
776 set_ia32_am_flavour(res, am_flav);
778 set_ia32_op_type(res, ia32_AddrModeS);
780 DBG((mod, LEVEL_1, "\tLEA [%+F + %+F * %d + %s]\n", base, index, scale, get_ia32_am_offs(res)));
782 /* get the result Proj of the Add/Sub */
783 irn = get_res_proj(irn);
785 assert(irn && "Couldn't find result proj");
787 /* exchange the old op with the new LEA */
795 * Optimizes a pattern around irn to address mode if possible.
797 void ia32_optimize_am(ir_node *irn, void *env) {
798 ia32_code_gen_t *cg = env;
799 firm_dbg_module_t *mod = cg->mod;
801 be_abi_irg_t *babi = cg->birg->abi;
804 ir_node *block, *noreg_gp, *noreg_fp;
805 ir_node *left, *right, *temp;
806 ir_node *store, *load, *mem_proj;
807 ir_node *succ, *addr_b, *addr_i;
808 int check_am_src = 0;
810 if (! is_ia32_irn(irn))
813 dbg = get_irn_dbg_info(irn);
814 mode = get_irn_mode(irn);
815 block = get_nodes_block(irn);
816 noreg_gp = ia32_new_NoReg_gp(cg);
817 noreg_fp = ia32_new_NoReg_fp(cg);
819 DBG((mod, LEVEL_1, "checking for AM\n"));
821 /* 1st part: check for address calculations and transform the into Lea */
823 /* Following cases can occur: */
824 /* - Sub (l, imm) -> LEA [base - offset] */
825 /* - Sub (l, r == LEA with ia32_am_O) -> LEA [base - offset] */
826 /* - Add (l, imm) -> LEA [base + offset] */
827 /* - Add (l, r == LEA with ia32_am_O) -> LEA [base + offset] */
828 /* - Add (l == LEA with ia32_am_O, r) -> LEA [base + offset] */
829 /* - Add (l, r) -> LEA [base + index * scale] */
830 /* with scale > 1 iff l/r == shl (1,2,3) */
832 if (is_ia32_Sub(irn) || is_ia32_Add(irn)) {
833 left = get_irn_n(irn, 2);
834 right = get_irn_n(irn, 3);
836 /* Do not try to create a LEA if one of the operands is a Load. */
837 /* check is irn is a candidate for address calculation */
838 if (is_candidate(block, irn, 1)) {
839 DBG((mod, LEVEL_1, "\tfound address calculation candidate %+F ... ", irn));
840 res = fold_addr(babi, irn, mod, noreg_gp);
843 DB((mod, LEVEL_1, "transformed into %+F\n", res));
845 DB((mod, LEVEL_1, "not transformed\n"));
849 /* 2nd part: fold following patterns: */
850 /* - Load -> LEA into Load } TODO: If the LEA is used by more than one Load/Store */
851 /* - Store -> LEA into Store } it might be better to keep the LEA */
852 /* - op -> Load into AMop with am_Source */
854 /* - op is am_Source capable AND */
855 /* - the Load is only used by this op AND */
856 /* - the Load is in the same block */
857 /* - Store -> op -> Load into AMop with am_Dest */
859 /* - op is am_Dest capable AND */
860 /* - the Store uses the same address as the Load AND */
861 /* - the Load is only used by this op AND */
862 /* - the Load and Store are in the same block AND */
863 /* - nobody else uses the result of the op */
865 if ((res == irn) && (get_ia32_am_support(irn) != ia32_am_None) && !is_ia32_Lea(irn)) {
866 /* 1st: check for Load/Store -> LEA */
867 if (is_ia32_Ld(irn) || is_ia32_St(irn) || is_ia32_Store8Bit(irn)) {
868 left = get_irn_n(irn, 0);
870 if (is_ia32_Lea(left)) {
871 DBG((mod, LEVEL_1, "\nmerging %+F into %+F\n", left, irn));
873 /* get the AM attributes from the LEA */
874 add_ia32_am_offs(irn, get_ia32_am_offs(left));
875 set_ia32_am_scale(irn, get_ia32_am_scale(left));
876 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
878 set_ia32_op_type(irn, is_ia32_Ld(irn) ? ia32_AddrModeS : ia32_AddrModeD);
880 /* set base and index */
881 set_irn_n(irn, 0, get_irn_n(left, 0));
882 set_irn_n(irn, 1, get_irn_n(left, 1));
884 /* clear remat flag */
885 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
888 /* check if the node is an address mode candidate */
889 else if (is_candidate(block, irn, 0)) {
890 DBG((mod, LEVEL_1, "\tfound address mode candidate %+F ... ", irn));
892 left = get_irn_n(irn, 2);
893 if (get_irn_arity(irn) == 4) {
894 /* it's an "unary" operation */
898 right = get_irn_n(irn, 3);
901 /* normalize commutative ops */
902 if (node_is_comm(irn)) {
903 /* Assure that right operand is always a Load if there is one */
904 /* because non-commutative ops can only use Dest AM if the right */
905 /* operand is a load, so we only need to check right operand. */
906 if (pred_is_specific_nodeblock(block, left, is_ia32_Ld))
908 set_irn_n(irn, 2, right);
909 set_irn_n(irn, 3, left);
917 /* check for Store -> op -> Load */
919 /* Store -> op -> Load optimization is only possible if supported by op */
920 /* and if right operand is a Load */
921 if ((get_ia32_am_support(irn) & ia32_am_Dest) &&
922 pred_is_specific_nodeblock(block, right, is_ia32_Ld))
925 /* An address mode capable op always has a result Proj. */
926 /* If this Proj is used by more than one other node, we don't need to */
927 /* check further, otherwise we check for Store and remember the address, */
928 /* the Store points to. */
930 succ = get_res_proj(irn);
931 assert(succ && "Couldn't find result proj");
937 /* now check for users and Store */
938 if (ia32_get_irn_n_edges(succ) == 1) {
939 succ = get_edge_src_irn(get_irn_out_edge_first(succ));
941 if (is_ia32_fStore(succ) || is_ia32_Store(succ)) {
943 addr_b = get_irn_n(store, 0);
945 /* Could be that the Store is connected to the address */
946 /* calculating LEA while the Load is already transformed. */
947 if (is_ia32_Lea(addr_b)) {
949 addr_b = get_irn_n(succ, 0);
950 addr_i = get_irn_n(succ, 1);
959 /* we found a Store as single user: Now check for Load */
961 /* Extra check for commutative ops with two Loads */
962 /* -> put the interesting Load right */
963 if (node_is_comm(irn) &&
964 pred_is_specific_nodeblock(block, left, is_ia32_Ld))
966 if ((addr_b == get_irn_n(get_Proj_pred(left), 0)) &&
967 (addr_i == get_irn_n(get_Proj_pred(left), 1)))
969 /* We exchange left and right, so it's easier to kill */
970 /* the correct Load later and to handle unary operations. */
971 set_irn_n(irn, 2, right);
972 set_irn_n(irn, 3, left);
980 /* skip the Proj for easier access */
981 load = get_Proj_pred(right);
983 /* Compare Load and Store address */
984 if (load_store_addr_is_equal(load, store, addr_b, addr_i)) {
985 /* Right Load is from same address, so we can */
986 /* disconnect the Load and Store here */
988 /* set new base, index and attributes */
989 set_irn_n(irn, 0, addr_b);
990 set_irn_n(irn, 1, addr_i);
991 add_ia32_am_offs(irn, get_ia32_am_offs(load));
992 set_ia32_am_scale(irn, get_ia32_am_scale(load));
993 set_ia32_am_flavour(irn, get_ia32_am_flavour(load));
994 set_ia32_op_type(irn, ia32_AddrModeD);
995 set_ia32_frame_ent(irn, get_ia32_frame_ent(load));
996 set_ia32_ls_mode(irn, get_ia32_ls_mode(load));
998 if (is_ia32_use_frame(load))
999 set_ia32_use_frame(irn);
1001 /* connect to Load memory and disconnect Load */
1002 if (get_irn_arity(irn) == 5) {
1004 set_irn_n(irn, 4, get_irn_n(load, 2));
1005 set_irn_n(irn, 3, noreg_gp);
1009 set_irn_n(irn, 3, get_irn_n(load, 2));
1010 set_irn_n(irn, 2, noreg_gp);
1013 /* connect the memory Proj of the Store to the op */
1014 mem_proj = get_mem_proj(store);
1015 set_Proj_pred(mem_proj, irn);
1016 set_Proj_proj(mem_proj, 1);
1018 /* clear remat flag */
1019 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1021 DB((mod, LEVEL_1, "merged with %+F and %+F into dest AM\n", load, store));
1024 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1025 /* There was no store, check if we still can optimize for source address mode */
1028 } /* if (support AM Dest) */
1029 else if (get_ia32_am_support(irn) & ia32_am_Source) {
1030 /* op doesn't support am AM Dest -> check for AM Source */
1034 /* normalize commutative ops */
1035 if (node_is_comm(irn)) {
1036 /* Assure that left operand is always a Load if there is one */
1037 /* because non-commutative ops can only use Source AM if the */
1038 /* left operand is a Load, so we only need to check the left */
1039 /* operand afterwards. */
1040 if (pred_is_specific_nodeblock(block, right, is_ia32_Ld)) {
1041 set_irn_n(irn, 2, right);
1042 set_irn_n(irn, 3, left);
1050 /* optimize op -> Load iff Load is only used by this op */
1051 /* and left operand is a Load which only used by this irn */
1053 pred_is_specific_nodeblock(block, left, is_ia32_Ld) &&
1054 (ia32_get_irn_n_edges(left) == 1))
1056 left = get_Proj_pred(left);
1058 addr_b = get_irn_n(left, 0);
1059 addr_i = get_irn_n(left, 1);
1061 /* set new base, index and attributes */
1062 set_irn_n(irn, 0, addr_b);
1063 set_irn_n(irn, 1, addr_i);
1064 add_ia32_am_offs(irn, get_ia32_am_offs(left));
1065 set_ia32_am_scale(irn, get_ia32_am_scale(left));
1066 set_ia32_am_flavour(irn, get_ia32_am_flavour(left));
1067 set_ia32_op_type(irn, ia32_AddrModeS);
1068 set_ia32_frame_ent(irn, get_ia32_frame_ent(left));
1069 set_ia32_ls_mode(irn, get_ia32_ls_mode(left));
1071 /* clear remat flag */
1072 set_ia32_flags(irn, get_ia32_flags(irn) & ~arch_irn_flags_rematerializable);
1074 if (is_ia32_use_frame(left))
1075 set_ia32_use_frame(irn);
1077 /* connect to Load memory */
1078 if (get_irn_arity(irn) == 5) {
1080 set_irn_n(irn, 4, get_irn_n(left, 2));
1084 set_irn_n(irn, 3, get_irn_n(left, 2));
1087 /* disconnect from Load */
1088 set_irn_n(irn, 2, noreg_gp);
1090 /* If Load has a memory Proj, connect it to the op */
1091 mem_proj = get_mem_proj(left);
1093 set_Proj_pred(mem_proj, irn);
1094 set_Proj_proj(mem_proj, 1);
1097 DB((mod, LEVEL_1, "merged with %+F into source AM\n", left));