2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
64 static void peephole_IncSP_IncSP(ir_node *node);
67 static void peephole_ia32_Store_IncSP_to_push(ir_node *node)
69 ir_node *base = get_irn_n(node, n_ia32_Store_base);
70 ir_node *index = get_irn_n(node, n_ia32_Store_index);
71 ir_node *mem = get_irn_n(node, n_ia32_Store_mem);
72 ir_node *incsp = base;
84 /* nomem inidicates the store doesn't alias with anything else */
88 /* find an IncSP in front of us, we might have to skip barriers for this */
89 while(is_Proj(incsp)) {
90 ir_node *proj_pred = get_Proj_pred(incsp);
91 if(!be_is_Barrier(proj_pred))
93 incsp = get_irn_n(proj_pred, get_Proj_proj(incsp));
95 if(!be_is_IncSP(incsp))
98 peephole_IncSP_IncSP(incsp);
100 /* must be in the same block */
101 if(get_nodes_block(incsp) != get_nodes_block(node))
104 if(!is_ia32_NoReg_GP(index) || get_ia32_am_sc(node) != NULL) {
105 panic("Invalid storeAM found (%+F)", node);
108 /* we should be the store to the end of the stackspace */
109 offset = be_get_IncSP_offset(incsp);
110 mode = get_ia32_ls_mode(node);
111 node_offset = get_ia32_am_offs_int(node);
112 if(node_offset != offset - get_mode_size_bytes(mode))
115 /* we can use a push instead of the store */
116 irg = current_ir_graph;
117 block = get_nodes_block(node);
118 dbgi = get_irn_dbg_info(node);
119 noreg = ia32_new_NoReg_gp(cg);
120 base = be_get_IncSP_pred(incsp);
121 val = get_irn_n(node, n_ia32_Store_val);
122 push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, mem, base, val);
124 proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
126 be_set_IncSP_offset(incsp, offset - get_mode_size_bytes(mode));
128 sched_add_before(node, push);
131 be_peephole_before_exchange(node, proj);
132 exchange(node, proj);
133 be_peephole_after_exchange(proj);
136 static void peephole_ia32_Store(ir_node *node)
138 peephole_ia32_Store_IncSP_to_push(node);
142 static int produces_zero_flag(ir_node *node, int pn)
145 const ia32_immediate_attr_t *imm_attr;
147 if(!is_ia32_irn(node))
151 if(pn != pn_ia32_res)
155 switch(get_ia32_irn_opcode(node)) {
173 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
174 assert(n_ia32_Shl_count == n_ia32_Shr_count
175 && n_ia32_Shl_count == n_ia32_Sar_count);
176 if(is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
177 count = get_irn_n(node, n_ia32_ShlD_count);
179 count = get_irn_n(node, n_ia32_Shl_count);
181 /* when shift count is zero the flags are not affected, so we can only
182 * do this for constants != 0 */
183 if(!is_ia32_Immediate(count))
186 imm_attr = get_ia32_immediate_attr_const(count);
187 if(imm_attr->symconst != NULL)
189 if((imm_attr->offset & 0x1f) == 0)
199 static ir_node *turn_into_mode_t(ir_node *node)
204 const arch_register_t *reg;
206 if(get_irn_mode(node) == mode_T)
209 assert(get_irn_mode(node) == mode_Iu);
211 new_node = exact_copy(node);
212 set_irn_mode(new_node, mode_T);
214 block = get_nodes_block(new_node);
215 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
218 reg = arch_get_irn_register(arch_env, node);
219 arch_set_irn_register(arch_env, res_proj, reg);
221 be_peephole_before_exchange(node, res_proj);
222 sched_add_before(node, new_node);
224 exchange(node, res_proj);
225 be_peephole_after_exchange(res_proj);
230 static void peephole_ia32_Test(ir_node *node)
232 ir_node *left = get_irn_n(node, n_ia32_Test_left);
233 ir_node *right = get_irn_n(node, n_ia32_Test_right);
239 const ir_edge_t *edge;
241 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
242 && n_ia32_Test_right == n_ia32_Test8Bit_right);
244 /* we need a test for 0 */
248 block = get_nodes_block(node);
249 if(get_nodes_block(left) != block)
253 pn = get_Proj_proj(left);
254 left = get_Proj_pred(left);
257 /* happens rarely, but if it does code will panic' */
258 if (is_ia32_Unknown_GP(left))
261 /* walk schedule up and abort when we find left or some other node destroys
263 schedpoint = sched_prev(node);
264 while(schedpoint != left) {
265 schedpoint = sched_prev(schedpoint);
266 if(arch_irn_is(arch_env, schedpoint, modify_flags))
268 if(schedpoint == block)
269 panic("couldn't find left");
272 /* make sure only Lg/Eq tests are used */
273 foreach_out_edge(node, edge) {
274 ir_node *user = get_edge_src_irn(edge);
275 int pnc = get_ia32_condcode(user);
277 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
282 if(!produces_zero_flag(left, pn))
285 left = turn_into_mode_t(left);
287 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
288 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
290 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
292 assert(get_irn_mode(node) != mode_T);
294 be_peephole_before_exchange(node, flags_proj);
295 exchange(node, flags_proj);
297 be_peephole_after_exchange(flags_proj);
301 * AMD Athlon works faster when RET is not destination of
302 * conditional jump or directly preceded by other jump instruction.
303 * Can be avoided by placing a Rep prefix before the return.
305 static void peephole_ia32_Return(ir_node *node) {
306 ir_node *block, *irn, *rep;
308 if (!ia32_cg_config.use_pad_return)
311 block = get_nodes_block(node);
313 /* check if this return is the first on the block */
314 sched_foreach_reverse_from(node, irn) {
315 switch (be_get_irn_opcode(irn)) {
317 /* the return node itself, ignore */
320 /* ignore the barrier, no code generated */
323 /* arg, IncSP 0 nodes might occur, ignore these */
324 if (be_get_IncSP_offset(irn) == 0)
333 /* yep, return is the first real instruction in this block */
334 rep = new_rd_ia32_RepPrefix(get_irn_dbg_info(node), current_ir_graph, block);
336 sched_add_before(node, rep);
339 /* only optimize up to 48 stores behind IncSPs */
340 #define MAXPUSH_OPTIMIZE 48
343 * Tries to create pushs from IncSP,Store combinations.
344 * The Stores are replaced by Push's, the IncSP is modified
345 * (possibly into IncSP 0, but not removed).
347 static void peephole_IncSP_Store_to_push(ir_node *irn)
352 ir_node *stores[MAXPUSH_OPTIMIZE];
353 ir_node *block = get_nodes_block(irn);
354 ir_graph *irg = cg->irg;
356 ir_mode *spmode = get_irn_mode(irn);
358 memset(stores, 0, sizeof(stores));
360 assert(be_is_IncSP(irn));
362 offset = be_get_IncSP_offset(irn);
367 * We first walk the schedule after the IncSP node as long as we find
368 * suitable stores that could be transformed to a push.
369 * We save them into the stores array which is sorted by the frame offset/4
370 * attached to the node
372 for(node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
377 // it has to be a store
378 if(!is_ia32_Store(node))
381 // it has to use our sp value
382 if(get_irn_n(node, n_ia32_base) != irn)
384 // store has to be attached to NoMem
385 mem = get_irn_n(node, n_ia32_mem);
390 /* unfortunately we can't support the full AMs possible for push at the
391 * moment. TODO: fix this */
392 if(get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
395 offset = get_ia32_am_offs_int(node);
397 storeslot = offset / 4;
398 if(storeslot >= MAXPUSH_OPTIMIZE)
401 // storing into the same slot twice is bad (and shouldn't happen...)
402 if(stores[storeslot] != NULL)
405 // storing at half-slots is bad
409 stores[storeslot] = node;
412 curr_sp = be_get_IncSP_pred(irn);
414 // walk the stores in inverse order and create pushs for them
415 i = (offset / 4) - 1;
416 if(i >= MAXPUSH_OPTIMIZE) {
417 i = MAXPUSH_OPTIMIZE - 1;
420 for( ; i >= 0; --i) {
421 const arch_register_t *spreg;
423 ir_node *val, *mem, *mem_proj;
424 ir_node *store = stores[i];
425 ir_node *noreg = ia32_new_NoReg_gp(cg);
427 if(store == NULL || is_Bad(store))
430 val = get_irn_n(store, n_ia32_unary_op);
431 mem = get_irn_n(store, n_ia32_mem);
432 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
434 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, curr_sp, val);
436 sched_add_before(irn, push);
438 // create stackpointer proj
439 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
440 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
442 // create memory proj
443 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
445 // use the memproj now
446 exchange(store, mem_proj);
448 // we can remove the store now
454 be_set_IncSP_offset(irn, offset);
455 be_set_IncSP_pred(irn, curr_sp);
459 * Tries to optimize two following IncSP.
461 static void peephole_IncSP_IncSP(ir_node *node)
466 ir_node *pred = be_get_IncSP_pred(node);
469 if(!be_is_IncSP(pred))
472 if(get_irn_n_edges(pred) > 1)
475 pred_offs = be_get_IncSP_offset(pred);
476 curr_offs = be_get_IncSP_offset(node);
478 if(pred_offs == BE_STACK_FRAME_SIZE_EXPAND) {
479 if(curr_offs != BE_STACK_FRAME_SIZE_SHRINK) {
483 } else if(pred_offs == BE_STACK_FRAME_SIZE_SHRINK) {
484 if(curr_offs != BE_STACK_FRAME_SIZE_EXPAND) {
488 } else if(curr_offs == BE_STACK_FRAME_SIZE_EXPAND
489 || curr_offs == BE_STACK_FRAME_SIZE_SHRINK) {
492 offs = curr_offs + pred_offs;
495 /* add pred offset to ours and remove pred IncSP */
496 be_set_IncSP_offset(node, offs);
498 predpred = be_get_IncSP_pred(pred);
499 be_peephole_before_exchange(pred, predpred);
501 /* rewire dependency edges */
502 edges_reroute_kind(pred, predpred, EDGE_KIND_DEP, current_ir_graph);
503 be_set_IncSP_pred(node, predpred);
507 be_peephole_after_exchange(predpred);
511 * Find a free GP register if possible, else return NULL.
513 static const arch_register_t *get_free_gp_reg(void)
517 for(i = 0; i < N_ia32_gp_REGS; ++i) {
518 const arch_register_t *reg = &ia32_gp_regs[i];
519 if(arch_register_type_is(reg, ignore))
522 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
523 return &ia32_gp_regs[i];
529 static void peephole_be_IncSP(ir_node *node)
531 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
532 const arch_register_t *reg;
542 /* first optimize incsp->incsp combinations */
543 peephole_IncSP_IncSP(node);
545 /* transform IncSP->Store combinations to Push where possible */
546 peephole_IncSP_Store_to_push(node);
548 if (arch_get_irn_register(arch_env, node) != esp)
551 /* replace IncSP -4 by Pop freereg when possible */
552 offset = be_get_IncSP_offset(node);
553 if (!(offset == -4 && !ia32_cg_config.use_add_esp_4) &&
554 !(offset == -8 && !ia32_cg_config.use_add_esp_8) &&
555 !(offset == +4 && !ia32_cg_config.use_sub_esp_4) &&
556 !(offset == +8 && !ia32_cg_config.use_sub_esp_8))
560 /* we need a free register for pop */
561 reg = get_free_gp_reg();
565 irg = current_ir_graph;
566 dbgi = get_irn_dbg_info(node);
567 block = get_nodes_block(node);
568 stack = be_get_IncSP_pred(node);
569 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
571 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
572 arch_set_irn_register(arch_env, stack, esp);
573 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
574 arch_set_irn_register(arch_env, val, reg);
576 sched_add_before(node, pop);
578 keep = sched_next(node);
579 if (!be_is_Keep(keep)) {
582 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
583 sched_add_before(node, keep);
585 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
589 pop2 = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
591 stack = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_stack);
592 arch_set_irn_register(arch_env, stack, esp);
593 val = new_r_Proj(irg, block, pop2, mode_Iu, pn_ia32_Pop_res);
594 arch_set_irn_register(arch_env, val, reg);
596 sched_add_after(pop, pop2);
597 be_Keep_add_node(keep, &ia32_reg_classes[CLASS_ia32_gp], val);
604 be_peephole_before_exchange(node, stack);
606 exchange(node, stack);
607 be_peephole_after_exchange(stack);
611 * Peephole optimisation for ia32_Const's
613 static void peephole_ia32_Const(ir_node *node)
615 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
616 const arch_register_t *reg;
617 ir_graph *irg = current_ir_graph;
624 /* try to transform a mov 0, reg to xor reg reg */
625 if (attr->offset != 0 || attr->symconst != NULL)
627 if (ia32_cg_config.use_mov_0)
629 /* xor destroys the flags, so no-one must be using them */
630 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
633 reg = arch_get_irn_register(arch_env, node);
634 assert(be_peephole_get_reg_value(reg) == NULL);
636 /* create xor(produceval, produceval) */
637 block = get_nodes_block(node);
638 dbgi = get_irn_dbg_info(node);
639 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
640 arch_set_irn_register(arch_env, produceval, reg);
642 noreg = ia32_new_NoReg_gp(cg);
643 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
644 produceval, produceval);
645 arch_set_irn_register(arch_env, xor, reg);
647 sched_add_before(node, produceval);
648 sched_add_before(node, xor);
650 be_peephole_before_exchange(node, xor);
653 be_peephole_after_exchange(xor);
656 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
658 return node == cg->noreg_gp;
661 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
663 ir_graph *irg = current_ir_graph;
664 ir_node *start_block = get_irg_start_block(irg);
665 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
667 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
672 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
675 ir_graph *irg = get_irn_irg(node);
676 ir_node *block = get_nodes_block(node);
677 int offset = get_ia32_am_offs_int(node);
678 int sc_sign = is_ia32_am_sc_sign(node);
679 ir_entity *entity = get_ia32_am_sc(node);
682 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
683 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
687 static int is_am_one(const ir_node *node)
689 int offset = get_ia32_am_offs_int(node);
690 ir_entity *entity = get_ia32_am_sc(node);
692 return offset == 1 && entity == NULL;
695 static int is_am_minus_one(const ir_node *node)
697 int offset = get_ia32_am_offs_int(node);
698 ir_entity *entity = get_ia32_am_sc(node);
700 return offset == -1 && entity == NULL;
704 * Transforms a LEA into an Add or SHL if possible.
706 static void peephole_ia32_Lea(ir_node *node)
708 const arch_env_t *arch_env = cg->arch_env;
709 ir_graph *irg = current_ir_graph;
712 const arch_register_t *base_reg;
713 const arch_register_t *index_reg;
714 const arch_register_t *out_reg;
725 assert(is_ia32_Lea(node));
727 /* we can only do this if are allowed to globber the flags */
728 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
731 base = get_irn_n(node, n_ia32_Lea_base);
732 index = get_irn_n(node, n_ia32_Lea_index);
734 if(is_noreg(cg, base)) {
738 base_reg = arch_get_irn_register(arch_env, base);
740 if(is_noreg(cg, index)) {
744 index_reg = arch_get_irn_register(arch_env, index);
747 if(base == NULL && index == NULL) {
748 /* we shouldn't construct these in the first place... */
750 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
755 out_reg = arch_get_irn_register(arch_env, node);
756 scale = get_ia32_am_scale(node);
757 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
758 /* check if we have immediates values (frame entities should already be
759 * expressed in the offsets) */
760 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
766 /* we can transform leas where the out register is the same as either the
767 * base or index register back to an Add or Shl */
768 if(out_reg == base_reg) {
771 if(!has_immediates) {
772 ir_fprintf(stderr, "Optimisation warning: found lea which is "
777 goto make_add_immediate;
779 if(scale == 0 && !has_immediates) {
784 /* can't create an add */
786 } else if(out_reg == index_reg) {
788 if(has_immediates && scale == 0) {
790 goto make_add_immediate;
791 } else if(!has_immediates && scale > 0) {
793 op2 = create_immediate_from_int(cg, scale);
795 } else if(!has_immediates) {
797 ir_fprintf(stderr, "Optimisation warning: found lea which is "
801 } else if(scale == 0 && !has_immediates) {
806 /* can't create an add */
809 /* can't create an add */
814 if(ia32_cg_config.use_incdec) {
815 if(is_am_one(node)) {
816 dbgi = get_irn_dbg_info(node);
817 block = get_nodes_block(node);
818 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
819 arch_set_irn_register(arch_env, res, out_reg);
822 if(is_am_minus_one(node)) {
823 dbgi = get_irn_dbg_info(node);
824 block = get_nodes_block(node);
825 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
826 arch_set_irn_register(arch_env, res, out_reg);
830 op2 = create_immediate_from_am(cg, node);
833 dbgi = get_irn_dbg_info(node);
834 block = get_nodes_block(node);
835 noreg = ia32_new_NoReg_gp(cg);
837 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
838 arch_set_irn_register(arch_env, res, out_reg);
839 set_ia32_commutative(res);
843 dbgi = get_irn_dbg_info(node);
844 block = get_nodes_block(node);
845 noreg = ia32_new_NoReg_gp(cg);
847 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
848 arch_set_irn_register(arch_env, res, out_reg);
852 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
854 /* add new ADD/SHL to schedule */
855 DBG_OPT_LEA2ADD(node, res);
857 /* exchange the Add and the LEA */
858 be_peephole_before_exchange(node, res);
859 sched_add_before(node, res);
862 be_peephole_after_exchange(res);
866 * Register a peephole optimisation function.
868 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
869 assert(op->ops.generic == NULL);
870 op->ops.generic = (void*) func;
873 /* Perform peephole-optimizations. */
874 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
877 arch_env = cg->arch_env;
879 /* register peephole optimisations */
880 clear_irp_opcodes_generic_func();
881 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
882 //register_peephole_optimisation(op_ia32_Store, peephole_ia32_Store);
883 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
884 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
885 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
886 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
887 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
889 be_peephole_opt(cg->birg);
893 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
894 * all it's Projs are removed as well.
895 * @param irn The irn to be removed from schedule
897 static INLINE void try_kill(ir_node *node)
899 if(get_irn_mode(node) == mode_T) {
900 const ir_edge_t *edge, *next;
901 foreach_out_edge_safe(node, edge, next) {
902 ir_node *proj = get_edge_src_irn(edge);
907 if(get_irn_n_edges(node) != 0)
910 if (sched_is_scheduled(node)) {
917 static void optimize_conv_store(ir_node *node)
924 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
927 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
928 pred_proj = get_irn_n(node, n_ia32_Store_val);
929 if(is_Proj(pred_proj)) {
930 pred = get_Proj_pred(pred_proj);
934 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
936 if(get_ia32_op_type(pred) != ia32_Normal)
939 /* the store only stores the lower bits, so we only need the conv
940 * it it shrinks the mode */
941 conv_mode = get_ia32_ls_mode(pred);
942 store_mode = get_ia32_ls_mode(node);
943 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
946 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
947 if(get_irn_n_edges(pred_proj) == 0) {
948 be_kill_node(pred_proj);
949 if(pred != pred_proj)
954 static void optimize_load_conv(ir_node *node)
956 ir_node *pred, *predpred;
960 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
963 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
964 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
968 predpred = get_Proj_pred(pred);
969 if(!is_ia32_Load(predpred))
972 /* the load is sign extending the upper bits, so we only need the conv
973 * if it shrinks the mode */
974 load_mode = get_ia32_ls_mode(predpred);
975 conv_mode = get_ia32_ls_mode(node);
976 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
979 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
980 /* change the load if it has only 1 user */
981 if(get_irn_n_edges(pred) == 1) {
983 if(get_mode_sign(conv_mode)) {
984 newmode = find_signed_mode(load_mode);
986 newmode = find_unsigned_mode(load_mode);
988 assert(newmode != NULL);
989 set_ia32_ls_mode(predpred, newmode);
991 /* otherwise we have to keep the conv */
997 exchange(node, pred);
1000 static void optimize_conv_conv(ir_node *node)
1002 ir_node *pred_proj, *pred, *result_conv;
1003 ir_mode *pred_mode, *conv_mode;
1007 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1010 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1011 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1012 if(is_Proj(pred_proj))
1013 pred = get_Proj_pred(pred_proj);
1017 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1020 /* we know that after a conv, the upper bits are sign extended
1021 * so we only need the 2nd conv if it shrinks the mode */
1022 conv_mode = get_ia32_ls_mode(node);
1023 conv_mode_bits = get_mode_size_bits(conv_mode);
1024 pred_mode = get_ia32_ls_mode(pred);
1025 pred_mode_bits = get_mode_size_bits(pred_mode);
1027 if(conv_mode_bits == pred_mode_bits
1028 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1029 result_conv = pred_proj;
1030 } else if(conv_mode_bits <= pred_mode_bits) {
1031 /* if 2nd conv is smaller then first conv, then we can always take the
1033 if(get_irn_n_edges(pred_proj) == 1) {
1034 result_conv = pred_proj;
1035 set_ia32_ls_mode(pred, conv_mode);
1037 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1038 if (get_mode_size_bits(conv_mode) == 8) {
1039 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1040 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1043 /* we don't want to end up with 2 loads, so we better do nothing */
1044 if(get_irn_mode(pred) == mode_T) {
1048 result_conv = exact_copy(pred);
1049 set_ia32_ls_mode(result_conv, conv_mode);
1051 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1052 if (get_mode_size_bits(conv_mode) == 8) {
1053 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1054 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1058 /* if both convs have the same sign, then we can take the smaller one */
1059 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1060 result_conv = pred_proj;
1062 /* no optimisation possible if smaller conv is sign-extend */
1063 if(mode_is_signed(pred_mode)) {
1066 /* we can take the smaller conv if it is unsigned */
1067 result_conv = pred_proj;
1072 exchange(node, result_conv);
1074 if(get_irn_n_edges(pred_proj) == 0) {
1075 be_kill_node(pred_proj);
1076 if(pred != pred_proj)
1079 optimize_conv_conv(result_conv);
1082 static void optimize_node(ir_node *node, void *env)
1086 optimize_load_conv(node);
1087 optimize_conv_store(node);
1088 optimize_conv_conv(node);
1092 * Performs conv and address mode optimization.
1094 void ia32_optimize_graph(ia32_code_gen_t *cg)
1096 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1099 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1102 void ia32_init_optimize(void)
1104 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");