2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Implements several optimizations for IA32.
23 * @author Matthias Braun, Christian Wuerdig
34 #include "firm_types.h"
46 #include "../benode_t.h"
47 #include "../besched_t.h"
48 #include "../bepeephole.h"
50 #include "ia32_new_nodes.h"
51 #include "ia32_optimize.h"
52 #include "bearch_ia32_t.h"
53 #include "gen_ia32_regalloc_if.h"
54 #include "ia32_transform.h"
55 #include "ia32_dbg_stat.h"
56 #include "ia32_util.h"
57 #include "ia32_architecture.h"
59 DEBUG_ONLY(static firm_dbg_module_t *dbg = NULL;)
61 static const arch_env_t *arch_env;
62 static ia32_code_gen_t *cg;
65 * Returns non-zero if the given node produces
68 * @param node the node to check
69 * @param pn if >= 0, the projection number of the used result
71 static int produces_zero_flag(ir_node *node, int pn)
74 const ia32_immediate_attr_t *imm_attr;
76 if (!is_ia32_irn(node))
80 if (pn != pn_ia32_res)
84 switch (get_ia32_irn_opcode(node)) {
102 assert(n_ia32_ShlD_count == n_ia32_ShrD_count);
103 assert(n_ia32_Shl_count == n_ia32_Shr_count
104 && n_ia32_Shl_count == n_ia32_Sar_count);
105 if (is_ia32_ShlD(node) || is_ia32_ShrD(node)) {
106 count = get_irn_n(node, n_ia32_ShlD_count);
108 count = get_irn_n(node, n_ia32_Shl_count);
110 /* when shift count is zero the flags are not affected, so we can only
111 * do this for constants != 0 */
112 if (!is_ia32_Immediate(count))
115 imm_attr = get_ia32_immediate_attr_const(count);
116 if (imm_attr->symconst != NULL)
118 if ((imm_attr->offset & 0x1f) == 0)
129 * If the given node has not mode_T, creates a mode_T version (with a result Proj).
131 * @param node the node to change
133 * @return the new mode_T node (if the mode was changed) or node itself
135 static ir_node *turn_into_mode_t(ir_node *node)
140 const arch_register_t *reg;
142 if(get_irn_mode(node) == mode_T)
145 assert(get_irn_mode(node) == mode_Iu);
147 new_node = exact_copy(node);
148 set_irn_mode(new_node, mode_T);
150 block = get_nodes_block(new_node);
151 res_proj = new_r_Proj(current_ir_graph, block, new_node, mode_Iu,
154 reg = arch_get_irn_register(arch_env, node);
155 arch_set_irn_register(arch_env, res_proj, reg);
157 sched_add_before(node, new_node);
158 be_peephole_exchange(node, res_proj);
163 * Peephole optimization for Test instructions.
164 * We can remove the Test, if a zero flags was produced which is still
167 static void peephole_ia32_Test(ir_node *node)
169 ir_node *left = get_irn_n(node, n_ia32_Test_left);
170 ir_node *right = get_irn_n(node, n_ia32_Test_right);
176 const ir_edge_t *edge;
178 assert(n_ia32_Test_left == n_ia32_Test8Bit_left
179 && n_ia32_Test_right == n_ia32_Test8Bit_right);
181 /* we need a test for 0 */
185 block = get_nodes_block(node);
186 if(get_nodes_block(left) != block)
190 pn = get_Proj_proj(left);
191 left = get_Proj_pred(left);
194 /* happens rarely, but if it does code will panic' */
195 if (is_ia32_Unknown_GP(left))
198 /* walk schedule up and abort when we find left or some other node destroys
200 schedpoint = sched_prev(node);
201 while(schedpoint != left) {
202 schedpoint = sched_prev(schedpoint);
203 if(arch_irn_is(arch_env, schedpoint, modify_flags))
205 if(schedpoint == block)
206 panic("couldn't find left");
209 /* make sure only Lg/Eq tests are used */
210 foreach_out_edge(node, edge) {
211 ir_node *user = get_edge_src_irn(edge);
212 int pnc = get_ia32_condcode(user);
214 if(pnc != pn_Cmp_Eq && pnc != pn_Cmp_Lg) {
219 if(!produces_zero_flag(left, pn))
222 left = turn_into_mode_t(left);
224 flags_mode = ia32_reg_classes[CLASS_ia32_flags].mode;
225 flags_proj = new_r_Proj(current_ir_graph, block, left, flags_mode,
227 arch_set_irn_register(arch_env, flags_proj, &ia32_flags_regs[REG_EFLAGS]);
229 assert(get_irn_mode(node) != mode_T);
231 be_peephole_exchange(node, flags_proj);
235 * AMD Athlon works faster when RET is not destination of
236 * conditional jump or directly preceded by other jump instruction.
237 * Can be avoided by placing a Rep prefix before the return.
239 static void peephole_ia32_Return(ir_node *node) {
240 ir_node *block, *irn;
242 if (!ia32_cg_config.use_pad_return)
245 block = get_nodes_block(node);
247 /* check if this return is the first on the block */
248 sched_foreach_reverse_from(node, irn) {
249 switch (get_irn_opcode(irn)) {
251 /* the return node itself, ignore */
254 /* ignore the barrier, no code generated */
257 /* arg, IncSP 0 nodes might occur, ignore these */
258 if (be_get_IncSP_offset(irn) == 0)
268 /* ensure, that the 3 byte return is generated
269 * actually the emitter tests again if the block beginning has a label and
270 * isn't just a fallthrough */
271 be_Return_set_emit_pop(node, 1);
274 /* only optimize up to 48 stores behind IncSPs */
275 #define MAXPUSH_OPTIMIZE 48
278 * Tries to create Push's from IncSP, Store combinations.
279 * The Stores are replaced by Push's, the IncSP is modified
280 * (possibly into IncSP 0, but not removed).
282 static void peephole_IncSP_Store_to_push(ir_node *irn)
284 int i, maxslot, inc_ofs;
286 ir_node *stores[MAXPUSH_OPTIMIZE];
292 memset(stores, 0, sizeof(stores));
294 assert(be_is_IncSP(irn));
296 inc_ofs = be_get_IncSP_offset(irn);
301 * We first walk the schedule after the IncSP node as long as we find
302 * suitable Stores that could be transformed to a Push.
303 * We save them into the stores array which is sorted by the frame offset/4
304 * attached to the node
307 for (node = sched_next(irn); !sched_is_end(node); node = sched_next(node)) {
312 /* it has to be a Store */
313 if (!is_ia32_Store(node))
316 /* it has to use our sp value */
317 if (get_irn_n(node, n_ia32_base) != irn)
319 /* Store has to be attached to NoMem */
320 mem = get_irn_n(node, n_ia32_mem);
324 /* unfortunately we can't support the full AMs possible for push at the
325 * moment. TODO: fix this */
326 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
329 offset = get_ia32_am_offs_int(node);
330 /* we should NEVER access uninitialized stack BELOW the current SP */
333 offset = inc_ofs - 4 - offset;
335 /* storing at half-slots is bad */
336 if ((offset & 3) != 0)
339 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
341 storeslot = offset >> 2;
343 /* storing into the same slot twice is bad (and shouldn't happen...) */
344 if (stores[storeslot] != NULL)
347 stores[storeslot] = node;
348 if (storeslot > maxslot)
352 curr_sp = be_get_IncSP_pred(irn);
354 /* walk through the Stores and create Pushs for them */
355 block = get_nodes_block(irn);
356 spmode = get_irn_mode(irn);
358 for (i = 0; i <= maxslot; ++i) {
359 const arch_register_t *spreg;
361 ir_node *val, *mem, *mem_proj;
362 ir_node *store = stores[i];
363 ir_node *noreg = ia32_new_NoReg_gp(cg);
368 val = get_irn_n(store, n_ia32_unary_op);
369 mem = get_irn_n(store, n_ia32_mem);
370 spreg = arch_get_irn_register(cg->arch_env, curr_sp);
372 push = new_rd_ia32_Push(get_irn_dbg_info(store), irg, block, noreg, noreg, mem, val, curr_sp);
374 sched_add_before(irn, push);
376 /* create stackpointer Proj */
377 curr_sp = new_r_Proj(irg, block, push, spmode, pn_ia32_Push_stack);
378 arch_set_irn_register(cg->arch_env, curr_sp, spreg);
380 /* create memory Proj */
381 mem_proj = new_r_Proj(irg, block, push, mode_M, pn_ia32_Push_M);
383 /* use the memproj now */
384 be_peephole_exchange(store, mem_proj);
389 be_set_IncSP_offset(irn, inc_ofs);
390 be_set_IncSP_pred(irn, curr_sp);
394 * Return true if a mode can be stored in the GP register set
396 static INLINE int mode_needs_gp_reg(ir_mode *mode) {
397 if (mode == mode_fpcw)
399 if (get_mode_size_bits(mode) > 32)
401 return mode_is_int(mode) || mode_is_reference(mode) || mode == mode_b;
405 * Tries to create Pops from Load, IncSP combinations.
406 * The Loads are replaced by Pops, the IncSP is modified
407 * (possibly into IncSP 0, but not removed).
409 static void peephole_Load_IncSP_to_pop(ir_node *irn)
411 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
412 int i, maxslot, inc_ofs, ofs;
413 ir_node *node, *pred_sp, *block;
414 ir_node *loads[MAXPUSH_OPTIMIZE];
416 unsigned regmask = 0;
417 unsigned copymask = ~0;
419 memset(loads, 0, sizeof(loads));
420 assert(be_is_IncSP(irn));
422 inc_ofs = -be_get_IncSP_offset(irn);
427 * We first walk the schedule before the IncSP node as long as we find
428 * suitable Loads that could be transformed to a Pop.
429 * We save them into the stores array which is sorted by the frame offset/4
430 * attached to the node
433 pred_sp = be_get_IncSP_pred(irn);
434 for (node = sched_prev(irn); !sched_is_end(node); node = sched_prev(node)) {
438 const arch_register_t *sreg, *dreg;
440 /* it has to be a Load */
441 if (!is_ia32_Load(node)) {
442 if (be_is_Copy(node)) {
443 if (!mode_needs_gp_reg(get_irn_mode(node))) {
444 /* not a GP copy, ignore */
447 dreg = arch_get_irn_register(arch_env, node);
448 sreg = arch_get_irn_register(arch_env, be_get_Copy_op(node));
449 if (regmask & copymask & (1 << sreg->index)) {
452 if (regmask & copymask & (1 << dreg->index)) {
455 /* we CAN skip Copies if neither the destination nor the source
456 * is not in our regmask, ie none of our future Pop will overwrite it */
457 regmask |= (1 << dreg->index) | (1 << sreg->index);
458 copymask &= ~((1 << dreg->index) | (1 << sreg->index));
464 /* we can handle only GP loads */
465 if (!mode_needs_gp_reg(get_ia32_ls_mode(node)))
468 /* it has to use our predecessor sp value */
469 if (get_irn_n(node, n_ia32_base) != pred_sp) {
470 /* it would be ok if this load does not use a Pop result,
471 * but we do not check this */
474 /* Load has to be attached to Spill-Mem */
475 mem = skip_Proj(get_irn_n(node, n_ia32_mem));
476 if (!is_Phi(mem) && !is_ia32_Store(mem) && !is_ia32_Push(mem))
479 /* should have NO index */
480 if (get_ia32_am_scale(node) > 0 || !is_ia32_NoReg_GP(get_irn_n(node, n_ia32_index)))
483 offset = get_ia32_am_offs_int(node);
484 /* we should NEVER access uninitialized stack BELOW the current SP */
487 /* storing at half-slots is bad */
488 if ((offset & 3) != 0)
491 if (offset < 0 || offset >= MAXPUSH_OPTIMIZE * 4)
493 /* ignore those outside the possible windows */
494 if (offset > inc_ofs - 4)
496 loadslot = offset >> 2;
498 /* loading from the same slot twice is bad (and shouldn't happen...) */
499 if (loads[loadslot] != NULL)
502 dreg = arch_get_irn_register(arch_env, node);
503 if (regmask & (1 << dreg->index)) {
504 /* this register is already used */
507 regmask |= 1 << dreg->index;
509 loads[loadslot] = node;
510 if (loadslot > maxslot)
517 /* find the first slot */
518 for (i = maxslot; i >= 0; --i) {
519 ir_node *load = loads[i];
525 ofs = inc_ofs - (maxslot + 1) * 4;
528 /* create a new IncSP if needed */
529 block = get_nodes_block(irn);
532 pred_sp = be_new_IncSP(esp, irg, block, pred_sp, -inc_ofs, be_get_IncSP_align(irn));
533 sched_add_before(irn, pred_sp);
536 /* walk through the Loads and create Pops for them */
537 for (++i; i <= maxslot; ++i) {
538 ir_node *load = loads[i];
540 const ir_edge_t *edge, *tmp;
541 const arch_register_t *reg;
543 mem = get_irn_n(load, n_ia32_mem);
544 reg = arch_get_irn_register(arch_env, load);
546 pop = new_rd_ia32_Pop(get_irn_dbg_info(load), irg, block, mem, pred_sp);
547 arch_set_irn_register(arch_env, pop, reg);
549 /* create stackpointer Proj */
550 pred_sp = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
551 arch_set_irn_register(arch_env, pred_sp, esp);
553 sched_add_before(irn, pop);
556 foreach_out_edge_safe(load, edge, tmp) {
557 ir_node *proj = get_edge_src_irn(edge);
559 set_Proj_pred(proj, pop);
562 /* we can remove the Load now */
567 be_set_IncSP_offset(irn, -ofs);
568 be_set_IncSP_pred(irn, pred_sp);
573 * Find a free GP register if possible, else return NULL.
575 static const arch_register_t *get_free_gp_reg(void)
579 for(i = 0; i < N_ia32_gp_REGS; ++i) {
580 const arch_register_t *reg = &ia32_gp_regs[i];
581 if(arch_register_type_is(reg, ignore))
584 if(be_peephole_get_value(CLASS_ia32_gp, i) == NULL)
585 return &ia32_gp_regs[i];
592 * Creates a Pop instruction before the given schedule point.
594 * @param dbgi debug info
595 * @param irg the graph
596 * @param block the block
597 * @param stack the previous stack value
598 * @param schedpoint the new node is added before this node
599 * @param reg the register to pop
601 * @return the new stack value
603 static ir_node *create_pop(dbg_info *dbgi, ir_graph *irg, ir_node *block,
604 ir_node *stack, ir_node *schedpoint,
605 const arch_register_t *reg)
607 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
613 pop = new_rd_ia32_Pop(dbgi, irg, block, new_NoMem(), stack);
615 stack = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_stack);
616 arch_set_irn_register(arch_env, stack, esp);
617 val = new_r_Proj(irg, block, pop, mode_Iu, pn_ia32_Pop_res);
618 arch_set_irn_register(arch_env, val, reg);
620 sched_add_before(schedpoint, pop);
623 keep = be_new_Keep(&ia32_reg_classes[CLASS_ia32_gp], irg, block, 1, in);
624 sched_add_before(schedpoint, keep);
630 * Creates a Push instruction before the given schedule point.
632 * @param dbgi debug info
633 * @param irg the graph
634 * @param block the block
635 * @param stack the previous stack value
636 * @param schedpoint the new node is added before this node
637 * @param reg the register to pop
639 * @return the new stack value
641 static ir_node *create_push(dbg_info *dbgi, ir_graph *irg, ir_node *block,
642 ir_node *stack, ir_node *schedpoint)
644 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
646 ir_node *val = ia32_new_Unknown_gp(cg);
647 ir_node *noreg = ia32_new_NoReg_gp(cg);
648 ir_node *nomem = get_irg_no_mem(irg);
649 ir_node *push = new_rd_ia32_Push(dbgi, irg, block, noreg, noreg, nomem, val, stack);
650 sched_add_before(schedpoint, push);
652 stack = new_r_Proj(irg, block, push, mode_Iu, pn_ia32_Push_stack);
653 arch_set_irn_register(arch_env, stack, esp);
659 * Optimize an IncSp by replacing it with Push/Pop.
661 static void peephole_be_IncSP(ir_node *node)
663 const arch_register_t *esp = &ia32_gp_regs[REG_ESP];
664 const arch_register_t *reg;
665 ir_graph *irg = current_ir_graph;
671 /* first optimize incsp->incsp combinations */
672 node = be_peephole_IncSP_IncSP(node);
674 /* transform IncSP->Store combinations to Push where possible */
675 peephole_IncSP_Store_to_push(node);
677 /* transform Load->IncSP combinations to Pop where possible */
678 peephole_Load_IncSP_to_pop(node);
680 if (arch_get_irn_register(arch_env, node) != esp)
683 /* replace IncSP -4 by Pop freereg when possible */
684 offset = be_get_IncSP_offset(node);
685 if ((offset != -8 || ia32_cg_config.use_add_esp_8) &&
686 (offset != -4 || ia32_cg_config.use_add_esp_4) &&
687 (offset != +4 || ia32_cg_config.use_sub_esp_4) &&
688 (offset != +8 || ia32_cg_config.use_sub_esp_8))
692 /* we need a free register for pop */
693 reg = get_free_gp_reg();
697 dbgi = get_irn_dbg_info(node);
698 block = get_nodes_block(node);
699 stack = be_get_IncSP_pred(node);
701 stack = create_pop(dbgi, irg, block, stack, node, reg);
704 stack = create_pop(dbgi, irg, block, stack, node, reg);
707 dbgi = get_irn_dbg_info(node);
708 block = get_nodes_block(node);
709 stack = be_get_IncSP_pred(node);
710 stack = create_push(dbgi, irg, block, stack, node);
713 stack = create_push(dbgi, irg, block, stack, node);
717 be_peephole_exchange(node, stack);
721 * Peephole optimisation for ia32_Const's
723 static void peephole_ia32_Const(ir_node *node)
725 const ia32_immediate_attr_t *attr = get_ia32_immediate_attr_const(node);
726 const arch_register_t *reg;
727 ir_graph *irg = current_ir_graph;
734 /* try to transform a mov 0, reg to xor reg reg */
735 if (attr->offset != 0 || attr->symconst != NULL)
737 if (ia32_cg_config.use_mov_0)
739 /* xor destroys the flags, so no-one must be using them */
740 if (be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
743 reg = arch_get_irn_register(arch_env, node);
744 assert(be_peephole_get_reg_value(reg) == NULL);
746 /* create xor(produceval, produceval) */
747 block = get_nodes_block(node);
748 dbgi = get_irn_dbg_info(node);
749 produceval = new_rd_ia32_ProduceVal(dbgi, irg, block);
750 arch_set_irn_register(arch_env, produceval, reg);
752 noreg = ia32_new_NoReg_gp(cg);
753 xor = new_rd_ia32_Xor(dbgi, irg, block, noreg, noreg, new_NoMem(),
754 produceval, produceval);
755 arch_set_irn_register(arch_env, xor, reg);
757 sched_add_before(node, produceval);
758 sched_add_before(node, xor);
760 be_peephole_exchange(node, xor);
763 static INLINE int is_noreg(ia32_code_gen_t *cg, const ir_node *node)
765 return node == cg->noreg_gp;
768 static ir_node *create_immediate_from_int(ia32_code_gen_t *cg, int val)
770 ir_graph *irg = current_ir_graph;
771 ir_node *start_block = get_irg_start_block(irg);
772 ir_node *immediate = new_rd_ia32_Immediate(NULL, irg, start_block, NULL,
774 arch_set_irn_register(cg->arch_env, immediate, &ia32_gp_regs[REG_GP_NOREG]);
779 static ir_node *create_immediate_from_am(ia32_code_gen_t *cg,
782 ir_graph *irg = get_irn_irg(node);
783 ir_node *block = get_nodes_block(node);
784 int offset = get_ia32_am_offs_int(node);
785 int sc_sign = is_ia32_am_sc_sign(node);
786 ir_entity *entity = get_ia32_am_sc(node);
789 res = new_rd_ia32_Immediate(NULL, irg, block, entity, sc_sign, offset);
790 arch_set_irn_register(cg->arch_env, res, &ia32_gp_regs[REG_GP_NOREG]);
794 static int is_am_one(const ir_node *node)
796 int offset = get_ia32_am_offs_int(node);
797 ir_entity *entity = get_ia32_am_sc(node);
799 return offset == 1 && entity == NULL;
802 static int is_am_minus_one(const ir_node *node)
804 int offset = get_ia32_am_offs_int(node);
805 ir_entity *entity = get_ia32_am_sc(node);
807 return offset == -1 && entity == NULL;
811 * Transforms a LEA into an Add or SHL if possible.
813 static void peephole_ia32_Lea(ir_node *node)
815 const arch_env_t *arch_env = cg->arch_env;
816 ir_graph *irg = current_ir_graph;
819 const arch_register_t *base_reg;
820 const arch_register_t *index_reg;
821 const arch_register_t *out_reg;
832 assert(is_ia32_Lea(node));
834 /* we can only do this if are allowed to globber the flags */
835 if(be_peephole_get_value(CLASS_ia32_flags, REG_EFLAGS) != NULL)
838 base = get_irn_n(node, n_ia32_Lea_base);
839 index = get_irn_n(node, n_ia32_Lea_index);
841 if(is_noreg(cg, base)) {
845 base_reg = arch_get_irn_register(arch_env, base);
847 if(is_noreg(cg, index)) {
851 index_reg = arch_get_irn_register(arch_env, index);
854 if(base == NULL && index == NULL) {
855 /* we shouldn't construct these in the first place... */
857 ir_fprintf(stderr, "Optimisation warning: found immediate only lea\n");
862 out_reg = arch_get_irn_register(arch_env, node);
863 scale = get_ia32_am_scale(node);
864 assert(!is_ia32_need_stackent(node) || get_ia32_frame_ent(node) != NULL);
865 /* check if we have immediates values (frame entities should already be
866 * expressed in the offsets) */
867 if(get_ia32_am_offs_int(node) != 0 || get_ia32_am_sc(node) != NULL) {
873 /* we can transform leas where the out register is the same as either the
874 * base or index register back to an Add or Shl */
875 if(out_reg == base_reg) {
878 if(!has_immediates) {
879 ir_fprintf(stderr, "Optimisation warning: found lea which is "
884 goto make_add_immediate;
886 if(scale == 0 && !has_immediates) {
891 /* can't create an add */
893 } else if(out_reg == index_reg) {
895 if(has_immediates && scale == 0) {
897 goto make_add_immediate;
898 } else if(!has_immediates && scale > 0) {
900 op2 = create_immediate_from_int(cg, scale);
902 } else if(!has_immediates) {
904 ir_fprintf(stderr, "Optimisation warning: found lea which is "
908 } else if(scale == 0 && !has_immediates) {
913 /* can't create an add */
916 /* can't create an add */
921 if(ia32_cg_config.use_incdec) {
922 if(is_am_one(node)) {
923 dbgi = get_irn_dbg_info(node);
924 block = get_nodes_block(node);
925 res = new_rd_ia32_Inc(dbgi, irg, block, op1);
926 arch_set_irn_register(arch_env, res, out_reg);
929 if(is_am_minus_one(node)) {
930 dbgi = get_irn_dbg_info(node);
931 block = get_nodes_block(node);
932 res = new_rd_ia32_Dec(dbgi, irg, block, op1);
933 arch_set_irn_register(arch_env, res, out_reg);
937 op2 = create_immediate_from_am(cg, node);
940 dbgi = get_irn_dbg_info(node);
941 block = get_nodes_block(node);
942 noreg = ia32_new_NoReg_gp(cg);
944 res = new_rd_ia32_Add(dbgi, irg, block, noreg, noreg, nomem, op1, op2);
945 arch_set_irn_register(arch_env, res, out_reg);
946 set_ia32_commutative(res);
950 dbgi = get_irn_dbg_info(node);
951 block = get_nodes_block(node);
952 noreg = ia32_new_NoReg_gp(cg);
954 res = new_rd_ia32_Shl(dbgi, irg, block, op1, op2);
955 arch_set_irn_register(arch_env, res, out_reg);
959 SET_IA32_ORIG_NODE(res, ia32_get_old_node_name(cg, node));
961 /* add new ADD/SHL to schedule */
962 DBG_OPT_LEA2ADD(node, res);
964 /* exchange the Add and the LEA */
965 sched_add_before(node, res);
966 be_peephole_exchange(node, res);
970 * Split a Imul mem, imm into a Load mem and Imul reg, imm if possible.
972 static void peephole_ia32_Imul_split(ir_node *imul) {
973 const ir_node *right = get_irn_n(imul, n_ia32_IMul_right);
974 const arch_register_t *reg;
975 ir_node *load, *block, *base, *index, *mem, *res, *noreg;
979 if (! is_ia32_Immediate(right) || get_ia32_op_type(imul) != ia32_AddrModeS) {
980 /* no memory, imm form ignore */
983 /* we need a free register */
984 reg = get_free_gp_reg();
988 /* fine, we can rebuild it */
989 dbgi = get_irn_dbg_info(imul);
990 block = get_nodes_block(imul);
991 irg = current_ir_graph;
992 base = get_irn_n(imul, n_ia32_IMul_base);
993 index = get_irn_n(imul, n_ia32_IMul_index);
994 mem = get_irn_n(imul, n_ia32_IMul_mem);
995 load = new_rd_ia32_Load(dbgi, irg, block, base, index, mem);
997 /* copy all attributes */
998 set_irn_pinned(load, get_irn_pinned(imul));
999 set_ia32_op_type(load, ia32_AddrModeS);
1000 set_ia32_ls_mode(load, get_ia32_ls_mode(imul));
1002 set_ia32_am_scale(load, get_ia32_am_scale(imul));
1003 set_ia32_am_sc(load, get_ia32_am_sc(imul));
1004 set_ia32_am_offs_int(load, get_ia32_am_offs_int(imul));
1005 if (is_ia32_am_sc_sign(imul))
1006 set_ia32_am_sc_sign(load);
1007 if (is_ia32_use_frame(imul))
1008 set_ia32_use_frame(load);
1009 set_ia32_frame_ent(load, get_ia32_frame_ent(imul));
1011 sched_add_before(imul, load);
1013 mem = new_rd_Proj(dbgi, irg, block, load, mode_M, pn_ia32_Load_M);
1014 res = new_rd_Proj(dbgi, irg, block, load, mode_Iu, pn_ia32_Load_res);
1016 arch_set_irn_register(arch_env, res, reg);
1017 be_peephole_new_node(res);
1019 set_irn_n(imul, n_ia32_IMul_mem, mem);
1020 noreg = get_irn_n(imul, n_ia32_IMul_left);
1021 set_irn_n(imul, n_ia32_IMul_left, res);
1022 set_ia32_op_type(imul, ia32_Normal);
1026 * Replace xorps r,r and xorpd r,r by pxor r,r
1028 static void peephole_ia32_xZero(ir_node *xor) {
1029 set_irn_op(xor, op_ia32_xPzero);
1033 * Register a peephole optimisation function.
1035 static void register_peephole_optimisation(ir_op *op, peephole_opt_func func) {
1036 assert(op->ops.generic == NULL);
1037 op->ops.generic = (op_func)func;
1040 /* Perform peephole-optimizations. */
1041 void ia32_peephole_optimization(ia32_code_gen_t *new_cg)
1044 arch_env = cg->arch_env;
1046 /* register peephole optimisations */
1047 clear_irp_opcodes_generic_func();
1048 register_peephole_optimisation(op_ia32_Const, peephole_ia32_Const);
1049 register_peephole_optimisation(op_be_IncSP, peephole_be_IncSP);
1050 register_peephole_optimisation(op_ia32_Lea, peephole_ia32_Lea);
1051 register_peephole_optimisation(op_ia32_Test, peephole_ia32_Test);
1052 register_peephole_optimisation(op_ia32_Test8Bit, peephole_ia32_Test);
1053 register_peephole_optimisation(op_be_Return, peephole_ia32_Return);
1054 if (! ia32_cg_config.use_imul_mem_imm32)
1055 register_peephole_optimisation(op_ia32_IMul, peephole_ia32_Imul_split);
1056 if (ia32_cg_config.use_pxor)
1057 register_peephole_optimisation(op_ia32_xZero, peephole_ia32_xZero);
1059 be_peephole_opt(cg->birg);
1063 * Removes node from schedule if it is not used anymore. If irn is a mode_T node
1064 * all it's Projs are removed as well.
1065 * @param irn The irn to be removed from schedule
1067 static INLINE void try_kill(ir_node *node)
1069 if(get_irn_mode(node) == mode_T) {
1070 const ir_edge_t *edge, *next;
1071 foreach_out_edge_safe(node, edge, next) {
1072 ir_node *proj = get_edge_src_irn(edge);
1077 if(get_irn_n_edges(node) != 0)
1080 if (sched_is_scheduled(node)) {
1087 static void optimize_conv_store(ir_node *node)
1092 ir_mode *store_mode;
1094 if(!is_ia32_Store(node) && !is_ia32_Store8Bit(node))
1097 assert(n_ia32_Store_val == n_ia32_Store8Bit_val);
1098 pred_proj = get_irn_n(node, n_ia32_Store_val);
1099 if(is_Proj(pred_proj)) {
1100 pred = get_Proj_pred(pred_proj);
1104 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1106 if(get_ia32_op_type(pred) != ia32_Normal)
1109 /* the store only stores the lower bits, so we only need the conv
1110 * it it shrinks the mode */
1111 conv_mode = get_ia32_ls_mode(pred);
1112 store_mode = get_ia32_ls_mode(node);
1113 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(store_mode))
1116 set_irn_n(node, n_ia32_Store_val, get_irn_n(pred, n_ia32_Conv_I2I_val));
1117 if(get_irn_n_edges(pred_proj) == 0) {
1118 kill_node(pred_proj);
1119 if(pred != pred_proj)
1124 static void optimize_load_conv(ir_node *node)
1126 ir_node *pred, *predpred;
1130 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1133 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1134 pred = get_irn_n(node, n_ia32_Conv_I2I_val);
1138 predpred = get_Proj_pred(pred);
1139 if(!is_ia32_Load(predpred))
1142 /* the load is sign extending the upper bits, so we only need the conv
1143 * if it shrinks the mode */
1144 load_mode = get_ia32_ls_mode(predpred);
1145 conv_mode = get_ia32_ls_mode(node);
1146 if(get_mode_size_bits(conv_mode) < get_mode_size_bits(load_mode))
1149 if(get_mode_sign(conv_mode) != get_mode_sign(load_mode)) {
1150 /* change the load if it has only 1 user */
1151 if(get_irn_n_edges(pred) == 1) {
1153 if(get_mode_sign(conv_mode)) {
1154 newmode = find_signed_mode(load_mode);
1156 newmode = find_unsigned_mode(load_mode);
1158 assert(newmode != NULL);
1159 set_ia32_ls_mode(predpred, newmode);
1161 /* otherwise we have to keep the conv */
1167 exchange(node, pred);
1170 static void optimize_conv_conv(ir_node *node)
1172 ir_node *pred_proj, *pred, *result_conv;
1173 ir_mode *pred_mode, *conv_mode;
1177 if (!is_ia32_Conv_I2I(node) && !is_ia32_Conv_I2I8Bit(node))
1180 assert(n_ia32_Conv_I2I_val == n_ia32_Conv_I2I8Bit_val);
1181 pred_proj = get_irn_n(node, n_ia32_Conv_I2I_val);
1182 if(is_Proj(pred_proj))
1183 pred = get_Proj_pred(pred_proj);
1187 if(!is_ia32_Conv_I2I(pred) && !is_ia32_Conv_I2I8Bit(pred))
1190 /* we know that after a conv, the upper bits are sign extended
1191 * so we only need the 2nd conv if it shrinks the mode */
1192 conv_mode = get_ia32_ls_mode(node);
1193 conv_mode_bits = get_mode_size_bits(conv_mode);
1194 pred_mode = get_ia32_ls_mode(pred);
1195 pred_mode_bits = get_mode_size_bits(pred_mode);
1197 if(conv_mode_bits == pred_mode_bits
1198 && get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1199 result_conv = pred_proj;
1200 } else if(conv_mode_bits <= pred_mode_bits) {
1201 /* if 2nd conv is smaller then first conv, then we can always take the
1203 if(get_irn_n_edges(pred_proj) == 1) {
1204 result_conv = pred_proj;
1205 set_ia32_ls_mode(pred, conv_mode);
1207 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1208 if (get_mode_size_bits(conv_mode) == 8) {
1209 set_irn_op(pred, op_ia32_Conv_I2I8Bit);
1210 set_ia32_in_req_all(pred, get_ia32_in_req_all(node));
1213 /* we don't want to end up with 2 loads, so we better do nothing */
1214 if(get_irn_mode(pred) == mode_T) {
1218 result_conv = exact_copy(pred);
1219 set_ia32_ls_mode(result_conv, conv_mode);
1221 /* Argh:We must change the opcode to 8bit AND copy the register constraints */
1222 if (get_mode_size_bits(conv_mode) == 8) {
1223 set_irn_op(result_conv, op_ia32_Conv_I2I8Bit);
1224 set_ia32_in_req_all(result_conv, get_ia32_in_req_all(node));
1228 /* if both convs have the same sign, then we can take the smaller one */
1229 if(get_mode_sign(conv_mode) == get_mode_sign(pred_mode)) {
1230 result_conv = pred_proj;
1232 /* no optimisation possible if smaller conv is sign-extend */
1233 if(mode_is_signed(pred_mode)) {
1236 /* we can take the smaller conv if it is unsigned */
1237 result_conv = pred_proj;
1242 exchange(node, result_conv);
1244 if(get_irn_n_edges(pred_proj) == 0) {
1245 kill_node(pred_proj);
1246 if(pred != pred_proj)
1249 optimize_conv_conv(result_conv);
1252 static void optimize_node(ir_node *node, void *env)
1256 optimize_load_conv(node);
1257 optimize_conv_store(node);
1258 optimize_conv_conv(node);
1262 * Performs conv and address mode optimization.
1264 void ia32_optimize_graph(ia32_code_gen_t *cg)
1266 irg_walk_blkwise_graph(cg->irg, NULL, optimize_node, cg);
1269 be_dump(cg->irg, "-opt", dump_ir_block_graph_sched);
1272 void ia32_init_optimize(void)
1274 FIRM_DBG_REGISTER(dbg, "firm.be.ia32.optimize");