2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Handling of ia32 specific firm opcodes.
23 * @author Christian Wuerdig
26 * This file implements the creation of the achitecture specific firm opcodes
27 * and the corresponding node constructors for the ia32 assembler irg.
36 #include "irgraph_t.h"
42 #include "firm_common_t.h"
47 #include "raw_bitset.h"
50 #include "../bearch_t.h"
52 #include "bearch_ia32_t.h"
53 #include "ia32_nodes_attr.h"
54 #include "ia32_new_nodes.h"
55 #include "gen_ia32_regalloc_if.h"
56 #include "gen_ia32_machine.h"
58 /***********************************************************************************
61 * __| |_ _ _ __ ___ _ __ ___ _ __ _ _ __ | |_ ___ _ __| |_ __ _ ___ ___
62 * / _` | | | | '_ ` _ \| '_ \ / _ \ '__| | | '_ \| __/ _ \ '__| _/ _` |/ __/ _ \
63 * | (_| | |_| | | | | | | |_) | __/ | | | | | | || __/ | | || (_| | (_| __/
64 * \__,_|\__,_|_| |_| |_| .__/ \___|_| |_|_| |_|\__\___|_| |_| \__,_|\___\___|
67 ***********************************************************************************/
70 * Dumps the register requirements for either in or out.
72 static void dump_reg_req(FILE *F, ir_node *n, const arch_register_req_t **reqs,
74 char *dir = inout ? "out" : "in";
75 int max = inout ? get_ia32_n_res(n) : get_irn_arity(n);
79 memset(buf, 0, sizeof(buf));
82 for (i = 0; i < max; i++) {
83 fprintf(F, "%sreq #%d =", dir, i);
85 if (reqs[i]->type == arch_register_req_type_none) {
89 if (reqs[i]->type & arch_register_req_type_normal) {
90 fprintf(F, " %s", reqs[i]->cls->name);
93 if (reqs[i]->type & arch_register_req_type_limited) {
95 arch_register_req_format(buf, sizeof(buf), reqs[i], n));
98 if (reqs[i]->type & arch_register_req_type_should_be_same) {
99 ir_fprintf(F, " same as %+F", get_irn_n(n, reqs[i]->other_same[0]));
100 if (reqs[i]->other_same[1] != -1)
101 ir_fprintf(F, " or %+F", get_irn_n(n, reqs[i]->other_same[1]));
104 if (reqs[i]->type & arch_register_req_type_should_be_different) {
105 ir_fprintf(F, " different from %+F", get_irn_n(n, reqs[i]->other_different));
114 fprintf(F, "%sreq = N/A\n", dir);
119 * Dumper interface for dumping ia32 nodes in vcg.
120 * @param n the node to dump
121 * @param F the output file
122 * @param reason indicates which kind of information should be dumped
123 * @return 0 on success or != 0 on failure
125 static int ia32_dump_node(ir_node *n, FILE *F, dump_reason_t reason) {
126 ir_mode *mode = NULL;
129 const arch_register_req_t **reqs;
130 const arch_register_t **slots;
133 case dump_node_opcode_txt:
134 fprintf(F, "%s", get_irn_opname(n));
136 if(is_ia32_Immediate(n) || is_ia32_Const(n)) {
137 const ia32_immediate_attr_t *attr
138 = get_ia32_immediate_attr_const(n);
145 fputs(get_entity_name(attr->symconst), F);
147 if(attr->offset != 0 || attr->symconst == NULL) {
148 if(attr->offset > 0 && attr->symconst != NULL) {
151 fprintf(F, "%ld", attr->offset);
155 const ia32_attr_t *attr = get_ia32_attr_const(n);
157 if(attr->am_sc != NULL || attr->am_offs != 0)
160 if(attr->am_sc != NULL) {
161 if(attr->data.am_sc_sign) {
164 fputs(get_entity_name(attr->am_sc), F);
166 if(attr->am_offs != 0) {
167 if(attr->am_offs > 0 && attr->am_sc != NULL) {
170 fprintf(F, "%d", attr->am_offs);
173 if(attr->am_sc != NULL || attr->am_offs != 0)
178 case dump_node_mode_txt:
179 if (is_ia32_Ld(n) || is_ia32_St(n)) {
180 mode = get_ia32_ls_mode(n);
181 fprintf(F, "[%s]", mode ? get_mode_name(mode) : "?NOMODE?");
185 case dump_node_nodeattr_txt:
186 if (! is_ia32_Lea(n)) {
187 if (is_ia32_AddrModeS(n)) {
188 fprintf(F, "[AM S] ");
189 } else if (is_ia32_AddrModeD(n)) {
190 fprintf(F, "[AM D] ");
196 case dump_node_info_txt:
197 n_res = get_ia32_n_res(n);
198 fprintf(F, "=== IA32 attr begin ===\n");
200 /* dump IN requirements */
201 if (get_irn_arity(n) > 0) {
202 reqs = get_ia32_in_req_all(n);
203 dump_reg_req(F, n, reqs, 0);
206 /* dump OUT requirements */
208 reqs = get_ia32_out_req_all(n);
209 dump_reg_req(F, n, reqs, 1);
212 /* dump assigned registers */
213 slots = get_ia32_slots(n);
214 if (slots && n_res > 0) {
215 for (i = 0; i < n_res; i++) {
216 const arch_register_t *reg;
220 fprintf(F, "reg #%d = %s\n", i, reg ? arch_register_get_name(reg) : "n/a");
227 switch (get_ia32_op_type(n)) {
229 fprintf(F, "Normal");
232 fprintf(F, "AM Dest (Load+Store)");
235 fprintf(F, "AM Source (Load)");
238 fprintf(F, "unknown (%d)", get_ia32_op_type(n));
243 /* dump supported am */
244 fprintf(F, "AM support = ");
245 switch (get_ia32_am_support(n)) {
250 fprintf(F, "source only (Load)");
253 fprintf(F, "dest only (Load+Store)");
259 fprintf(F, "unknown (%d)", get_ia32_am_support(n));
265 if(get_ia32_am_offs_int(n) != 0) {
266 fprintf(F, "AM offset = %d\n", get_ia32_am_offs_int(n));
269 /* dump AM symconst */
270 if(get_ia32_am_sc(n) != NULL) {
271 ir_entity *ent = get_ia32_am_sc(n);
272 ident *id = get_entity_ld_ident(ent);
273 fprintf(F, "AM symconst = %s\n", get_id_str(id));
277 fprintf(F, "AM scale = %d\n", get_ia32_am_scale(n));
280 if (is_ia32_SwitchJmp(n)) {
281 fprintf(F, "pn_code = %ld\n", get_ia32_condcode(n));
282 } else if (is_ia32_CMov(n) || is_ia32_Set(n) || is_ia32_Jcc(n)) {
283 long pnc = get_ia32_condcode(n);
284 fprintf(F, "pn_code = %ld (%s)\n", pnc, get_pnc_string(pnc));
286 else if (is_ia32_CopyB(n) || is_ia32_CopyB_i(n)) {
287 fprintf(F, "size = %u\n", get_ia32_copyb_size(n));
291 fprintf(F, "n_res = %d\n", get_ia32_n_res(n));
294 fprintf(F, "use_frame = %d\n", is_ia32_use_frame(n));
297 fprintf(F, "commutative = %d\n", is_ia32_commutative(n));
300 fprintf(F, "need stackent = %d\n", is_ia32_need_stackent(n));
303 fprintf(F, "latency = %d\n", get_ia32_latency(n));
306 fprintf(F, "flags =");
307 flags = get_ia32_flags(n);
308 if (flags == arch_irn_flags_none) {
312 if (flags & arch_irn_flags_dont_spill) {
313 fprintf(F, " unspillable");
315 if (flags & arch_irn_flags_rematerializable) {
316 fprintf(F, " remat");
318 if (flags & arch_irn_flags_ignore) {
319 fprintf(F, " ignore");
321 if (flags & arch_irn_flags_modify_sp) {
322 fprintf(F, " modify_sp");
325 fprintf(F, " (%d)\n", flags);
327 /* dump frame entity */
328 fprintf(F, "frame entity = ");
329 if (get_ia32_frame_ent(n)) {
330 ir_fprintf(F, "%+F", get_ia32_frame_ent(n));
338 fprintf(F, "ls_mode = ");
339 if (get_ia32_ls_mode(n)) {
340 ir_fprintf(F, "%+F", get_ia32_ls_mode(n));
348 /* dump original ir node name */
349 fprintf(F, "orig node = ");
350 if (get_ia32_orig_node(n)) {
351 fprintf(F, "%s", get_ia32_orig_node(n));
359 fprintf(F, "=== IA32 attr end ===\n");
360 /* end of: case dump_node_info_txt */
369 /***************************************************************************************************
371 * | | | | | | / / | | | | | | | |
372 * __ _| |_| |_ _ __ ___ ___| |_ / /_ _ ___| |_ _ __ ___ ___| |_| |__ ___ __| |___
373 * / _` | __| __| '__| / __|/ _ \ __| / / _` |/ _ \ __| | '_ ` _ \ / _ \ __| '_ \ / _ \ / _` / __|
374 * | (_| | |_| |_| | \__ \ __/ |_ / / (_| | __/ |_ | | | | | | __/ |_| | | | (_) | (_| \__ \
375 * \__,_|\__|\__|_| |___/\___|\__/_/ \__, |\___|\__| |_| |_| |_|\___|\__|_| |_|\___/ \__,_|___/
378 ***************************************************************************************************/
380 ia32_attr_t *get_ia32_attr(ir_node *node) {
381 assert(is_ia32_irn(node) && "need ia32 node to get ia32 attributes");
382 return (ia32_attr_t *)get_irn_generic_attr(node);
385 const ia32_attr_t *get_ia32_attr_const(const ir_node *node) {
386 assert(is_ia32_irn(node) && "need ia32 node to get ia32 attributes");
387 return (const ia32_attr_t*) get_irn_generic_attr_const(node);
390 ia32_x87_attr_t *get_ia32_x87_attr(ir_node *node) {
391 ia32_attr_t *attr = get_ia32_attr(node);
392 ia32_x87_attr_t *x87_attr = CAST_IA32_ATTR(ia32_x87_attr_t, attr);
396 const ia32_x87_attr_t *get_ia32_x87_attr_const(const ir_node *node) {
397 const ia32_attr_t *attr = get_ia32_attr_const(node);
398 const ia32_x87_attr_t *x87_attr = CONST_CAST_IA32_ATTR(ia32_x87_attr_t, attr);
402 const ia32_asm_attr_t *get_ia32_asm_attr_const(const ir_node *node) {
403 const ia32_attr_t *attr = get_ia32_attr_const(node);
404 const ia32_asm_attr_t *asm_attr = CONST_CAST_IA32_ATTR(ia32_asm_attr_t, attr);
409 const ia32_immediate_attr_t *get_ia32_immediate_attr_const(const ir_node *node)
411 const ia32_attr_t *attr = get_ia32_attr_const(node);
412 const ia32_immediate_attr_t *imm_attr = CONST_CAST_IA32_ATTR(ia32_immediate_attr_t, attr);
414 assert(is_ia32_Immediate(node) || is_ia32_Const(node));
418 ia32_condcode_attr_t *get_ia32_condcode_attr(ir_node *node) {
419 ia32_attr_t *attr = get_ia32_attr(node);
420 ia32_condcode_attr_t *cc_attr = CAST_IA32_ATTR(ia32_condcode_attr_t, attr);
422 assert(is_ia32_SwitchJmp(node) || is_ia32_CMov(node) || is_ia32_Set(node) || is_ia32_Jcc(node));
426 const ia32_condcode_attr_t *get_ia32_condcode_attr_const(const ir_node *node) {
427 const ia32_attr_t *attr = get_ia32_attr_const(node);
428 const ia32_condcode_attr_t *cc_attr = CONST_CAST_IA32_ATTR(ia32_condcode_attr_t, attr);
430 assert(is_ia32_SwitchJmp(node) || is_ia32_CMov(node) || is_ia32_Set(node) || is_ia32_Jcc(node));
434 ia32_copyb_attr_t *get_ia32_copyb_attr(ir_node *node) {
435 ia32_attr_t *attr = get_ia32_attr(node);
436 ia32_copyb_attr_t *copyb_attr = CAST_IA32_ATTR(ia32_copyb_attr_t, attr);
438 assert(is_ia32_CopyB(node) || is_ia32_CopyB_i(node));
442 const ia32_copyb_attr_t *get_ia32_copyb_attr_const(const ir_node *node) {
443 const ia32_attr_t *attr = get_ia32_attr_const(node);
444 const ia32_copyb_attr_t *copyb_attr = CONST_CAST_IA32_ATTR(ia32_copyb_attr_t, attr);
446 assert(is_ia32_CopyB(node) || is_ia32_CopyB_i(node));
451 * Gets the type of an ia32 node.
453 ia32_op_type_t get_ia32_op_type(const ir_node *node) {
454 const ia32_attr_t *attr = get_ia32_attr_const(node);
455 return attr->data.tp;
459 * Sets the type of an ia32 node.
461 void set_ia32_op_type(ir_node *node, ia32_op_type_t tp) {
462 ia32_attr_t *attr = get_ia32_attr(node);
467 * Gets the supported address mode of an ia32 node
469 ia32_am_type_t get_ia32_am_support(const ir_node *node) {
470 const ia32_attr_t *attr = get_ia32_attr_const(node);
471 return attr->data.am_support;
474 ia32_am_arity_t get_ia32_am_arity(const ir_node *node) {
475 const ia32_attr_t *attr = get_ia32_attr_const(node);
476 return attr->data.am_arity;
480 * Sets the supported address mode of an ia32 node
482 void set_ia32_am_support(ir_node *node, ia32_am_type_t am_tp,
483 ia32_am_arity_t arity) {
484 ia32_attr_t *attr = get_ia32_attr(node);
485 attr->data.am_support = am_tp;
486 attr->data.am_arity = arity;
488 assert((am_tp == ia32_am_None && arity == ia32_am_arity_none) ||
489 (am_tp != ia32_am_None &&
490 ((arity == ia32_am_unary) || (arity == ia32_am_binary) || (arity == ia32_am_ternary))));
494 * Gets the address mode offset as int.
496 int get_ia32_am_offs_int(const ir_node *node) {
497 const ia32_attr_t *attr = get_ia32_attr_const(node);
498 return attr->am_offs;
502 * Sets the address mode offset from an int.
504 void set_ia32_am_offs_int(ir_node *node, int offset) {
505 ia32_attr_t *attr = get_ia32_attr(node);
506 attr->am_offs = offset;
509 void add_ia32_am_offs_int(ir_node *node, int offset) {
510 ia32_attr_t *attr = get_ia32_attr(node);
511 attr->am_offs += offset;
515 * Returns the symconst entity associated to address mode.
517 ir_entity *get_ia32_am_sc(const ir_node *node) {
518 const ia32_attr_t *attr = get_ia32_attr_const(node);
523 * Sets the symconst entity associated to address mode.
525 void set_ia32_am_sc(ir_node *node, ir_entity *entity) {
526 ia32_attr_t *attr = get_ia32_attr(node);
527 attr->am_sc = entity;
531 * Sets the sign bit for address mode symconst.
533 void set_ia32_am_sc_sign(ir_node *node) {
534 ia32_attr_t *attr = get_ia32_attr(node);
535 attr->data.am_sc_sign = 1;
539 * Clears the sign bit for address mode symconst.
541 void clear_ia32_am_sc_sign(ir_node *node) {
542 ia32_attr_t *attr = get_ia32_attr(node);
543 attr->data.am_sc_sign = 0;
547 * Returns the sign bit for address mode symconst.
549 int is_ia32_am_sc_sign(const ir_node *node) {
550 const ia32_attr_t *attr = get_ia32_attr_const(node);
551 return attr->data.am_sc_sign;
555 * Gets the addr mode const.
557 int get_ia32_am_scale(const ir_node *node) {
558 const ia32_attr_t *attr = get_ia32_attr_const(node);
559 return attr->data.am_scale;
563 * Sets the index register scale for address mode.
565 void set_ia32_am_scale(ir_node *node, int scale) {
566 ia32_attr_t *attr = get_ia32_attr(node);
567 attr->data.am_scale = scale;
570 void ia32_copy_am_attrs(ir_node *to, const ir_node *from)
572 set_ia32_ls_mode(to, get_ia32_ls_mode(from));
573 set_ia32_am_scale(to, get_ia32_am_scale(from));
574 set_ia32_am_sc(to, get_ia32_am_sc(from));
575 if(is_ia32_am_sc_sign(from))
576 set_ia32_am_sc_sign(to);
577 add_ia32_am_offs_int(to, get_ia32_am_offs_int(from));
578 set_ia32_frame_ent(to, get_ia32_frame_ent(from));
579 if (is_ia32_use_frame(from))
580 set_ia32_use_frame(to);
584 * Sets the uses_frame flag.
586 void set_ia32_use_frame(ir_node *node) {
587 ia32_attr_t *attr = get_ia32_attr(node);
588 attr->data.use_frame = 1;
592 * Clears the uses_frame flag.
594 void clear_ia32_use_frame(ir_node *node) {
595 ia32_attr_t *attr = get_ia32_attr(node);
596 attr->data.use_frame = 0;
600 * Gets the uses_frame flag.
602 int is_ia32_use_frame(const ir_node *node) {
603 const ia32_attr_t *attr = get_ia32_attr_const(node);
604 return attr->data.use_frame;
608 * Sets node to commutative.
610 void set_ia32_commutative(ir_node *node) {
611 ia32_attr_t *attr = get_ia32_attr(node);
612 attr->data.is_commutative = 1;
616 * Sets node to non-commutative.
618 void clear_ia32_commutative(ir_node *node) {
619 ia32_attr_t *attr = get_ia32_attr(node);
620 attr->data.is_commutative = 0;
624 * Checks if node is commutative.
626 int is_ia32_commutative(const ir_node *node) {
627 const ia32_attr_t *attr = get_ia32_attr_const(node);
628 return attr->data.is_commutative;
631 void set_ia32_need_stackent(ir_node *node) {
632 ia32_attr_t *attr = get_ia32_attr(node);
633 attr->data.need_stackent = 1;
636 void clear_ia32_need_stackent(ir_node *node) {
637 ia32_attr_t *attr = get_ia32_attr(node);
638 attr->data.need_stackent = 0;
641 int is_ia32_need_stackent(const ir_node *node) {
642 const ia32_attr_t *attr = get_ia32_attr_const(node);
643 return attr->data.need_stackent;
647 * Gets the mode of the stored/loaded value (only set for Store/Load)
649 ir_mode *get_ia32_ls_mode(const ir_node *node) {
650 const ia32_attr_t *attr = get_ia32_attr_const(node);
651 return attr->ls_mode;
655 * Sets the mode of the stored/loaded value (only set for Store/Load)
657 void set_ia32_ls_mode(ir_node *node, ir_mode *mode) {
658 ia32_attr_t *attr = get_ia32_attr(node);
659 attr->ls_mode = mode;
663 * Gets the frame entity assigned to this node.
665 ir_entity *get_ia32_frame_ent(const ir_node *node) {
666 const ia32_attr_t *attr = get_ia32_attr_const(node);
667 return attr->frame_ent;
671 * Sets the frame entity for this node.
673 void set_ia32_frame_ent(ir_node *node, ir_entity *ent) {
674 ia32_attr_t *attr = get_ia32_attr(node);
675 attr->frame_ent = ent;
677 set_ia32_use_frame(node);
679 clear_ia32_use_frame(node);
684 * Gets the instruction latency.
686 unsigned get_ia32_latency(const ir_node *node) {
687 const ia32_attr_t *attr = get_ia32_attr_const(node);
688 return attr->latency;
692 * Sets the instruction latency.
694 void set_ia32_latency(ir_node *node, unsigned latency) {
695 ia32_attr_t *attr = get_ia32_attr(node);
696 attr->latency = latency;
700 * Returns the argument register requirements of an ia32 node.
702 const arch_register_req_t **get_ia32_in_req_all(const ir_node *node) {
703 const ia32_attr_t *attr = get_ia32_attr_const(node);
708 * Sets the argument register requirements of an ia32 node.
710 void set_ia32_in_req_all(ir_node *node, const arch_register_req_t **reqs) {
711 ia32_attr_t *attr = get_ia32_attr(node);
716 * Returns the result register requirements of an ia32 node.
718 const arch_register_req_t **get_ia32_out_req_all(const ir_node *node) {
719 const ia32_attr_t *attr = get_ia32_attr_const(node);
720 return attr->out_req;
724 * Sets the result register requirements of an ia32 node.
726 void set_ia32_out_req_all(ir_node *node, const arch_register_req_t **reqs) {
727 ia32_attr_t *attr = get_ia32_attr(node);
728 attr->out_req = reqs;
732 * Returns the argument register requirement at position pos of an ia32 node.
734 const arch_register_req_t *get_ia32_in_req(const ir_node *node, int pos) {
735 const ia32_attr_t *attr = get_ia32_attr_const(node);
736 if(attr->in_req == NULL)
737 return arch_no_register_req;
739 return attr->in_req[pos];
743 * Returns the result register requirement at position pos of an ia32 node.
745 const arch_register_req_t *get_ia32_out_req(const ir_node *node, int pos) {
746 const ia32_attr_t *attr = get_ia32_attr_const(node);
747 if(attr->out_req == NULL)
748 return arch_no_register_req;
750 return attr->out_req[pos];
754 * Sets the OUT register requirements at position pos.
756 void set_ia32_req_out(ir_node *node, const arch_register_req_t *req, int pos) {
757 ia32_attr_t *attr = get_ia32_attr(node);
758 attr->out_req[pos] = req;
762 * Sets the IN register requirements at position pos.
764 void set_ia32_req_in(ir_node *node, const arch_register_req_t *req, int pos) {
765 ia32_attr_t *attr = get_ia32_attr(node);
766 attr->in_req[pos] = req;
770 * Returns the register flag of an ia32 node.
772 arch_irn_flags_t get_ia32_flags(const ir_node *node) {
773 const ia32_attr_t *attr = get_ia32_attr_const(node);
774 return attr->data.flags;
778 * Sets the register flag of an ia32 node.
780 void set_ia32_flags(ir_node *node, arch_irn_flags_t flags) {
781 ia32_attr_t *attr = get_ia32_attr(node);
782 attr->data.flags = flags;
786 * Returns the result register slots of an ia32 node.
788 const arch_register_t **get_ia32_slots(const ir_node *node) {
789 const ia32_attr_t *attr = get_ia32_attr_const(node);
794 * Returns the number of results.
796 int get_ia32_n_res(const ir_node *node) {
797 const ia32_attr_t *attr = get_ia32_attr_const(node);
798 return ARR_LEN(attr->slots);
802 * Returns the condition code of a node.
804 long get_ia32_condcode(const ir_node *node)
806 const ia32_condcode_attr_t *attr = get_ia32_condcode_attr_const(node);
807 return attr->pn_code;
811 * Sets the condition code of a node
813 void set_ia32_condcode(ir_node *node, long code)
815 ia32_condcode_attr_t *attr = get_ia32_condcode_attr(node);
816 attr->pn_code = code;
820 * Returns the condition code of a node.
822 unsigned get_ia32_copyb_size(const ir_node *node)
824 const ia32_copyb_attr_t *attr = get_ia32_copyb_attr_const(node);
829 * Sets the flags for the n'th out.
831 void set_ia32_out_flags(ir_node *node, arch_irn_flags_t flags, int pos) {
832 ia32_attr_t *attr = get_ia32_attr(node);
833 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
834 attr->out_flags[pos] = flags;
838 * Gets the flags for the n'th out.
840 arch_irn_flags_t get_ia32_out_flags(const ir_node *node, int pos) {
841 const ia32_attr_t *attr = get_ia32_attr_const(node);
842 assert(pos < ARR_LEN(attr->out_flags) && "Invalid OUT position.");
843 return attr->out_flags[pos];
847 * Get the list of available execution units.
849 const be_execution_unit_t ***get_ia32_exec_units(const ir_node *node) {
850 const ia32_attr_t *attr = get_ia32_attr_const(node);
851 return attr->exec_units;
855 * Get the exception label attribute.
857 unsigned get_ia32_exc_label(const ir_node *node) {
858 const ia32_attr_t *attr = get_ia32_attr_const(node);
859 return attr->data.except_label;
863 * Set the exception label attribute.
865 void set_ia32_exc_label(ir_node *node, unsigned flag) {
866 ia32_attr_t *attr = get_ia32_attr(node);
867 attr->data.except_label = flag;
873 * Returns the name of the original ir node.
875 const char *get_ia32_orig_node(const ir_node *node) {
876 const ia32_attr_t *attr = get_ia32_attr_const(node);
877 return attr->orig_node;
881 * Sets the name of the original ir node.
883 void set_ia32_orig_node(ir_node *node, const char *name) {
884 ia32_attr_t *attr = get_ia32_attr(node);
885 attr->orig_node = name;
890 /******************************************************************************************************
892 * (_) | | | | | | / _| | | (_)
893 * ___ _ __ ___ ___ _ __ _| | __ _| |_| |_ _ __ | |_ _ _ _ __ ___| |_ _ ___ _ __ ___
894 * / __| '_ \ / _ \/ __| |/ _` | | / _` | __| __| '__| | _| | | | '_ \ / __| __| |/ _ \| '_ \ / __|
895 * \__ \ |_) | __/ (__| | (_| | | | (_| | |_| |_| | | | | |_| | | | | (__| |_| | (_) | | | | \__ \
896 * |___/ .__/ \___|\___|_|\__,_|_| \__,_|\__|\__|_| |_| \__,_|_| |_|\___|\__|_|\___/|_| |_| |___/
899 ******************************************************************************************************/
902 * Returns whether or not the node is an AddrModeS node.
904 int is_ia32_AddrModeS(const ir_node *node) {
905 const ia32_attr_t *attr = get_ia32_attr_const(node);
906 return (attr->data.tp == ia32_AddrModeS);
910 * Returns whether or not the node is an AddrModeD node.
912 int is_ia32_AddrModeD(const ir_node *node) {
913 const ia32_attr_t *attr = get_ia32_attr_const(node);
914 return (attr->data.tp == ia32_AddrModeD);
918 * Checks if node is a Load or xLoad/vfLoad.
920 int is_ia32_Ld(const ir_node *node) {
921 int op = get_ia32_irn_opcode(node);
922 return op == iro_ia32_Load ||
923 op == iro_ia32_xLoad ||
924 op == iro_ia32_vfld ||
929 * Checks if node is a Store or xStore/vfStore.
931 int is_ia32_St(const ir_node *node) {
932 int op = get_ia32_irn_opcode(node);
933 return op == iro_ia32_Store ||
934 op == iro_ia32_Store8Bit ||
935 op == iro_ia32_xStore ||
936 op == iro_ia32_vfst ||
937 op == iro_ia32_fst ||
942 * Returns the name of the OUT register at position pos.
944 const char *get_ia32_out_reg_name(const ir_node *node, int pos) {
945 const ia32_attr_t *attr = get_ia32_attr_const(node);
947 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
948 assert(attr->slots[pos] && "No register assigned");
950 return arch_register_get_name(attr->slots[pos]);
954 * Returns the index of the OUT register at position pos within its register class.
956 int get_ia32_out_regnr(const ir_node *node, int pos) {
957 const ia32_attr_t *attr = get_ia32_attr_const(node);
959 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
960 assert(attr->slots[pos] && "No register assigned");
962 return arch_register_get_index(attr->slots[pos]);
965 void ia32_swap_left_right(ir_node *node)
967 ia32_attr_t *attr = get_ia32_attr(node);
968 ir_node *left = get_irn_n(node, n_ia32_binary_left);
969 ir_node *right = get_irn_n(node, n_ia32_binary_right);
971 assert(is_ia32_commutative(node));
972 attr->data.ins_permuted = !attr->data.ins_permuted;
973 set_irn_n(node, n_ia32_binary_left, right);
974 set_irn_n(node, n_ia32_binary_right, left);
978 * Returns the OUT register at position pos.
980 const arch_register_t *get_ia32_out_reg(const ir_node *node, int pos) {
981 const ia32_attr_t *attr = get_ia32_attr_const(node);
983 assert(pos < ARR_LEN(attr->slots) && "Invalid OUT position.");
984 assert(attr->slots[pos] && "No register assigned");
986 return attr->slots[pos];
990 * Initializes the nodes attributes.
992 void init_ia32_attributes(ir_node *node, arch_irn_flags_t flags,
993 const arch_register_req_t **in_reqs,
994 const arch_register_req_t **out_reqs,
995 const be_execution_unit_t ***execution_units,
996 int n_res, unsigned latency)
998 ir_graph *irg = get_irn_irg(node);
999 struct obstack *obst = get_irg_obstack(irg);
1000 ia32_attr_t *attr = get_ia32_attr(node);
1002 set_ia32_flags(node, flags);
1003 set_ia32_in_req_all(node, in_reqs);
1004 set_ia32_out_req_all(node, out_reqs);
1005 set_ia32_latency(node, latency);
1007 attr->exec_units = execution_units;
1009 attr->attr_type |= IA32_ATTR_ia32_attr_t;
1012 attr->out_flags = NEW_ARR_D(int, obst, n_res);
1013 memset(attr->out_flags, 0, n_res * sizeof(attr->out_flags[0]));
1015 attr->slots = NEW_ARR_D(const arch_register_t*, obst, n_res);
1016 /* void* cast to suppress an incorrect warning on MSVC */
1017 memset((void*)attr->slots, 0, n_res * sizeof(attr->slots[0]));
1021 init_ia32_x87_attributes(ir_node *res)
1024 ia32_attr_t *attr = get_ia32_attr(res);
1025 attr->attr_type |= IA32_ATTR_ia32_x87_attr_t;
1029 ia32_current_cg->do_x87_sim = 1;
1033 init_ia32_asm_attributes(ir_node *res)
1036 ia32_attr_t *attr = get_ia32_attr(res);
1037 attr->attr_type |= IA32_ATTR_ia32_asm_attr_t;
1044 init_ia32_immediate_attributes(ir_node *res, ir_entity *symconst,
1045 int symconst_sign, long offset)
1047 ia32_immediate_attr_t *attr = get_irn_generic_attr(res);
1050 attr->attr.attr_type |= IA32_ATTR_ia32_immediate_attr_t;
1052 attr->symconst = symconst;
1053 attr->sc_sign = symconst_sign;
1054 attr->offset = offset;
1058 init_ia32_copyb_attributes(ir_node *res, unsigned size) {
1059 ia32_copyb_attr_t *attr = get_irn_generic_attr(res);
1062 attr->attr.attr_type |= IA32_ATTR_ia32_copyb_attr_t;
1068 init_ia32_condcode_attributes(ir_node *res, long pnc) {
1069 ia32_condcode_attr_t *attr = get_irn_generic_attr(res);
1072 attr->attr.attr_type |= IA32_ATTR_ia32_condcode_attr_t;
1074 attr->pn_code = pnc;
1077 ir_node *get_ia32_result_proj(const ir_node *node)
1079 const ir_edge_t *edge;
1081 foreach_out_edge(node, edge) {
1082 ir_node *proj = get_edge_src_irn(edge);
1083 if(get_Proj_proj(proj) == 0) {
1090 /***************************************************************************************
1093 * _ __ ___ __| | ___ ___ ___ _ __ ___| |_ _ __ _ _ ___| |_ ___ _ __ ___
1094 * | '_ \ / _ \ / _` |/ _ \ / __/ _ \| '_ \/ __| __| '__| | | |/ __| __/ _ \| '__/ __|
1095 * | | | | (_) | (_| | __/ | (_| (_) | | | \__ \ |_| | | |_| | (__| || (_) | | \__ \
1096 * |_| |_|\___/ \__,_|\___| \___\___/|_| |_|___/\__|_| \__,_|\___|\__\___/|_| |___/
1098 ***************************************************************************************/
1100 /* default compare operation to compare attributes */
1101 int ia32_compare_attr(const ia32_attr_t *a, const ia32_attr_t *b) {
1102 if (a->data.tp != b->data.tp)
1105 if (a->data.am_scale != b->data.am_scale
1106 || a->data.am_sc_sign != b->data.am_sc_sign
1107 || a->am_offs != b->am_offs
1108 || a->am_sc != b->am_sc
1109 || a->ls_mode != b->ls_mode)
1112 /* nodes with not yet assigned entities shouldn't be CSEd (important for
1113 * unsigned int -> double conversions */
1114 if(a->data.use_frame && a->frame_ent == NULL)
1116 if(b->data.use_frame && b->frame_ent == NULL)
1119 if (a->data.use_frame != b->data.use_frame
1120 || a->frame_ent != b->frame_ent)
1123 if (a->data.tp != b->data.tp)
1126 if (a->data.except_label != b->data.except_label)
1129 if (a->data.ins_permuted != b->data.ins_permuted
1130 || a->data.cmp_unsigned != b->data.cmp_unsigned)
1136 /** Compare nodes attributes for all "normal" nodes. */
1138 int ia32_compare_nodes_attr(ir_node *a, ir_node *b)
1140 const ia32_attr_t* attr_a = get_ia32_attr_const(a);
1141 const ia32_attr_t* attr_b = get_ia32_attr_const(b);
1143 return ia32_compare_attr(attr_a, attr_b);
1146 /** Compare node attributes for nodes with condition code. */
1148 int ia32_compare_condcode_attr(ir_node *a, ir_node *b)
1150 const ia32_condcode_attr_t *attr_a;
1151 const ia32_condcode_attr_t *attr_b;
1153 if (ia32_compare_nodes_attr(a, b))
1156 attr_a = get_ia32_condcode_attr_const(a);
1157 attr_b = get_ia32_condcode_attr_const(b);
1159 if(attr_a->pn_code != attr_b->pn_code)
1165 /** Compare node attributes for CopyB nodes. */
1167 int ia32_compare_copyb_attr(ir_node *a, ir_node *b)
1169 const ia32_copyb_attr_t *attr_a;
1170 const ia32_copyb_attr_t *attr_b;
1172 if (ia32_compare_nodes_attr(a, b))
1175 attr_a = get_ia32_copyb_attr_const(a);
1176 attr_b = get_ia32_copyb_attr_const(b);
1178 if(attr_a->size != attr_b->size)
1185 /** Compare ASM node attributes. */
1187 int ia32_compare_asm_attr(ir_node *a, ir_node *b)
1189 const ia32_asm_attr_t *attr_a;
1190 const ia32_asm_attr_t *attr_b;
1192 if(ia32_compare_nodes_attr(a, b))
1195 attr_a = get_ia32_asm_attr_const(a);
1196 attr_b = get_ia32_asm_attr_const(b);
1198 if(attr_a->asm_text != attr_b->asm_text)
1204 /** Compare node attributes for Immediates. */
1206 int ia32_compare_immediate_attr(ir_node *a, ir_node *b)
1208 const ia32_immediate_attr_t *attr_a = get_ia32_immediate_attr_const(a);
1209 const ia32_immediate_attr_t *attr_b = get_ia32_immediate_attr_const(b);
1211 if(attr_a->symconst != attr_b->symconst ||
1212 attr_a->sc_sign != attr_b->sc_sign ||
1213 attr_a->offset != attr_b->offset)
1219 /** Compare node attributes for x87 nodes. */
1221 int ia32_compare_x87_attr(ir_node *a, ir_node *b)
1223 return ia32_compare_nodes_attr(a, b);
1227 /* copies the ia32 attributes */
1228 static void ia32_copy_attr(const ir_node *old_node, ir_node *new_node)
1230 ir_graph *irg = get_irn_irg(new_node);
1231 struct obstack *obst = get_irg_obstack(irg);
1232 const ia32_attr_t *attr_old = get_ia32_attr_const(old_node);
1233 ia32_attr_t *attr_new = get_ia32_attr(new_node);
1235 /* copy the attributes */
1236 memcpy(attr_new, attr_old, get_op_attr_size(get_irn_op(old_node)));
1238 /* copy out flags */
1239 attr_new->out_flags =
1240 DUP_ARR_D(int, obst, attr_old->out_flags);
1241 /* copy register assignments */
1243 DUP_ARR_D(arch_register_t*, obst, attr_old->slots);
1246 /* Include the generated constructor functions */
1247 #include "gen_ia32_new_nodes.c.inl"