2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Register param constraints and some other register handling tools.
23 * @author Christian Wuerdig
35 #include "ia32_map_regs.h"
36 #include "ia32_new_nodes.h"
37 #include "gen_ia32_regalloc_if.h"
38 #include "bearch_ia32_t.h"
39 #include "../benodesets.h"
41 static int maxnum_gpreg_args = 3; /* maximum number of int arguments passed in registers; default 3 */
42 static int maxnum_sse_args = 5; /* maximum number of float arguments passed in registers; default 5 */
44 /* this is the order of the assigned registers usesd for parameter passing */
46 const arch_register_t *gpreg_param_reg_std[] = {
47 &ia32_gp_regs[REG_EAX],
48 &ia32_gp_regs[REG_EDX],
49 &ia32_gp_regs[REG_ECX],
50 &ia32_gp_regs[REG_EBX],
51 &ia32_gp_regs[REG_EDI],
52 &ia32_gp_regs[REG_ESI]
55 const arch_register_t *gpreg_param_reg_this[] = {
56 &ia32_gp_regs[REG_ECX],
57 &ia32_gp_regs[REG_EAX],
58 &ia32_gp_regs[REG_EDX],
59 &ia32_gp_regs[REG_EBX],
60 &ia32_gp_regs[REG_EDI],
61 &ia32_gp_regs[REG_ESI]
64 const arch_register_t *fpreg_sse_param_reg_std[] = {
65 &ia32_xmm_regs[REG_XMM0],
66 &ia32_xmm_regs[REG_XMM1],
67 &ia32_xmm_regs[REG_XMM2],
68 &ia32_xmm_regs[REG_XMM3],
69 &ia32_xmm_regs[REG_XMM4],
70 &ia32_xmm_regs[REG_XMM5],
71 &ia32_xmm_regs[REG_XMM6],
72 &ia32_xmm_regs[REG_XMM7]
75 const arch_register_t *fpreg_sse_param_reg_this[] = {
76 NULL, /* in case of a "this" pointer, the first parameter must not be a float */
77 &ia32_xmm_regs[REG_XMM0],
78 &ia32_xmm_regs[REG_XMM1],
79 &ia32_xmm_regs[REG_XMM2],
80 &ia32_xmm_regs[REG_XMM3],
81 &ia32_xmm_regs[REG_XMM4],
82 &ia32_xmm_regs[REG_XMM5],
83 &ia32_xmm_regs[REG_XMM6],
84 &ia32_xmm_regs[REG_XMM7]
89 /* Mapping to store registers in firm nodes */
91 struct ia32_irn_reg_assoc {
93 const arch_register_t *reg;
96 int ia32_cmp_irn_reg_assoc(const void *a, const void *b, size_t len) {
97 const struct ia32_irn_reg_assoc *x = a;
98 const struct ia32_irn_reg_assoc *y = b;
100 return x->irn != y->irn;
103 static struct ia32_irn_reg_assoc *get_irn_reg_assoc(const ir_node *irn, set *reg_set) {
104 struct ia32_irn_reg_assoc templ;
109 hash = nodeset_hash(irn);
111 return set_insert(reg_set, &templ, sizeof(templ), hash);
114 void ia32_set_firm_reg(ir_node *irn, const arch_register_t *reg, set *reg_set) {
115 struct ia32_irn_reg_assoc *assoc = get_irn_reg_assoc(irn, reg_set);
119 const arch_register_t *ia32_get_firm_reg(const ir_node *irn, set *reg_set) {
120 struct ia32_irn_reg_assoc *assoc = get_irn_reg_assoc(irn, reg_set);
124 void ia32_build_16bit_reg_map(pmap *reg_map) {
125 pmap_insert(reg_map, &ia32_gp_regs[REG_EAX], "ax");
126 pmap_insert(reg_map, &ia32_gp_regs[REG_EBX], "bx");
127 pmap_insert(reg_map, &ia32_gp_regs[REG_ECX], "cx");
128 pmap_insert(reg_map, &ia32_gp_regs[REG_EDX], "dx");
129 pmap_insert(reg_map, &ia32_gp_regs[REG_ESI], "si");
130 pmap_insert(reg_map, &ia32_gp_regs[REG_EDI], "di");
131 pmap_insert(reg_map, &ia32_gp_regs[REG_EBP], "bp");
132 pmap_insert(reg_map, &ia32_gp_regs[REG_ESP], "sp");
135 void ia32_build_8bit_reg_map(pmap *reg_map) {
136 pmap_insert(reg_map, &ia32_gp_regs[REG_EAX], "al");
137 pmap_insert(reg_map, &ia32_gp_regs[REG_EBX], "bl");
138 pmap_insert(reg_map, &ia32_gp_regs[REG_ECX], "cl");
139 pmap_insert(reg_map, &ia32_gp_regs[REG_EDX], "dl");
142 void ia32_build_8bit_reg_map_high(pmap *reg_map) {
143 pmap_insert(reg_map, &ia32_gp_regs[REG_EAX], "ah");
144 pmap_insert(reg_map, &ia32_gp_regs[REG_EBX], "bh");
145 pmap_insert(reg_map, &ia32_gp_regs[REG_ECX], "ch");
146 pmap_insert(reg_map, &ia32_gp_regs[REG_EDX], "dh");
149 const char *ia32_get_mapped_reg_name(pmap *reg_map, const arch_register_t *reg) {
150 pmap_entry *e = pmap_find(reg_map, (void *)reg);
152 //assert(e && "missing map init?");
154 printf("FIXME: ia32map_regs.c:122: returning fake register name for ia32 with 32 register\n");
162 * Check all parameters and determine the maximum number of parameters
163 * to pass in gp regs resp. in fp regs.
165 int ia32_get_n_regparam_class(ia32_code_gen_t *cg, int n, ir_mode **modes)
173 max_fp_regs = maxnum_sse_args;
178 for (i = 0; i < n; i++) {
179 if (mode_is_int(modes[i]) || mode_is_reference(modes[i])) {
181 } else if (mode_is_float(modes[i])) {
184 panic("Unknown parameter mode encountered");
187 if (n_int >= maxnum_gpreg_args || n_float >= max_fp_regs)
196 * Returns the register for parameter nr.
198 * @param n The number of parameters
199 * @param modes The list of the parameter modes
200 * @param nr The number of the parameter to return the requirements for
201 * @param cc The calling convention
202 * @return The register
204 const arch_register_t *ia32_get_RegParam_reg(ia32_code_gen_t *cg, unsigned cc,
205 unsigned nr, ir_mode *mode)
207 if(mode_is_float(mode)) {
210 assert(nr < maxnum_sse_args);
211 if(cc & cc_this_call) {
212 return fpreg_sse_param_reg_this[nr];
214 return fpreg_sse_param_reg_std[nr];
217 assert(mode_is_int(mode) || mode_is_reference(mode));
219 if(cc & cc_this_call) {
220 assert(nr < maxnum_gpreg_args);
221 return gpreg_param_reg_this[nr];
223 return gpreg_param_reg_std[nr];