2 * Copyright (C) 1995-2007 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Handles fpu rounding modes
23 * @author Matthias Braun
26 * The problem we deal with here is that the x86 ABI says the user can control
27 * the fpu rounding mode, which means that when we do some operations like float
28 * to int conversion which are specified as truncation in the C standard we have
29 * to spill, change and restore the fpu rounding mode between spills.
36 #include "ia32_new_nodes.h"
37 #include "gen_ia32_regalloc_if.h"
44 #include "../beirgmod.h"
45 #include "../bearch_t.h"
46 #include "../besched.h"
48 #include "../benode_t.h"
49 #include "../bestate.h"
50 #include "../beutil.h"
51 #include "../bessaconstr.h"
52 #include "../beirg_t.h"
54 static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
57 ia32_code_gen_t *cg = env;
58 ir_node *spill = NULL;
60 if(force == 1 || !is_ia32_ChangeCW(state)) {
61 ir_graph *irg = get_irn_irg(state);
62 ir_node *block = get_nodes_block(state);
63 ir_node *noreg = ia32_new_NoReg_gp(cg);
64 ir_node *nomem = new_NoMem();
65 ir_node *frame = get_irg_frame(irg);
67 spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, state,
69 set_ia32_am_support(spill, ia32_am_Dest);
70 set_ia32_op_type(spill, ia32_AddrModeD);
71 set_ia32_am_flavour(spill, ia32_B);
72 set_ia32_ls_mode(spill, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
73 set_ia32_use_frame(spill);
75 sched_add_after(after, spill);
81 static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
82 ir_node *spill, ir_node *before,
85 ia32_code_gen_t *cg = env;
86 ir_graph *irg = get_irn_irg(state);
87 ir_node *block = get_nodes_block(before);
88 ir_node *frame = get_irg_frame(irg);
89 ir_node *noreg = ia32_new_NoReg_gp(cg);
90 ir_node *reload = NULL;
93 reload = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, spill);
94 set_ia32_am_support(reload, ia32_am_Source);
95 set_ia32_op_type(reload, ia32_AddrModeS);
96 set_ia32_am_flavour(reload, ia32_B);
97 set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
98 set_ia32_use_frame(reload);
99 arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
101 sched_add_before(before, reload);
103 ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
104 ir_node *nomem = new_NoMem();
105 ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
107 assert(last_state != NULL);
108 cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, last_state,
110 set_ia32_am_support(cwstore, ia32_am_Dest);
111 set_ia32_op_type(cwstore, ia32_AddrModeD);
112 set_ia32_am_flavour(cwstore, ia32_B);
113 set_ia32_ls_mode(cwstore, lsmode);
114 set_ia32_use_frame(cwstore);
115 sched_add_before(before, cwstore);
117 load = new_rd_ia32_Load(NULL, irg, block, frame, noreg, cwstore);
118 set_ia32_am_support(load, ia32_am_Source);
119 set_ia32_op_type(load, ia32_AddrModeS);
120 set_ia32_am_flavour(load, ia32_B);
121 set_ia32_ls_mode(load, lsmode);
122 set_ia32_use_frame(load);
123 sched_add_before(before, load);
125 load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
126 sched_add_before(before, load_res);
128 /* TODO: make the actual mode configurable in ChangeCW... */
129 or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, load_res, noreg,
131 set_ia32_Immop_tarval(or, new_tarval_from_long(3072, mode_Iu));
132 sched_add_before(before, or);
134 store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, or, nomem);
135 set_ia32_am_support(store, ia32_am_Dest);
136 set_ia32_op_type(store, ia32_AddrModeD);
137 set_ia32_am_flavour(store, ia32_B);
138 set_ia32_ls_mode(store, lsmode);
139 set_ia32_use_frame(store);
140 sched_add_before(before, store);
142 fldcw = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, store);
143 set_ia32_am_support(fldcw, ia32_am_Source);
144 set_ia32_op_type(fldcw, ia32_AddrModeS);
145 set_ia32_am_flavour(fldcw, ia32_B);
146 set_ia32_ls_mode(fldcw, lsmode);
147 set_ia32_use_frame(fldcw);
148 arch_set_irn_register(cg->arch_env, fldcw, &ia32_fp_cw_regs[REG_FPCW]);
149 sched_add_before(before, fldcw);
157 typedef struct collect_fpu_mode_nodes_env_t {
158 const arch_env_t *arch_env;
159 ir_node **state_nodes;
160 } collect_fpu_mode_nodes_env_t;
163 void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
165 collect_fpu_mode_nodes_env_t *env = data;
167 const arch_register_t *reg = arch_get_irn_register(env->arch_env, node);
168 if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
169 ARR_APP1(ir_node*, env->state_nodes, node);
174 void rewire_fpu_mode_nodes(be_irg_t *birg)
176 collect_fpu_mode_nodes_env_t env;
177 be_ssa_construction_env_t senv;
178 const arch_register_t *reg = &ia32_fp_cw_regs[REG_FPCW];
179 ir_graph *irg = be_get_birg_irg(birg);
180 ir_node *initial_value;
182 be_lv_t *lv = be_get_birg_liveness(birg);
185 /* do ssa construction for the fpu modes */
186 env.arch_env = be_get_birg_arch_env(birg);
187 env.state_nodes = NEW_ARR_F(ir_node*, 0);
188 irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
190 initial_value = be_abi_get_ignore_irn(birg->abi, reg);
192 /* nothing needs to be done, in fact we must not continue as for endless
193 * loops noone is using the initial_value and it will point to a bad node
196 if(ARR_LEN(env.state_nodes) == 0) {
197 DEL_ARR_F(env.state_nodes);
201 be_ssa_construction_init(&senv, birg);
202 be_ssa_construction_add_copies(&senv, env.state_nodes,
203 ARR_LEN(env.state_nodes));
204 be_ssa_construction_fix_users(&senv, initial_value);
207 be_ssa_construction_update_liveness_phis(&senv, lv);
208 be_liveness_update(lv, initial_value);
209 len = ARR_LEN(env.state_nodes);
210 for(i = 0; i < len; ++i) {
211 be_liveness_update(lv, env.state_nodes[i]);
215 /* set registers for the phis */
216 phis = be_ssa_construction_get_new_phis(&senv);
218 for(i = 0; i < len; ++i) {
219 ir_node *phi = phis[i];
220 be_set_phi_flags(env.arch_env, phi, arch_irn_flags_ignore);
221 arch_set_irn_register(env.arch_env, phi, reg);
223 be_ssa_construction_destroy(&senv);
224 DEL_ARR_F(env.state_nodes);
227 void ia32_setup_fpu_mode(ia32_code_gen_t *cg)
229 /* do ssa construction for the fpu modes */
230 rewire_fpu_mode_nodes(cg->birg);
232 /* ensure correct fpu mode for operations */
233 be_assure_state(cg->birg, &ia32_fp_cw_regs[REG_FPCW],
234 cg, create_fpu_mode_spill, create_fpu_mode_reload);