3 * @brief Handles fpu rounding modes
4 * @author Matthias Braun
7 * The problem we deal with here is that the x86 ABI says the user can control
8 * the fpu rounding mode, which means that when we do some operations like float
9 * to int conversion which are specified as truncation in the C standard we have
10 * to spill, change and restore the fpu rounding mode between spills.
17 #include "ia32_new_nodes.h"
18 #include "gen_ia32_regalloc_if.h"
25 #include "../beirgmod.h"
26 #include "../bearch_t.h"
27 #include "../besched.h"
29 #include "../benode_t.h"
30 #include "../bestate.h"
31 #include "../beutil.h"
32 #include "../bessaconstr.h"
33 #include "../beirg_t.h"
35 static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
38 ia32_code_gen_t *cg = env;
39 ir_node *spill = NULL;
41 if(force == 1 || !is_ia32_ChangeCW(state)) {
42 ir_graph *irg = get_irn_irg(state);
43 ir_node *block = get_nodes_block(state);
44 ir_node *noreg = ia32_new_NoReg_gp(cg);
45 ir_node *nomem = new_NoMem();
46 ir_node *frame = get_irg_frame(irg);
48 spill = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, state,
50 set_ia32_am_support(spill, ia32_am_Dest);
51 set_ia32_op_type(spill, ia32_AddrModeD);
52 set_ia32_am_flavour(spill, ia32_B);
53 set_ia32_ls_mode(spill, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
54 set_ia32_use_frame(spill);
56 sched_add_after(after, spill);
62 static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
63 ir_node *spill, ir_node *before,
66 ia32_code_gen_t *cg = env;
67 ir_graph *irg = get_irn_irg(state);
68 ir_node *block = get_nodes_block(before);
69 ir_node *frame = get_irg_frame(irg);
70 ir_node *noreg = ia32_new_NoReg_gp(cg);
71 ir_node *reload = NULL;
74 reload = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, spill);
75 set_ia32_am_support(reload, ia32_am_Source);
76 set_ia32_op_type(reload, ia32_AddrModeS);
77 set_ia32_am_flavour(reload, ia32_B);
78 set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
79 set_ia32_use_frame(reload);
80 arch_set_irn_register(cg->arch_env, reload, &ia32_fp_cw_regs[REG_FPCW]);
82 sched_add_before(before, reload);
84 ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
85 ir_node *nomem = new_NoMem();
86 ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
88 assert(last_state != NULL);
89 cwstore = new_rd_ia32_FnstCW(NULL, irg, block, frame, noreg, last_state,
91 set_ia32_am_support(cwstore, ia32_am_Dest);
92 set_ia32_op_type(cwstore, ia32_AddrModeD);
93 set_ia32_am_flavour(cwstore, ia32_B);
94 set_ia32_ls_mode(cwstore, lsmode);
95 set_ia32_use_frame(cwstore);
96 sched_add_before(before, cwstore);
98 load = new_rd_ia32_Load(NULL, irg, block, frame, noreg, cwstore);
99 set_ia32_am_support(load, ia32_am_Source);
100 set_ia32_op_type(load, ia32_AddrModeS);
101 set_ia32_am_flavour(load, ia32_B);
102 set_ia32_ls_mode(load, lsmode);
103 set_ia32_use_frame(load);
104 sched_add_before(before, load);
106 load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
107 sched_add_before(before, load_res);
109 /* TODO: make the actual mode configurable in ChangeCW... */
110 or = new_rd_ia32_Or(NULL, irg, block, noreg, noreg, load_res, noreg,
112 set_ia32_Immop_tarval(or, new_tarval_from_long(3072, mode_Iu));
113 sched_add_before(before, or);
115 store = new_rd_ia32_Store(NULL, irg, block, frame, noreg, or, nomem);
116 set_ia32_am_support(store, ia32_am_Dest);
117 set_ia32_op_type(store, ia32_AddrModeD);
118 set_ia32_am_flavour(store, ia32_B);
119 set_ia32_ls_mode(store, lsmode);
120 set_ia32_use_frame(store);
121 sched_add_before(before, store);
123 fldcw = new_rd_ia32_FldCW(NULL, irg, block, frame, noreg, store);
124 set_ia32_am_support(fldcw, ia32_am_Source);
125 set_ia32_op_type(fldcw, ia32_AddrModeS);
126 set_ia32_am_flavour(fldcw, ia32_B);
127 set_ia32_ls_mode(fldcw, lsmode);
128 set_ia32_use_frame(fldcw);
129 arch_set_irn_register(cg->arch_env, fldcw, &ia32_fp_cw_regs[REG_FPCW]);
130 sched_add_before(before, fldcw);
138 typedef struct collect_fpu_mode_nodes_env_t {
139 const arch_env_t *arch_env;
140 ir_node **state_nodes;
141 } collect_fpu_mode_nodes_env_t;
144 void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
146 collect_fpu_mode_nodes_env_t *env = data;
148 const arch_register_t *reg = arch_get_irn_register(env->arch_env, node);
149 if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
150 ARR_APP1(ir_node*, env->state_nodes, node);
155 void rewire_fpu_mode_nodes(be_irg_t *birg)
157 collect_fpu_mode_nodes_env_t env;
158 be_ssa_construction_env_t senv;
159 const arch_register_t *reg = &ia32_fp_cw_regs[REG_FPCW];
160 ir_graph *irg = be_get_birg_irg(birg);
161 ir_node *initial_value;
163 be_lv_t *lv = be_get_birg_liveness(birg);
166 /* do ssa construction for the fpu modes */
167 env.arch_env = be_get_birg_arch_env(birg);
168 env.state_nodes = NEW_ARR_F(ir_node*, 0);
169 irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
171 initial_value = be_abi_get_ignore_irn(birg->abi, reg);
173 /* nothing needs to be done, in fact we must not continue as for endless
174 * loops noone is using the initial_value and it will point to a bad node
177 if(ARR_LEN(env.state_nodes) == 0) {
178 DEL_ARR_F(env.state_nodes);
182 be_ssa_construction_init(&senv, birg);
183 be_ssa_construction_add_copies(&senv, env.state_nodes,
184 ARR_LEN(env.state_nodes));
185 be_ssa_construction_fix_users(&senv, initial_value);
188 be_ssa_construction_update_liveness_phis(&senv, lv);
189 be_liveness_update(lv, initial_value);
190 len = ARR_LEN(env.state_nodes);
191 for(i = 0; i < len; ++i) {
192 be_liveness_update(lv, env.state_nodes[i]);
196 /* set registers for the phis */
197 phis = be_ssa_construction_get_new_phis(&senv);
199 for(i = 0; i < len; ++i) {
200 ir_node *phi = phis[i];
201 be_set_phi_flags(env.arch_env, phi, arch_irn_flags_ignore);
202 arch_set_irn_register(env.arch_env, phi, reg);
204 be_ssa_construction_destroy(&senv);
205 DEL_ARR_F(env.state_nodes);
208 void ia32_setup_fpu_mode(ia32_code_gen_t *cg)
210 /* do ssa construction for the fpu modes */
211 rewire_fpu_mode_nodes(cg->birg);
213 /* ensure correct fpu mode for operations */
214 be_assure_state(cg->birg, &ia32_fp_cw_regs[REG_FPCW],
215 cg, create_fpu_mode_spill, create_fpu_mode_reload);