2 * Copyright (C) 1995-2008 University of Karlsruhe. All right reserved.
4 * This file is part of libFirm.
6 * This file may be distributed and/or modified under the terms of the
7 * GNU General Public License version 2 as published by the Free Software
8 * Foundation and appearing in the file LICENSE.GPL included in the
9 * packaging of this file.
11 * Licensees holding valid libFirm Professional Edition licenses may use
12 * this file in accordance with the libFirm Commercial License.
13 * Agreement provided with the Software.
15 * This file is provided AS IS with NO WARRANTY OF ANY KIND, INCLUDING THE
16 * WARRANTY OF DESIGN, MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * @brief Handles fpu rounding modes
23 * @author Matthias Braun
26 * The problem we deal with here is that the x86 ABI says the user can control
27 * the fpu rounding mode, which means that when we do some operations like float
28 * to int conversion which are specified as truncation in the C standard we have
29 * to spill, change and restore the fpu rounding mode between spills.
34 #include "ia32_new_nodes.h"
35 #include "ia32_architecture.h"
36 #include "gen_ia32_regalloc_if.h"
43 #include "../beirgmod.h"
44 #include "../bearch_t.h"
45 #include "../besched.h"
47 #include "../benode_t.h"
48 #include "../bestate.h"
49 #include "../beutil.h"
50 #include "../bessaconstr.h"
51 #include "../beirg_t.h"
53 static ir_entity *fpcw_round = NULL;
54 static ir_entity *fpcw_truncate = NULL;
56 static ir_entity *create_ent(int value, const char *name)
58 ir_mode *mode = mode_Hu;
59 ir_type *type = new_type_primitive(new_id_from_str("_fpcw_type"), mode);
60 ir_type *glob = get_glob_type();
66 set_type_alignment_bytes(type, 4);
68 tv = new_tarval_from_long(value, mode);
69 ent = new_entity(glob, new_id_from_str(name), type);
70 set_entity_ld_ident(ent, get_entity_ident(ent));
71 set_entity_visibility(ent, visibility_local);
72 set_entity_variability(ent, variability_constant);
73 set_entity_allocation(ent, allocation_static);
75 cnst_irg = get_const_code_irg();
76 cnst = new_r_Const(cnst_irg, get_irg_start_block(cnst_irg), mode, tv);
77 set_atomic_ent_value(ent, cnst);
82 static void create_fpcw_entities(void)
84 fpcw_round = create_ent(0xc7f, "_fpcw_round");
85 fpcw_truncate = create_ent(0x37f, "_fpcw_truncate");
88 static ir_node *create_fpu_mode_spill(void *env, ir_node *state, int force,
91 ia32_code_gen_t *cg = env;
92 ir_node *spill = NULL;
94 /* we don't spill the fpcw in unsafe mode */
95 if(ia32_cg_config.use_unsafe_floatconv) {
96 ir_node *block = get_nodes_block(state);
97 if(force == 1 || !is_ia32_ChangeCW(state)) {
98 ir_node *spill = new_bd_ia32_FnstCWNOP(NULL, block, state);
99 sched_add_after(after, spill);
105 if(force == 1 || !is_ia32_ChangeCW(state)) {
106 ir_graph *irg = get_irn_irg(state);
107 ir_node *block = get_nodes_block(state);
108 ir_node *noreg = ia32_new_NoReg_gp(cg);
109 ir_node *nomem = new_NoMem();
110 ir_node *frame = get_irg_frame(irg);
112 spill = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem, state);
113 set_ia32_op_type(spill, ia32_AddrModeD);
114 /* use mode_Iu, as movl has a shorter opcode than movw */
115 set_ia32_ls_mode(spill, mode_Iu);
116 set_ia32_use_frame(spill);
118 sched_add_after(after, spill);
124 static ir_node *create_fldcw_ent(ia32_code_gen_t *cg, ir_node *block,
127 ir_node *nomem = new_NoMem();
128 ir_node *noreg = ia32_new_NoReg_gp(cg);
131 reload = new_bd_ia32_FldCW(NULL, block, noreg, noreg, nomem);
132 set_ia32_op_type(reload, ia32_AddrModeS);
133 set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
134 set_ia32_am_sc(reload, entity);
135 set_ia32_use_frame(reload);
136 arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]);
141 static ir_node *create_fpu_mode_reload(void *env, ir_node *state,
142 ir_node *spill, ir_node *before,
145 ia32_code_gen_t *cg = env;
146 ir_graph *irg = get_irn_irg(state);
147 ir_node *block = get_nodes_block(before);
148 ir_node *frame = get_irg_frame(irg);
149 ir_node *noreg = ia32_new_NoReg_gp(cg);
150 ir_node *reload = NULL;
152 if(ia32_cg_config.use_unsafe_floatconv) {
153 if(fpcw_round == NULL) {
154 create_fpcw_entities();
157 reload = create_fldcw_ent(cg, block, fpcw_round);
159 reload = create_fldcw_ent(cg, block, fpcw_truncate);
161 sched_add_before(before, reload);
166 reload = new_bd_ia32_FldCW(NULL, block, frame, noreg, spill);
167 set_ia32_op_type(reload, ia32_AddrModeS);
168 set_ia32_ls_mode(reload, ia32_reg_classes[CLASS_ia32_fp_cw].mode);
169 set_ia32_use_frame(reload);
170 arch_set_irn_register(reload, &ia32_fp_cw_regs[REG_FPCW]);
172 sched_add_before(before, reload);
174 ir_mode *lsmode = ia32_reg_classes[CLASS_ia32_fp_cw].mode;
175 ir_node *nomem = new_NoMem();
176 ir_node *cwstore, *load, *load_res, *or, *store, *fldcw;
179 assert(last_state != NULL);
180 cwstore = new_bd_ia32_FnstCW(NULL, block, frame, noreg, nomem,
182 set_ia32_op_type(cwstore, ia32_AddrModeD);
183 set_ia32_ls_mode(cwstore, lsmode);
184 set_ia32_use_frame(cwstore);
185 sched_add_before(before, cwstore);
187 load = new_bd_ia32_Load(NULL, block, frame, noreg, cwstore);
188 set_ia32_op_type(load, ia32_AddrModeS);
189 set_ia32_ls_mode(load, lsmode);
190 set_ia32_use_frame(load);
191 sched_add_before(before, load);
193 load_res = new_r_Proj(irg, block, load, mode_Iu, pn_ia32_Load_res);
195 /* TODO: make the actual mode configurable in ChangeCW... */
196 or_const = new_bd_ia32_Immediate(NULL, get_irg_start_block(irg),
198 arch_set_irn_register(or_const, &ia32_gp_regs[REG_GP_NOREG]);
199 or = new_bd_ia32_Or(NULL, block, noreg, noreg, nomem, load_res,
201 sched_add_before(before, or);
203 store = new_bd_ia32_Store(NULL, block, frame, noreg, nomem, or);
204 set_ia32_op_type(store, ia32_AddrModeD);
205 /* use mode_Iu, as movl has a shorter opcode than movw */
206 set_ia32_ls_mode(store, mode_Iu);
207 set_ia32_use_frame(store);
208 sched_add_before(before, store);
210 fldcw = new_bd_ia32_FldCW(NULL, block, frame, noreg, store);
211 set_ia32_op_type(fldcw, ia32_AddrModeS);
212 set_ia32_ls_mode(fldcw, lsmode);
213 set_ia32_use_frame(fldcw);
214 arch_set_irn_register(fldcw, &ia32_fp_cw_regs[REG_FPCW]);
215 sched_add_before(before, fldcw);
223 typedef struct collect_fpu_mode_nodes_env_t {
224 ir_node **state_nodes;
225 } collect_fpu_mode_nodes_env_t;
227 static void collect_fpu_mode_nodes_walker(ir_node *node, void *data)
229 collect_fpu_mode_nodes_env_t *env = data;
230 const arch_register_t *reg;
232 if(!mode_is_data(get_irn_mode(node)))
235 reg = arch_get_irn_register(node);
236 if(reg == &ia32_fp_cw_regs[REG_FPCW] && !is_ia32_ChangeCW(node)) {
237 ARR_APP1(ir_node*, env->state_nodes, node);
242 void rewire_fpu_mode_nodes(be_irg_t *birg)
244 collect_fpu_mode_nodes_env_t env;
245 be_ssa_construction_env_t senv;
246 const arch_register_t *reg = &ia32_fp_cw_regs[REG_FPCW];
247 ir_graph *irg = be_get_birg_irg(birg);
248 ir_node *initial_value;
250 be_lv_t *lv = be_get_birg_liveness(birg);
253 /* do ssa construction for the fpu modes */
254 env.state_nodes = NEW_ARR_F(ir_node*, 0);
255 irg_walk_graph(irg, collect_fpu_mode_nodes_walker, NULL, &env);
257 initial_value = be_abi_get_ignore_irn(birg->abi, reg);
259 /* nothing needs to be done, in fact we must not continue as for endless
260 * loops noone is using the initial_value and it will point to a bad node
263 if(ARR_LEN(env.state_nodes) == 0) {
264 DEL_ARR_F(env.state_nodes);
268 be_ssa_construction_init(&senv, birg);
269 be_ssa_construction_add_copies(&senv, env.state_nodes,
270 ARR_LEN(env.state_nodes));
271 be_ssa_construction_fix_users(&senv, initial_value);
274 be_ssa_construction_update_liveness_phis(&senv, lv);
275 be_liveness_update(lv, initial_value);
276 len = ARR_LEN(env.state_nodes);
277 for(i = 0; i < len; ++i) {
278 be_liveness_update(lv, env.state_nodes[i]);
281 be_liveness_invalidate(birg->lv);
284 /* set registers for the phis */
285 phis = be_ssa_construction_get_new_phis(&senv);
287 for(i = 0; i < len; ++i) {
288 ir_node *phi = phis[i];
289 arch_set_irn_register(phi, reg);
291 be_ssa_construction_destroy(&senv);
292 DEL_ARR_F(env.state_nodes);
294 be_liveness_invalidate(be_get_birg_liveness(birg));
297 void ia32_setup_fpu_mode(ia32_code_gen_t *cg)
299 /* do ssa construction for the fpu modes */
300 rewire_fpu_mode_nodes(cg->birg);
302 /* ensure correct fpu mode for operations */
303 be_assure_state(cg->birg, &ia32_fp_cw_regs[REG_FPCW],
304 cg, create_fpu_mode_spill, create_fpu_mode_reload);